3-Bipolar Junction Transistors

Transistor Construction
The transistor is a three-layer semiconductor device consisting of either two n- and one p-type
layers of material(npn transistor) or two p- and one n-type layers of material(pnp transistor).
The outer layers of the transistor widths much greater than those of the sandwiched p- or ntype material
The doping of the sandwiched layer is also considerably less than that of the outer layers, this
lower doping level decreases the conductivity (increases the resistance) of this material by
limiting the number of free carriers

Fig (3-1) (a)pnp (b) npn.

The terminals have been indicated by E for emitter, C for collector, and B for base.
The abbreviation BJT, from bipolar junction transistor, is often applied to this three-terminal
device.
The term bipolar reflects the fact that holes and electrons participate in the injection
process into the oppositely polarized material. If only one carrier is employed (electron or
hole), it is considered a unipolar device.
Transistor Operation
In Fig (3-2) the pnp transistor has been redrawn without the base-to-collector bias.
The depletion region has been reduced in width due to the applied bias, resulting a heavy flow
of majority carriers from the p- to the n-type material.
Let us now remove the base-to-emitter bias of the pnp transistor. The flow of majority carriers
is zero, resulting in only a minority-carrier flow.
i.e. one p-n junction of a transistor is reverse biased, while the other is forward biased.

Fig (3-2) Forward-biased of a pnp CB tr

Fig (3-3) Reverse-biased of a pnp CB tr

In Fig (3-4) both biasing potentials have been applied to a pnp transistor, with the resulting
majority- and minority-carrier flow indicated. A large number of majority carriers will diffuse
across the forward-biased p-n junction into the n-type material.

49

Fig (3-4) Majority and minority carrier flow of a pnp transistor

Since the sandwiched n-type material is very thin and has a low conductivity, a very small
number of these carriers will take this path of high resistance obtaining the base current IB
in A, the magnitude of the emitter IE and collector IC currents in mA
Applying KCL to the transistor of Fig (3-4) as if it were a single node, we obtain

[3-1]
The IC has two components-the majority and minority carriers. The minority-current component
is called the leakage current ICO (CO = Current with emitter terminal Open). Therefore:

[3-2]
IC
ICO

in mA
in A or nA , is temperature sensitive

Common-Base Configuration (CB)

Fig (3-5) Notation and symbols used with the CB (a) pnp transistor (b) npn transistor.
For fixed values of VCB in the CB configuration the ratio of a small change in IC to a small
change in IE is commonly called the common-base short-circuit amplification factor and
is given by the symbol (alpha).

50

[3-3]
The term short circuit indicates that the load is short-circuited when is determined.
Typical values of vary from 0.90 to 0.998.
For most practical applications can be obtained using the following equation:
[3-4]
Therefore Eqs [3-2] be:
[3-5]
The current amplification IC / IE is always less than 1 for the CB configuration. This latter
characteristic should be obvious since IC = IE and is always less than 1.
Two sets of characteristics are necessary to represent the behavior of the pnp CB transistor
1--the driving point (or input)
2--the output set.
The output or collector characteristics of Fig (3-6a) relate the collector (output) current to the
collector-to-base (output) voltage and (input) emitter current. The collector characteristics
have three basic regions of interest:
1--the active region
In the active region the collector junction is reverse-biased, while the emitter junction is
forward-biased, it is the only region employed for the amplification of signals with minimum
distortion.
-When the emitter current IE =0 the collector current IC = ICO ( emitter input circuit is open)
-When the emitter current increases above Zero, IC=IE (in active region)

[3-6]

Fig (3-6) pnp CB transister (a) O/P Collector characteristics (b) I/P Emitter characteristics

51

Fig (3-7) Reverse saturation current

2--the cutoff region
In cut off region the collector and emitter junction are both reverse biased, resulting in
negligible collector current.
3--and saturation region
In saturation region the collector & emitter junction are forward biased, resulting in the
exponential change in the collector current with small change in collector to base potential.
For fixed values of collector voltage VCB in the input characteristics fig(3-6b) as VEB increases,
the IE will increased , Increasing levels of VCB result in a reduced level of VEB to establish
the same current.
[3-7]
Example 1:
Using the characteristic of fig (3-6):

Solution:

The proper biasing of the CB determined using the approximation IC IE and assuming for
the moment that IB 0A.

Fig (3-8) the configuration for the pnp CB transistor.

52

Common-Emitter Configuration (CE)

Fig (3-9) Notation and symbols used with CE configuration (a)npn transistor(b)pnp transistor
Two sets of characteristics are again necessary to describe the behavior of CE configuration:
-One for the input or base circuit.
-One for the output or collector circuit. Both are shown in Fig (3-10)

Fig (3-10) npn CE transistor (a) O/P Collector characteristics (b) I/P Base characteristic
-In the active region the collector junction is reverse biased, while the emitter junction is
forward-biased, this region employed for voltage, current, or power amplification.
-in cutoff region for the CE, IC = lCEO determined the cutoff for the CE configuration
For C.E
For C.B
The reason for this is,

IC 0 when
IB = 0
IC = ICO when IE = 0
Eqs[3-5]

But

Eqs[3-1]

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[3-8]
If we consider the case where IB=0, and substitute this value in Eqs.[3-8],then

[3-9]

And
The collector current defined by Eqs[3-9] will be assigned the notation indicated by Eqs[3-10].

[3-10]
In Fig (3-11) the conditions surrounding this newly defined current are demonstrated.

Fig (3-11) Circuit related to ICEO condition

The CE forward-current amplification factor is

[3-11]
The value obtained for beta () from Eqs[3-11] is called ac or dynamic value.

[3-12]
The value obtained for from Eqs[3-12] is called the dc beta, since IC and IB in Eqs[3-12] are
dc values, vary from 20 to 600.
Eqs[3-12]
Eqs[3-4]
Eqs[3-1]

54

Substituting:

And dividing by IC

We obtain:
[3-13]
or
[3-14]

Then
[3-15]
Example 2:
Using the characteristics of fig (3-10)
Solution:

Example 3:

55

Solution:

The input char for CE & CB configuration is, the increase in input current is due to an
increase in majority carriers crossing the B-to-E junction with increasing forward-bias potential.
Common-Collector Configuration (CC)
The CC configuration is used primarily for impedance matching purposes since it has a high
input impedance and low output impedance, opposite to that which is true of the CB & CE
configurations.

Fig (3-12) Notation and symbols used with CC configuration(a)pnp transistor(b)npn transistor
The output characteristics of the CC configuration are the same as for the CE configuration.
Transistor Maximum Ratings
The standard transistor data sheet will include at least three maximum ratings:
-Collector dissipation (power), collector voltage, And collector current
The power or dissipation rating is the product of the collector voltage and current.
For the CE configuration

[3-16]
-For the CB configuration the collector dissipation is determined by the following equation.

[3-17]

56

Summary

Biasing the two PN junction in an NPN transistor

The NPN transistor with both bias sources connected

Equivalent NPN transistor diagrams

Equivalent PNP transistor diagrams

57

ICBO is the collector current that flows when the emitter is open

Input and output voltage in NPN and PNP common-base transistors

Common-emitter bias arrangements

Input and output voltages and currents for NPN and PNP transistor in the CE configuration

58

VCE ~ VCB + 0.7 for Si , when VCE is reduced to about 0.7, then VCB ~ 0 and the collector-base
junction is no longer reverse biased.

CC bias configuration

Input and output voltage and current in the CC configuration

59

4-DC Biasing (BJTS)

To use these devices for amplification of voltage or current, or as control (on or off) elements, it
is necessary first to bias the device. The usual reason for this biasing is to turn the device on
and to place it in operation in the region of its characteristic where the device operates most
linearly.
Operating point:
Since the aim of biasing is to achieve a certain condition of current and voltage called the
operating point (quiescent point or Q-point).
Operating region is the area of current or voltage within the maximum limits for the particular
device. These maximum ratings are indicated on the characteristic of Fig (4-1) by a horizontal
line for the maximum current, Imax and a vertical line for the maximum voltage Vmax

Fig (4-1) various operating points

Operating in the linear regions, cutoff region, and saturation region of the BJT characteristic
are provided as follows:
1. Linear-region operation:
Base-emitter forward biased, Base-collector reverse biased, IC=IB , is true only in this region
2. Cutoff-region operation:
Base-emitter reverse biased
3. Saturation-region operation:
Base-emitter forward biased, Base-collector forward biased
Fixed-Bias Circuit
The fixed-bias circuit shown in Fig (4-2) provides a relatively straightforward and simple
starting point in the dc bias considerations.
It is possible to consider the biasing of a BJT by separately analyzing the base-emitter and
the base-collector dc bias loops.

Fig (4-2) Fixed-bias circuit

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Forward Bias of Base-Emitter

Consider the base-emitter circuit loop shown, writing the KVL equation for the loop, we get:

Fig (4-3) Base-emitter loop

We can solve the foregoing equation for the base current IB
[4-1]
Since the supply voltage VCC and VBE are fixed values, as a good approximation we may even
neglect the few tenths of a volt drop (VBE) obtaining the simplified form for the base current IB
[4-2]
Reverse Bias of Base-Collector
The collector-emitter section (Fig4-4) consists of the supply battery, the collector resistor, and
the transistor collector-emitter junction. The currents through the collector and emitter are
about the same since IB is small in comparison to either

Fig (4-4) Collector-Emitter loop

For linear amplifier operation the IC is related to the IB by the transistor current gain,
[4-3]
Calculating voltage drops in the collector-emitter loop, we get
[4-4]
Example 1: Compute the dc bias voltages and currents for the circuit of Fig (4-5).

Fig (4-5) dc fixed-bias for Ex 1:

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Solution:

Example 2: Compute the collector voltage and current for the circuit of fig (4-6).

Fig (4-6) Circuit for Example 2:

Solution:

DC Bias Circuit with emitter resistor

The dc bias circuit of Fig (4-7) contains RE to provide better bias stability than the fixed-bias
circuit

Fig (4-7) emitter-stabilization resistor

Base-Emitter Loop
A partial circuit diagram of the base-emitter loop is shown in Fig (4-8).

Fig (4-8) Base-emitter loop with emitter resistor.

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Writing KVL equation for the loop, we get

[4-5]
Collector-Emitter Loop
The collector emitter loop is shown in fig (4-9).writing KVL for this loop we get

Fig (4-9) Collector-Emitter loop with emitter resistor.

The collector current IC is calculated using the relation

[4-6]
[4-7]
[4-8]
The voltage at which the transistor is based is measured from collector to emitter VCE
Example 3: Calculate the dc bias voltage VCE and current IC in the circuit of Fig (4-10)

Fig (4-10) E-stabilized bias cct for Ex3: & Ex4:

Solution:

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Example 4: Calculate the value of collector resistor RC needed VC = 10 v, using Fig (4-10)
Solution:

Note: that IB and IC are still the same values as calculated in Ex 3: using Eq[4-11]

Improved Bias Stability

The addition of the emitter resistor to the dc bias of the BJT improved stability ( the dc bias
currents and voltages remain closer to where they were set by the circuit even when outside
conditions supply voltage, temperature, and transistor beta change)
Example 5: Prepare a table comparing the bias voltage and currents of the circuit of Fig (45) for the given value of = 50 and for a new value of = 100.
Solution:
Using the results calculated in Ex1: then repeating for a value of = 100 yields the following:

IC is seen to change by 100% due to the 100% change in (and no change in IB).
Using the results calculated in Ex3: then repeating for a value of = 50, we have the following:

DC Bias Circuit Independent of (Approximate Analysis)

In the previous dc bias circuits the values of IB and voltage of the collector depend on , but
is temperature sensitive for this reasons needs to provide a dc bias circuit that is
independent of the transistor beta

Fig (4-11) Beta-independent dc bias circuit

64

a) base-emitter Loop.
If the resistance seen looking into the base ( Fig4-12) is much larger than that of resistor RB2,
then the base voltage is set by the voltage divider of RB1 and RB2, then the current through
RBl goes almost completely into RB2 and the two resistors in series.

Fig (4-12) bias circuit for approximate VB

Calculating VB to the voltage-divider network of resistors RB1 and RB2, we get
[4-9]
Where VB is the voltage measured from base to ground. We then calculate the VE
[4-10]
The current in the emitter may then be calculated from
[4-11]
[4-12]

[4-13]
b) Collector-emitter Loop

VB is set by RB1 & RB2 and the supply voltage VCC , VE is the same VB, RE
RC determines the VC and, VCE voltage.

[4-14]
determines IE & IC,

Example 6: Calculate the dc bias voltage VCE and current IC for the circuit of Fig (4-13)

Fig (4-13) Beta-stabilized circuit for Ex 6:

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Solution:

Exact Analysis
A more exact analysis can be obtained by using the Thevenin equivalent of the voltage divider
as described by the following analysis:
[4-15]
[4-16]

The dc circuit to be analyzed can be redrawn as in fig (4-14) then calculate IB.

Fig (4-14) Dc circuit to analyze using Thevenin Eq

[4-17]
The value of VCE can be obtained using Eq[4-6]
Example 7: Calculate the dc bias voltage VCE and current IC for the circuit of Fig (4-13).
Solution:

Example 8: Using an exact bias analysis of the circuit of Fig (4-13), compare the IC & VCE for
the given of 140 and for a new of 70
Solution:
Using the results calculated in Ex 7: and repeating for a value of = 70, we have

66

The circuit maintains the IC and VCE even with a change in of 100%, the bias values only
changed by less than 3% in this circuit.
The approximate analysis would be satisfactory as long as

DC Bias with Voltage Feedback

The use of emitter resistor to provide improved bias stability, voltage feedback also provides
improved dc bias stability.

Fig (4-15) Dc bias cct with voltage feedback

Base Emitter loop
Writing the KVL equation around the base-emitter loop of the voltage feedback circuit gives

Fig (4-16) Partial circuit showing base-emitter loop

[4-18]
Collector-Emitter Loop
The partial circuit diagram of the collector-emitter section show in fig (4-17) the KVL equation is

67

[4-19]

Fig (4-17) Partial circuit showing collector-emitter loop

Example 9: Calculate the dc IE & VCE for the circuit of fig (4-18) using voltage feedback
Solution:

Fig (4-18) V-F circuit for Ex 9:

Example 10: Calculate the dc IC current & VC for the bias circuit of Fig (4-19).
Solution:

68

Fig (4-19) Dc bias with RE & V-F

Example 11: Analysis of various DC bias circuits
Calculate the collector current Ic and voltage VCE for the circuit of Fig (4-20)

Fig (4-20) Bias circuit for Example 11:

Solution:

Example 12: Calculate the bias voltage VE and current IC for the circuit of Fig (4-21)

Fig (4-21) Bias circuit for Example 12:

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Solution: Writing the base-emitter loop equation

Example 13: Calculate the collector voltage VC for the circuit of fig (4-22)

Fig (4-22) Bias circuit for Example 13:

Solution:

Example 14: Determine the collector voltage VC and current IC for the circuit of fig (4-23).

Fig (4-23) Bias circuit for Example 14:

Solution:

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Example 15: Calculate the emitter current IE and collector voltage VC for circuit in fig (4-24)

Fig (4-24) Circuit for example 15:

Solution:

Graphical DC bias analysis

A graphical technique is another method for finding the operating point of a transistor circuit.
The typical CE collector characteristic shown in Fig4-25, the circuit constraints must also be
taken into account in obtaining the actual operating point (quiescent point or Q-point)

Fig (4-25) Transistor collector characteristic

As typical of most circuits previously covered

We can rewrite that equation to solve for the collector current as follows:

71

[4-20]
Eq[4-20] shows the circuit equation as that of a straight line with slope

1. For
2. For

IC = 0,
VCE = 0,

And y-intercept
VCE = VCC
IC = VCC / (RC + RE)

Fig (4-26) Dc load line

The straight line connecting these points called the dc load line as in Fig (4-26)

Fig (4-27) Effect of varying (RC+RE) or VCC on dc load line: a- effect of resistor on dc load line,
b- effect of supply voltage on dc load line.
plotting transistor characteristic and dc load line on one graph for determination Q-point.

Fig (4-28) obtaining Q point

72

Example 16: Determine the quiescent operating point (Q) for the circuit of fig (4-29) using the
transistor collector characteristic of fig (4-25).

Fig (4-29) Bias circuit for Example 16:

Solution:
A dc load should be plotted on the collector characteristic of fig (4-25) this dc load line is
plotted by drawing a straight line from the point

Fig(4-30) shows the circuit dc load line and the transistor collector characteristic with the Qpoint marked at the intersection of the dc load line and base current of IB = 30.4 A. The
transistor is seen to be biased at

Fig (4-30) Graphical analysis for Ex 16:

Design of DC bias circuits
It is important to be able to design a circuit to operate at a desired or specified bias point. Often
the manufacturer's specification sheets provide information stating a suitable operating point
for a particular transistor and other circuit factors dictate some conditions of current swing,
voltage swing, and value of common supply voltage, which can be used in determining the
Q-point in a design.

73

Design of Bias Circuit with Emitter Feedback Resistor

The supply voltage and operating point will be selected from the manufacturer's information on
the transistor used in the amplifier.

Fig (4-31) Emitter-stabilization bias circuit

There are two unknown quantities: 1-the values of RC 2- the value of RE
VE is typically around one-fifth (1/5) to one-tenth (1/10) of the supply voltage VCC . Selecting the
emitter voltage in this way will permit calculating the RE and RC we get

Example 17: Calculate the resistor values RE , RC, and RB for a transistor amplifier circuit
having emitter-resistor stabilization (Fig4-31). The current gain of a transistor is 90 at a IC of
5mA Use a supply voltage VCC of 20V
Solution:The operating point selected from the information of tran ICQ=5 mA & VCEQ=10 V.

74

Design of Current Gain Stabilized (Beta Independent) Circuit

Circuit in Fig (4-32) provides stabilization both for ICO & current gain changes, the emitter
voltage selected to be one-tenth (1/10) of the supply voltage (VCC).

Fig (4-32) current gain stabilization design

Example 18: Design a dc bias circuit for an amplifier circuit as in Fig (4-32). The transistor has
a current gain of 150, at a collector current of 1 mA, and the supply voltage for the present
circuit is 16 V. Provide design for VCQ = VCC/2.
Solution;

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Bias Stabilization
In any amplifier circuit the collector current IC will vary with change in temperature
because of the three following main factors:
1. Reverse IC current leakage current ICO which doubles for every 10 increase in temperature
2. Base-emitter voltage VBE which decreases by 2.5 mV per C
3. Transistor current gain which increases with temperature.

Table-1
Notice that the significant increase of leakage current ICO not only causes the curves to rise
but also that an increase in beta occurs as shown in fig by the larger spacing between the
curves at the higher temperature.
Since the fixed-bias circuit provides an IB whose value depends on the VCC and RB, neither of
which is affected by temperature or the change in ICO or , the same IB will exist at high
temperatures as indicated on the fig

Fig (4-33) Shift in dc bias point (Q-point) due to change in temperature (a) 25 C (b) 100C
Stability Factor, S
A stability factor S, is the ratio of a change in collector current IC to the change in the
parameter value that caused it due to change in temperature Thus a stability factor is a
measure of how sensitive collector bias current is to change in a parameter value

76

Fig4-34a shows a basic transistor circuit and the effect of ICO

Fig4-34b the result of analyzing the stability based on change in ICO only ( & VBE constant)
Stability factor varies from the ideal case of S = 1 up to a maximum value of S = + 1 which
occurs for the fixed-bias circuit ( RB / RE > + 1 )
S is smallest for larger values of RE (RE improves S, makes S smaller)

Fig (4-34) Effect of ICO

[4-21]

Example 19: In a circuit using a transistor typified by the parameters in Table-1 calculate the
change in IC from 25C to 100C for
(a) Fixed bias (RB/RE )
(b) RB/RE = 11,
(c) RB/RE = 0.01.
Solution:

77

Analysis of the stability factor due to change in VBE will result in

Since smaller values of S indicate better stability, the larger the value of RE the better the
circuit stability due to changes in VBE with temperature.
Example 20: Determine the change in IC for a transistor having parameters listed in Table-1
over a temperature range from 25 to 100C for a circuit having RE = 1 k (and +1 >> RB/RE ).
Solution:

Analysis of the effect of changing with temperature on the circuit bias stability results in

[4-22]

Example 21: Calculate the change in collector current for the transistor having parameters as
given in Table-1 from room temperature to 100C. Assume that RB/RE = 20 for the circuit used
and that IC at room temperature is 2 mA.
Solution:

The collector current changing from 2 mA at room temperature to 2.315 mA at 100C

represents a change of about 16%.
The three parameters affecting S the change due to variation is probably greatest
The design of a good bias stabilized circuit most on stabilizing the effect of changes
in transistor beta.

78

So the total change in collector current over a certain temperature range is:
[4-23]
,
&
are the total change in the respective parameter values over the
temperature range. The expression is an approximation because all three parameters are
changing simultaneously with temperature
BJT switching circuits
Transistors are widely used in digital logic circuits and switching applications called an inverter.
Alternate between a Low 0V and a high voltage + 5V
When the input is high +5V, VBE is forward biased and current flows through RB , the values
of RB and RC are chosen so that the amount of base current flowing is enough to saturate the
transistor (to drive it into the saturation region of its output characteristics).

Fig4-36 an npn transistor inverter, or switch

VCE corresponding to this point is VCE(sat) is very nearly 0V, the current at the saturation point is
called IC(sat) is very nearly to VCC / RC
When the transistor is saturated, it is said to be ON "a High input to the inverter + 5V results in
a Low output 0V"
When the input to the transistor is Low 0V, the base-emitter junction has No forward bias
applied to it, so NO IB and hence NO IC flows therefore NO voltage drop across RC so that VCE
must be the same as VCC = + 5V, By substituting IC = 0 in the equation for VCE
VCE = VCC -ICRC = VCC - (0)(RC) = VCC
In this situation, the transistor is in the cutoff region of its output characteristics and is said to
be OFF. In designing and analyzing transistor inverters. It is usually assumed that
IC(sat) = VCC/RC and that VE(sat) = 0 V

Fig4-37 When the input to the inverter is high +5V the transistor is saturated and its output is
low ~0V, When the input to the inverter is low, the transistor is cut off its output is high.

79

We can easily derive the voltage-current relations in a transistor inverter, since the transistor is
cut off when the input is Low, the equations we will study are that apply when the input is high

VHI is the high level of the input voltage. Usually the same as VCC

Example 22: Verify that the circuit in fig8-38 behaves like an inverter when the input switches
between 0V and +5V. Assume that the transistor is Silicon and that =100.

Fig4-38 Example 22:

Solution:
It is necessary to verify that the transistor is saturated when Vin = +5V.

Example 23:

80

Example 24: Determine RB & RC for the transistor inverter of ICsat = 10mA

Solution:At saturation:

81

SUMMARY (BJT)
1-A bipolar junction transistor (BJT) consists of three regions: emitter, base, and collector.
2- The three regions of a BJT are separated by two pn junctions.
3- The two types of bipolar transistor are the npn and the pnp.
4- The term bipolar refers to two types of current: electron current and hole current.
5- One p-n junction of a transistor is forward-biased while the other is reverse-biased.
6- The dc emitter current is always the largest current of a transistor whereas the base
current is always the smallest. The emitter current is always the sum of the other two.
7- The collector current is made up of two components: the majority component and the
minority current (also called the leakage current).
8- The arrow in the transistor symbol defines the direction of conventional current flow for the
emitter current and thereby defines the direction for the other currents of the device
9- A three-terminal device needs two sets of characteristics to completely define its
characteristics.
10- In the active region of a transistor, the base-emitter junction is forward-biased while the
collector-base junction is reverse-biased.
11- In the cutoff region the base-emitter and collector-base junctions of a transistor are both
reverse-biased.
12- In the saturation region the base-emitter and collector-base junctions are forward biased.
13- On an average basis, as a first approximation, the base-to-emitter voltage of an operating
transistor can be assumed to be 0.7 V
14- The quantity alpha () relates the collector and emitter currents and is always close to one.
15- The impedance between terminals of a forward-biased junction is always relatively small
while the impedance between terminals of a reverse-biased junction is usually quite large.
16- The arrow in the symbol of an npn transistor points out of the device (not pointing in),
while the arrow points in to the center of the symbol for a pnp transistor, pointing in
17- For the linear amplification purposes, cutoff for the common-emitter configuration will be
defined by IC=ICEO
18- The quantity beta () provides an important relationship between the base and the
collector currents; the dc beta is defined by a simple ratio of dc currents at an operating point
19- To ensure that a transistor is operating within its maximum power level rating, simply find
the product of the collector-to-emitter voltage and collector current, and compare it to the rated
value.
20- No matter what type of configuration a transistor is used in, the basic relation ships
between the currents are always the same, and the base-to-emitter voltage is the threshold
value if the transistor is in the on state.
21- The operating point defines where the transistor will operate on its character curves under
dc conditions. For linear amplification, dc operating point should avoid the regions of saturation
and cutoff.
22- For most configurations the dc analysis begins with a determination of the base current.
23- For the dc analysis of a transistor network, all capacitors are replaced by an open circuit
equivalent.
24- The fixed-bias configuration is the simplest of transistor biasing arrangement but it is also
quite unstable due its sensitivity to beta at the operating point
25- Determining the saturation (maximum) collector current for any configuration can usually
be done quite easily if an imaginary short circuit is superimpose between the collector and
emitter terminals of the transistor. The resulting current through the short is then the saturation
current.
26- The equation for the load line of a transistor network can be found by applying KVL to the
output or collector network. The Q-point is determined by finding the intersection between the
base current and the load drawn on the device characteristics.
27- The emitter-stabilized biasing arrangement is less sensitive to changes in beta providing
more stability for the network. However, that any resistance in the emitter leg is "seen" at the

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base of the transistor as a much larger resistor (RE 10R2), a fact that will reduce the base
current of the configuration.
28- The voltage-divider bias configuration is probably the most common of all configurations.
Its popularity is due primarily to its Low sensitivity to change beta from one transistor to
another of the same lot. The exact analysis can be applied to any configuration, but the
approximate can be applied only if the reflected emitter resistance as seen at the base is
much larger (RE 10R2) than the lower resistor of the voltage-divider bias arrangement
connected to the base of the transistor.
29- When analyzing the dc bias with a voltage feedback configuration, be sure to remember
that both the emitter resistor and the collector resistor are reflected back to the base circuit by
beta. The least sensitivity to beta is obtained when the reflected resistance is much larger than
the feedback resistor between the base and collector.
30- For the common-base configuration the emitter current is normally determined first due to
the presence of the base-to-emitter junction in the same loop. Then the fact that the emitter
and collector current are essentially of the same magnitude is employed.
31- A clear understanding of the procedure employed to analyze a dc transistor network will
usually permit a design of the same configuration with a minimum of difficulty and confusion.
Simply start with those relationships that minimize the number of unknowns, and then proceed
to make some decisions about the unknown elements of the network.
32- In a switching configuration, a transistor quickly moves between saturation and cutoff, or
vice versa. Essentially, the impedance between collector and emitter can be approximated as
a short circuit for saturation and an open circuit for cutoff.
33- When checking the operation of a dc transistor network, first check that the base-to-emitter
voltage is very close to 0.7 V and that the collector-to-emitter voltage is between 25% and 75%
of the applied voltage VCC
34-The analysis of pnp configurations is exactly the same as that applied to npn transistors
with the exception that current directions will reverse and voltages will have the opposite
polarities.
35- Beta is very sensitive to temperature, and VBE decreases about 7.5 mV (0.0075 V) for each
10 increase in temperature on a Celsius scale. The reverse saturation current typically
doubles for every 10 increase in Celsius temperature.
36- Keep in mind that networks that are the most stable and least sensitive to temperature
changes have the smallest stability factors.

CB npn

CB pnp

83

Reveres saturation current

CE npn

CE pnp

Circuit conditions related to ICEO

CC pnp

CC npn

84

Determining the proper biasing arrangement for a CE npn transistor

Equation

85

86

87