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ORGANIZATION
CHAPTER 3
Sub-topics
The topic will cover:
Microprocessor architecture
CPU processing methods
Pipelining
Superscalar
RISC vs CISC
Multiprocessing
Instruction Cycle
Instruction Sets and Types
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MICROPROCESSOR
ARCHITECTURE
Control Unit,
Arithmetic Logic Unit,
Registers, and
Clock.
Microprocessor (CPU)
Microprocessor (CPU)
The microprocessor (central processing unit) is similar to the human
brain.
The heart of a computer is the CPU.
It interprets and carries out the basic instructions that operate a
computer.
Most processor chips manufacturers now offer multi-core processors
single chip with more than one separate processor cores.
These cores are viewed by the OS as separate processors. Currently
there are dual-core processors and quad-core processors.
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Microprocessor (CPU)
The processors contains three main components which work
together to perform processing operations.
CU
ALU
Registers
Decode :
Translate the program instruction into the commands that computer can
process
Execute:
Carry out the commands one after another
Store:
Store the result into main memory
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Logic Registers
Performs such logic operations as AND, OR, XOR, etc.
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Shifter
A special function register. It will move the contents of a register one or more
positions left or right. Can also perform a unique operation called rotate when
used with status register.
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Registers
A single, permanent storage location within the CPU used for
particular defined purpose.
Used to hold binary value temporarily for
Storage,
Manipulation, and/or
Simple calculations.
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Registers
A register may hold:
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Registers
Four primary operations by registers:
Can be loaded with values from other locations (from other registers
or memory location).
Data can be added or subtracted.
Data can be shifted or rotated right or left by one or more bits.
Value of data in register can be tested for certain conditions (zeros,
negative, etc)
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Registers
Instruction Register (IR)
Holds the current instruction being executed.
Program Counter
Both a counter and a register.
The address in the program counter register is always the address of
the next instruction to be executed.
When the current instruction is finished, the program counter
generates an address and places it on the address bus.
It then increments, that is, adds 1 to the address it just generated and
puts the number in the counter register.
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Registers
Program Counter (cont)
Again, when the current instruction is finished, it places the new
address on the address bus and again adds 1 to the register.
Therefore, the program counter continually generates sequential
address.
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Registers
Memory Data Register (MDR)
Also known as Memory Buffer Register (MBR).
Holds data value that is being stored to or retrieved from the memory
location currently addressed by the memory address register.
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Registers
Status Register (Flags)
Allow computers to keep track of special condition such as:
Arithmetic carry and overflow
Power failure, and
Internal computer error.
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System Clock
The system clock is a device that emits periodic sequence of
pulses to control the timing of all computer operations.
These pulses define machine cycles.
During each machine cycle, some activity occurs, such as the
execution of a microinstruction.
The interval between corresponding edges of two consecutive
pulses is called the clock cycle time.
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System Clock
The pace of the clock or the clock speed is measured by the
number of ticks per second.
Pulse frequencies are currently in the gigahertz range which
corresponds to billions of ticks per second.
Therefore the faster the clock speed, the more instructions the
processor can execute per second.
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System clock:
Chapter 8
Chapter 15
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Pipelining
Superscalar
CISC and RISC
Multiprocessing
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Instruction
Decode
Unit
Registers
ALU
Bus Interface
Memory
Addressing
Unit
Instruction
Execution
Unit
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Pipelining
A Pipelining is an implementation technique where
multiple instructions are overlapped in execution.
Used in advanced microprocessors where the
microprocessor begins executing a second instruction
before the first has been completed.
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Pipelining
Computer processors can handle millions of instructions each
second. Once one instruction is processed, the next one in line is
processed, and so on.
A pipeline allows multiple instructions to be processed at the same
time. While one stage of an instruction is being processed, other
instructions may be undergoing processing at a different stage.
Without a pipeline, each instruction would have to wait for the
previous one to finish before it could even be accessed.
Refer to Figure 8.5 Page 252
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Pipelining
The computer pipeline is divided in stages.
Each stage completes a part of an instruction in parallel.
That is, several instructions are in the pipeline
simultaneously, each at a different processing stage.
The stages are connected one to the next to form a pipe
instructions enter at one end, progress through the stages, and
exit at the other end.
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Pipelining
Instruction 1
Instruction 2
Instruction 3
Instruction 4
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Pipelining
It is not useful to pipe different types of instructions
through a single pipeline different execution units are
created based on general types of instructions:
Load/store unit
Integer arithmetic unit
Floating point arithmetic unit
Branch unit
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Pipelining
Pipeline hazards
Situations that prevent the next instruction in the instruction
stream from executing during its designated clock cycle.
The instruction is said to be stalled.
Effect stall following instructions too. No new instructions
are fetched during the stall.
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Pipelining
Types of hazards:
Structural hazard
Control Hazard
Data hazard
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Pipelining
Structural hazard attempt to use the same resource
two different ways at a time.
Eg: use the register for multiplication and division operation
at the same time.
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Pipelining
Data hazard attempt to use data before it is ready
Eg: the following instruction depends on the result of prior
instruction in the pipeline.
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Pipelining
How to overcome hazards?
Instruction reordering separate dependent
instructions so they are not executed one right after
the other.
Prediction, superscalar processing.
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Superscalar
It means processing multiple instructions at a time because of
its multiple pipeline.
It is a standard feature in modern computer systems.
Superscalar processing can increase the throughput by double
or more.
Separate fetch and execute cycles as much as possible
Buffers for fetch and decode phases
Parallel execution units
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Scalar VS Superscalar
Scalar:
A CPU that performs computations on one number or set of
data at a time.
Most computers have scalar CPUs.
A scalar processor is known as a "single instruction stream
single data stream
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Scalar VS Superscalar
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Data dependency
later instruction completes ahead of the earlier one.
Implication
wrong order.
Solution
provide reservation station.
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Conflict of Resources
Conflict
bet instructions that use the same registers
Solution
Bank of registers
Concept
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CPU Architecture
CISC Complex Instruction Set Computer
RISC Reduced Instruction Set Computer
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CISC Architecture
Examples
Intel x86, IBM Z-Series Mainframes, older CPU
architectures
Characteristics
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Multiprocessing
The use of more than 1 CPU to process instructions.
Reasons for using multiprocessing:
Increase the processing power of a system.
Enables parallel processing programs can be divided into
independent pieces and the different parts executed
simultaneously on multiple processors.
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Multiprocessing
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Multiprocessing
Since the execution speed of a CPU is directly related to the
clock speed, equivalent processing power can be achieved at
much lower clock speeds, reducing power consumption, heat
and stress within the various computer components.
Adding more CPUs is relatively inexpensive.
If a CPU encounters a problem, other CPUs can continue
instruction execution, increasing overall throughput.
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Multiprocessing
Two types:
a) tightly coupled system
b) loosely coupled system
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Multiprocessing
Typical multiprocessing system configuration
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Disadvantages
Master CPU becomes a bottleneck
Reliability issues if master CPU fails entire system fails
Applications
Game, Finance, Economics, Biology, Physics
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Advantages
High reliability
Fault tolerant support is straightforward
Balanced workload
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Pipelining
Superscalar
RISC vs CISC
Multiprocessing
: Chapter
: Chapter
: Chapter
: Chapter
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INSTRUCTION CYCLE
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Instruction Cycle
The microprocessors main task is to execute
instructions.
The instruction cycle is therefore at the heart of
understanding the function and operation of the
microprocessor.
The time begins when the address for retrieving an
instruction from memory is placed on the address bus
for a fetch, and ending when the execution phase is
completed.
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Instruction Cycle
The instruction cycle is composed of two main cycles,
because both instructions and data are in memory.
Fetch cycle
Find and Decode instruction, load from memory into register and
signal ALU
Execute cycle.
Performs operation that instruction requires
Move/transform data
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Instruction Cycle
Generally, a microprocessor carries out instructions in
a three-step (or phase) process.
It simply repeats the three-step operation with almost
no variation, as long as power is applied to it.
These three steps are called
Fetch
Decode
Execute
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2. MDR -> IR
4. MDR -> A
5. PC + 1 -> PC
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2. MDR -> IR
4. A + MDR -> A
5. PC + 1 -> PC
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2. MDR -> IR
4.
A -> MDR*
5.
PC + 1 -> PC
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LMC Fetch-Execute
SUBTRACT
IN
OUT
HALT
PC MAR
PC MAR
PC MAR
PC MAR
MDR IR
MDR IR
MDR IR
MDR IR
IR[addr] MAR
IOR A
A IOR
A MDR A
PC + 1 PC
PC + 1 PC
BRANCH
BRANCH on Condition
PC MAR
PC MAR
MDR IR
MDR IR
IR[addr] PC
If condition false: PC + 1 PC
PC + 1 PC
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Arithmetic
Operators + - / * ^
Integers and floating point
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Program control
Jumps, branch, CALL, RETURN
Stack instructions
Push, pop
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