Documente Academic
Documente Profesional
Documente Cultură
Page 0
Regulation 2013
V- Semester
Name
: ..
Reg .No
: ..
Branch
: ..
Page 1
LTPC
0032
OBJECTIVES:
TOTAL: 45 PERIODS
OUTCOMES: Students will be able to
Carry out simulation of DSP systems
Demonstrate their abilities towards DSP processor based implementation of
DSP systems
Analyze Finite word length effect on DSP systems
Demonstrate the applications of FFT to DSP
Implement adaptive filters for various applications of DSP
LAB EQUIPMENT FOR A BATCH OF 30 STUDENTS (2 STUDENTS PER
SYSTEM) PCs with Fixed / Floating point DSP Processors (Kit / Add-on Cards) 15 Units
LIST OF SOFTWARE REQUIRED: MATLAB with Simulink and Signal Processing
Tool Box or Equivalent Software in desktop systems -15 Nos Signal Generators (1MHz)
15 Nos CRO (20MHz) -15 Nos
Page 2
INDEX
S.No
Date
Page
No
Staff
Sign
Page 3
INDEX
S.No
Date
Page
No
Staff
Sign
Page 4
Why go digital?
Digital signal processing techniques are now so powerful that sometimes it is extremely difficult, if
not impossible, for analogue signal processing to achieve similar performance.
Examples:
FIR filter with linear phase.
Adaptive filters.
Analogue signal processing is achieved by using analogue components such as:
Resistors.
Capacitors.
Inductors.
The inherent tolerances associated with these components, temperature, voltage changes and
mechanical vibrations can dramatically affect the effectiveness of the analogue circuitry.
With DSP it is easy to:
Change applications.
Correct applications.
Update applications.
Additionally DSP reduces:
Noise susceptibility.
Chip count.
Development time.
Cost.
Power consumption.
Why NOT go digital?
Page 5
99
yn ak xn k
k 0
Real-time processing
Waiting Time 0
Page 6
Equation
M
y ( n)
x(n k )
x ( n k )
k 0
M
y ( n)
k 0
b y (n k )
k
k 1
Convolution
x ( k ) h( n k )
y ( n)
k 0
N 1
X (k )
n 0
F u
N 1
Microcode
Page 7
High throughput
Lower silicon area
Lower power consumption
Improved reliability
Reduction in system noise
Low overall system cost
Disadvantages
High investment cost
Less flexibility
Long time from design to market
Useful Links
Selection Guide:
\Links\DSP Selection Guide.pdf
Page 8
(2) Repeatability: The same signal processing operation can be repeated again and
again giving same results, while in analog systems there may be parameter variation due to
change in temperature or supply voltage. The choice between analog or digital signal processing
depends on application. One has to compare design time,size and cost of the implementation.
The applications of the digital signal processing will include the following main applications.
Page 9
Chip Series
Analog Devices
ADSP-21XX series
Texas instruments,USA
TMS-320XXX series
Motorola Corporation,USA
M-56XXX series
Scientist
Year
Term Z-transform
Jury
1964
Cooley-Tukey
1965
Cooley-Tukey
1965
1966
algorithms
4
1967
1968
1973
Page 10
From 1975
processor
10
For Reference:http://www.vlab.co.in/
Objectives of the Virtual Labs:
To provide remote-access to Labs in various disciplines of Science and Engineering. These
Virtual Labs would cater to students at the undergraduate level, post graduate level as well as to
research scholars.
To enthuse students to conduct experiments by arousing their curiosity. This would help them in
learning basic and advanced concepts through remote experimentation.
To provide a complete Learning Management System around the Virtual Labs where the students
can avail the various tools for learning, including additional web-resources, video-lectures,
animated demonstrations and self evaluation.
To share costly equipment and resources, which are otherwise available to limited number of
users due to constraints on time and geographical distances
Page 11
MathWorks
Initial release
Stable release
Preview release
None []
Development status
Active
Written in
Operating system
Platform
IA-32, x86-64
Type
Technical computing
License
Website
Page 12
DATE:
AIM:
To study about MATLAB R2013a
MATLAB:
MATLAB is a high performance language for technical computing. It integrates computation,
visualization and programming in an easy to use environment where problems and solutions are expressed
in familiar mathematical notations.
The name MATLAB stands for MATRIX LABORATORY. Today, MATLAB engines incorporate the
LAPACK and BLAS Libraries, embedding the state of the art in software for matrix computation.
USES:
Typical uses include,
Algorithm development
Data acquisition
Page 13
GRAPHICS:
MATLAB has extensive facilities for displaying vectors and matrices as groups as well as annotating and
printing these graphs.
Expressions
EXPRESSIONS :
The building blocks of expressions are
Variables
Numbers
Operators
Functions
VARIABLES :
MATLAB does not require any type of declarations or dimensions when it encounters a new variable
name. It automatically creates the variable and allocates appropriate memory.
Example : num_stud = 25
NUMBERS :
MATLAB uses conventional decimal notation, with an optional decimal point. It uses E to specify a
power of ten. Imaginary nos used either i or j as a suffix.
Example : 3, -99, 1i, 3e5i
OPERATORS :
+
add
subtract
multiply
division
Page 14
left division
Power
FUNCTIONS :
MATLAB provides a large no.of standard functions including abs, sqrt, exp and stn.
SYNTAX:
abs :
y = abs(x)
b = sqrt(x)
y = exp(x)
c = sin(A)
TOOL BOXES :
There are a no.of tool boxes available in MATLAB some of them are:
Communication toolbox
Wavelet toolbox
RF toolbox
COMMUNICATION TOOLBOX:
The communication toolbox extends the MATLAB technical computing environment with functions, plot
as a graphical user interface.
The toolbox helps you to create algorithms for commercial and defense wireless s/ms.
FUNCTIONS :
Signal Sources: Sources of random signals Performance evaluation : analysing and visualizing
performances of a communication s/m.
Page 15
cepstral analysis
MATLAB COMMANDS:
Page 16
Morphological operations
Transforms
Deblurring
Image registration
SIMULINK :
Simulink is a software package for modeling, simulating and analysing dynamic systems. It supports linear
and non-linear s/ms, modeled in continuous time, sampled time, or a hybrid of the two systems may also
have different parts that are sampled at different rates (multirated).
RESULT:
Thus the MATLAB and MATLAB tools were studied.
Page 17
PROGRAM
% program to generate unit step sequence
n = -10:10;
s = [zeros(1,10) 1 ones(1,10)];
stem (n,s);
title ('unit step sequence');
xlabel ('time index n');
ylabel ('amplitude');
OUTPUT:
Page 18
EX.NO: 2
DATE:
AIM
To write a MATLAB program to generate the following standard input signals and plot the response.
1. Unit step,
2. Unit impulse,
3. Unit ramp,
4. Exponential signal
5. Sinusoidal signal,
6. Cos signal
7. Triangular wave,
8. Saw tooth wave
APPARATUS REQUIRED
SOFTWARE : MATLAB 7.10 (OR) High version
UNIT STEP SEQUENCE
The unit step sequence is a signal that is zero everywhere except at n >= 0 where its value is unity.
In otherwise integral of the impulse function is also a singularity function and is called the unit step
function.
MATHEMATICAL EQUATION
u(n) = 1 for n >= 0
= 0 for n < 0
ALGORITHM
1.
2.
3.
Discrete output is obtained for n>= 0 and zeros for all other values.
4.
5.
Page 19
PROGRAM
%program to generate unit ramp sequence
n =0:10;
s =n;
stem (n,s);
title ('unit ramp sequence');
xlabel ('time index');
ylabel ('amplitude');
OUTPUT
Page 20
for n = 0
for n 0
ALGORITHM
1.
2.
3.
Discrete output is obtained for n = 0 and zeros for all other values.
4.
5.
for n >= 0
for n< 0
ALGORITHM
1.
2.
3.
Discrete output is obtained for n>=0 and zeros for all other values
4.
5.
Page 21
Page 22
SINUSOIDAL SEQUENCE
The sine function output is calculate by the following equation
General equation Fn = sin (2 * pi * f * t)
The modified sine wave equation is
X(t) = sin (2 *pi * Fin * Tsamp * t)
Where,
t = No of Samples vary from 0 to Nsamp-1(It is generate single wave. Increase wave means to multiply that
no into Nsamp. Ex generate two cycles means multiply 2 into Nsamp.
MATHEMATICAL EQUATION
X(n) = A sin (2 * pi * f * t)
Where f frequency in Hz, t time in sec, A - Amplitude
Page 23
Page 24
Where,
t = No of Samples vary from 0 to Nsamp-1(It is generate single wave. Increase wave means to multiply that
no into Nsamp. Ex generate two cycles means multiply 2 into Nsamp.
Page 25
Page 26
Page 27
Page 28
Page 29
Page 30
RESULT
Thus the MATLAB programs for unit step, unit impulse, unit ramp, sinusoidal signal sawtooth ,
Triangular wave ,exponential signals were generated and their responses were plotted in discrete and
continuous time domain successfully.
Page 31
Viva voce:
1. What is signal.
2. Classify the signals.
3. What is an Energy and power signal?
4. What is the formula for energy and power?
5. what is continuous time and discrete time signal.
6. What is analog and digital signal?
7. What is even and odd signal?
8. What is multi channel and multidimensional signal?
9. What is energy of unit sample function?
10. what is unit step function.
11. How unit step and impulse function are related?
12. What is the condition for periodicity of DT signal?
13. What is deterministic and random signal.
14. what is causal and non causal signal.
15. what is unit impulse and unit ramp signal.
16. what is cos and sine signal.
17. what is sinc and saw tooth function.
18. what is Exponential signal.
19. What is Elementary signal?
20. What is BIBO stable system?
Page 32
DATE:
New
Script.
Save
Page 33
Page 34
Page 35
Correlation :
Enter the 1st sequence : [1 2 3 4]
Enter the 2nd sequence : [4 3 2 1]
The resultant Signal is : y1 = 1.0000
4.0000
10.0000
20.0000
25.0000
24.0000
16.0000
Page 36
(h) ------>
1
0.5
2
1
1.5
(a)n ------>
4
3
2
1
0
2
(d)n ------>
2
1
0
4
2
2
3
(b)n ------>
Discrete Correlation
4
(h1) ------>
(x1) ------>
2
(e)n ------>
2
(c)n ------>
5
(f)n ------>
10
30
(y1) ------>
(x) ------>
1.5
Discrete Convolution
4
(y) ------>
20
10
RESULT
Thus the MATLAB programs for discrete convolution and correlation were plotted in discrete time
domain successfully.
Page 37
Page 38
DATE:
AIM
To write a MATLAB program to obtain the linear & circular convolution between two finite duration
sequences x(n) and h(n).
THEORY
Convolution is a powerful way of characterizing the input-output relationship of time invariant linear
systems. Convolution finds its application in processing signals especially analyzing the output of the
system.
The response or output y(n) of a LTI system for any arbitrary input is given by convolution of input and the
impulse response h(n) of the system.
y(n)
[ x( k )h(n k ]
(1)
If the input has L samples and the impulse response h(n) has M samples then the output sequence y(n)
will be a finite duration sequence consisting of L+ M-1 samples. The convolution results in a non-periodic
sequence. Hence this convolution is also called a periodic convolution.
The convolution relation of equation (1) can also be expressed as
y(n) = x(n) *h(n) = h(n) * x(n)
where the symbol * indicates convolution operation.
ALGORITHM
1. Initialize the two input sequences.
2. Find the length of first and second input sequences use the following syntax
length (x ).
Where, x input sequence
3. Find out the linear convolution output length using first sequence length and Second sequence
length (N = x+h-1).
Page 39
Page 40
Page 41
PROGRAM
CIRCULAR CONVOLUTION
clear all;
Xn = [1,2,1,1];
Hn = [1,1,1];
x=length(Xn);
h = length(Hn);
N = max(x,h);
Yn = cconv(Xn,Hn,N);
subplot(2,2,1);
stem(Xn);
Page 42
Page 43
subplot(2,2,2);
stem(Hn);
title('Second Input Sequence');
xlabel('Length of Second Input Sequence');
ylabel('Input Value');
subplot(2,2,3);
stem(Yn);
title('Circular Convolution Output Sequence');
xlabel('Length of Output Sequence');
ylabel('Output Value');
INPUT & OUTPUT
Enter the input sequence x(n) = [1,2,1,1]
Enter the input sequence h(n) = [1,1,1]
Convoluted output y(n) = 3, 4, 4, 4
Page 44
RESULT
Thus the MATLAB programs for linear and circular convolution signals were generated and their
responses were plotted in discrete time domain successfully.
Page 45
%x =[0 1 2 3 4 5 6 7]
t = 0:pi/x:pi;
num =[0.05 0.033 0.008];
den =[0.06 4 1];
trans = tf(num,den);
[freq,w] =freqz(num,den,x); grid on;
subplot(2,1,1);plot(abs(freq),'k');
Page 46
Aim : To develop program for computing discrete Fourier Transform (DFT) and inverse discrete Fourier
Transform (IDFT).
Apparatus : PC having MATLAB software.
Procedure
1. OPEN MATLAB
2. File
New
Script.
Save
Page 47
DFT is x = 28.0000
-4.0000
-4.0000 + 9.6569i
-4.0000 + 4.0000i
-4.0000 + 1.6569i
-4.0000 - 1.6569i
-4.0000 - 4.0000i
-4.0000 - 9.6569i
IDFT :
Enter length of DFT 4 = 0.0180
0.0166
0.0130
0.0093
Page 48
Graph:
DFT :
Imaginary axis------>
4
2
0
-2
-4
-6
-8
-10
4
5
Real axis------>
IDFT :
Magnitude Response
Magnitude
0.02
0.015
0.01
0.005
1.5
2.5
Frequency index
3.5
RESULT
Thus the MATLAB programs for DFT/IDFT done successfully.
Page 49
Page 50
The principal objective of this experiment is to understand the principle of sampling of continuous time
analog signal.
AIM
To perform sampling operation and view the aliasing effect.
THEORY
A key step in any digital processing of real world analog signals is converting the analog signals into
digital form. We sample continuous data and create a discrete signal. Unfortunately, sampling can
introduce aliasing, a nonlinear process which shifts frequencies. Aliasing is an inevitable result of both
sampling and sample rate conversion.
The Nyquist sampling theorem defines the minimum sampling frequency to completely represent a
continuous signal with a discrete one. If the sampling frequency is at least twice the highest frequency in
the continuous baseband signal, the samples can be used to exactly reconstruct the continuous signal. A
sine wave can be described by at least two samples per cycle (consider drawing two dots on a picture of a
single cycle, then try and draw a single cycle of a different frequency that passes through the same two
dots). Sampling at slightly less than two samples per cycle, however, is indistinguishable from sampling a
sine wave close to but below the original frequency. This is aliasing - the transformation of high frequency
information into false low frequencies that were not present in the original signal. The Nyquist frequency,
also called the folding frequency, is equal to half the sampling frequency f, and is the demarcation between
frequencies that are correctly sampled and those that will cause aliases. Aliases will be 'folded' from the
Nyquist frequency back into the useful frequency range.
ALGORITHM
1. Initialize input Frequency, sampling frequency and number of sample values (Nsamp).
Sampling frequency must be twice the input frequency.
2. Then two different sinusoidal signals are sampled at the same sampling frequency.
Page 51
Page 52
RESULT
Thus the sampling operation and effect aliasing is performed.
Page 53
Page 54
DATE:
The experiment enables students to understand:
AIM
To write a MATLAB program for the design of FIR Filter for the given cutoff frequency using windowing
technique. Also plot the magnitude and phase responses for the same.
THEORY
The filters designed by using finite number of samples of impulse response are called FIR filters. These
finite number of samples are obtained from the infinite duration desired impulse response h d(n). Here
hd(n)is the inverse Fourier transform of Hd(), where Hd() is the ideal (desired) frequency response. The
various methods of designing FIR filters are (i). Fourier Series method, (ii). Window method, (iii).
Frequency Sampling method, (iv) Optimal filter design method. Here we discuss about window method
only.
FILTER TYPES
1. Low Pass Filter
2. High Pass Filter
3. Band Pass Filter
4. Band Reject Filter
1.
2 Fc
Hd ( n )
sin(Wc n) / n
2.
n 0
n/2 n n/2
1 2 Fc
Hd (n)
sin (Wc n) / n
n 0
n/2 n n/2
Page 55
Page 56
2( Fc2 Fc1)
Hd (n)
sin (Wc2 n) sin (Wc1 n) / n
4.
n 0
n/2 n n/2
2( Fc1 Fc2)
Hd (n)
sin (Wc1 n) sin (Wc2 n) / n
n 0
n/2 n n/2
Hd (e )
jw
(n)e jwn ]
..(1)
Where
hd (n) 1 / 2 H (e jw )e jwn d
(2)
Page 57
Page 58
After multiplying window sequence w(n) with Hed(n), we get a finite duration sequence h(n) that satisfies
the desired magnitude response,
h(n) = hd(n)(n)
=0
The frequency response H(ej) of the filter can be obtained by convolution of H d(ej)) and W(ej)
given
by
Hd (e jw )
(n)e jwn ]
(1)
H (e ) 1 / 2 Hd (e j )e j ( w ) d
j
(2)
= H(e ) * W(e )
Because both Hd(ej) and W(ej) are periodic function, the operation often called as periodic convolution.
WINDOW TYPES
Rectangular window
Rectangular window function can be found by the following equation
Page 59
Page 60
Hamming window
Hamming window function is calculated by the given equation
0.54 0.46
0
hm (n)
cos(2n) / ( N 1) for ( N 1) / 2 n ( N 1) / 2
Otherwise
Hanning window
Hanning window function is calculated by the given equation
0.5 0.5
0
hn (n)
cos(2n) / ( N 1) for ( N 1) / 2 n ( N 1) / 2
Otherwise
Blackman window
Blackman window function is calculated by following equation
b1(n)
for ( N 1) / 2 n ( N 1) / 2
0
Otherwise
Page 61
Page 62
Declare the five filter types (low pass, high pass, Band pass, Band Reject), with the above
specification.
1. Low pass = fdesign.lowpass(N,fc,N,Fcut,Fsamp)
2. High pass = fdesign.highpass(N,fc,N,Fcut,Fsamp)
3. Band pass = fdesign.bandpass('N,fc1,fc2', N,Fpass, Fstop, Fsamp)
4. Band stop = fdesign.bandstop('N,fc1,fc2', N,Fpass, Fstop, Fsamp)
Bartlett window
- @bartlett
- @blackman
- @hamming
- @hann
v. Kaiser window
- @kaiser
- @triang
4. Then use the fvtool for display the filter response outputs (fvtool filter visualization tool).
RESULT
Thus the FIR filters were designed using various windowing techniques in MATLAB and the output has
been verified.
Page 63
Page 64
DATE:
The experiment enables students to understand:
AIM
To write a MATLAB program to design Butterworth & Chebychev low pass, high pass, band pass and
band stop digital IIR filter from the given specifications.
THEORY
The filters designed by considering all the infinite samples of impulse response are called IIR filters. IIR
filters are of recursive type, whereby the present output sample depends on the present input, past input
samples and output samples.
ALGORITHM
1. Initialize the pass band ripple, stop band attenuation and sampling frequency.
2.
Declare the five filter types (low pass, high pass, Band pass, Band Reject), with the above
specification. It is only for butterworth filter.
1. [b, a] = butter(n, wn,'low');
2. [b, a] = butter(n, wn,high);
3. [b, a] = butter(n, wn,'passband');
4. [b, a] = butter(n, wn,'stop');
Page 65
Page 66
Page 67
Page 68
Page 69
Page 70
RESULT
Thus the MATLAB programs for the design of Butterworth & Chebychev LPF, HPF, BPF and BSF were
designed and also their magnitude responses has been plotted successfully.
Page 71
bilinear transformation.
Page 72
INTERPOLATION
DATE:
AIM:
The objective of this program is To Perform upsampling on the Given Input Sequence.
EQUIPMENT REQUIRED:
P IV Computer
Windows Xp SP2
MATLAB
Procedure
1. OPEN MATLAB
2. File
New
Script.
Save
THEORY:
Up sampling on the Given Input Sequence and Interpolating the sequence.
Page 73
EXPECTED GRAPH:
Page 74
Result:
This MATLAB program has been written to perform interpolation on the Given Input sequence.
Page 75
title('Decimated Sequence');
EXPECTED GRAPH:
Page 76
DECIMATION
DATE:
AIM:
The objective of this program is To Perform Decimation on the Given Input Sequence.
EQUIPMENT REQUIRED:
P IV Computer
Windows Xp SP2
MATLAB
Procedure
1. OPEN MATLAB
2. File
New
Script.
Save
THEORY:
Decimation on the Given Input Sequence by using filter with filter-coefficients a and b.
Result:
This MATLAB program has been written to perform Decimation on the Given Input
Sequence.
Page 77
K=M-L; %% Discarding several starting samples for avoiding 0's and negative
X=zeros(L+1,K); % each vector column is a sample
for i=1:K X(:,i)=x(i+L:-1:i).';
end
%adaptive LMS Equalizer
e=zeros(1,T-10); % initial error
c=zeros(L+1,1); % initial condition
mu=0.001;
% step size
for i=1:T-10
e(i)=TxS(i+10+L-EqD)-c'*X(:,i+10); % instant error
c=c+mu*conj(e(i))*X(:,i+10);
% update filter or equalizer coefficient
end
sb=c'*X; % recieved symbol estimation
%SER(decision part)
sb1=sb/norm(c); % normalize the output sb1=sign(real(sb1))+sqrt(1)*sign(imag(sb1)); %symbol detection start=7;
sb2=sb1-TxS(start+1:start+length(sb1));
%
error
detection
SER=length(find(sb2~=0))/length(sb2); % SER calculation disp(SER);
% plot of transmitted symbols
subplot(2,2,1), plot(TxS,'*');
grid,title('Input symbols'); xlabel('real part'),ylabel('imaginary part') axis([-2 2 2 2])
% plot of received symbols
subplot(2,2,2), plot(x,'o');
grid, title('Received samples'); xlabel('real part'), ylabel('imaginary part')
Page 78
EQUALIZATION
DATE:
Aim :
To develop program for equalization.
Apparatus :
PC having MATLAB software.
Procedure:
Equalizing a signal using Communications System Toolbox software involves these steps:
1. Create an equalizer object that describes the equalizer class and the adaptive algorithm that you
want to use. An equalizer object is a type of MATLAB variable that contains information about
the equalizer, such as the name of the equalizer class, the name of the adaptive algorithm, and the
values of the weights.
2. Adjust properties of the equalizer object, if necessary, to tailor it to your needs. For example,
you can change the number of weights or the values of the weights.
3. Apply the equalizer object to the signal you want to equalize, using the equalize method of the
equalizer object.
Page 79
Expected graph:
Page 80
RESULT:
Thus the equalization program is designed and developed.
Page 81
Digital imaging
Medical ultrasound
Portable ultrasound equipment
CT scanners
Magnetic resonance imaging
Page 82
DATE:
AIM:
To study architecture of TMS 320C5416
THEORY:
TM320C5416 consists of CPU containing various functional units such as ALU, MAC unit, EXP
encoders, brrel registers, shifters, memory mapped registers, system control interface, program address
generation logic and data address generation logic and eight 16 bit buses with interconnection.
5AX BUSEs :
The 5AX architecture in built around eight major 16 bit buses. The program bus arrives the
instruction code and immediate operands from program memory. Three data buses interconnect to various
elements such as CPU, DAGEN, on chip peripherals and the memory. The CB & DB carry operands that
are read from data memory. The EB carrier data to be written in memory.
INTERNAL MEMORY ORGANIZATION :
1. ON CHIP ROM :
This is part of program memory space and in some cases, part of data
memory space. The amount of ON Chip on data devices varies.
2. ON - CHIP DUAL ACCESS RAM :
The DARAM is composed of several blocks can be accessed twice per machine cycle CPU can read from
and write to a single block of DARAM in same cycle.
3. ON CHIP SINGLE ACCESS RAM :
The SARAM is composed of several blocks. Each block is accessible once per machine cycle. For either a
read or write, the SARAM is always mapped in data space and primarily written to store data values.
4. ON CHIP MEMORY SECURITY :
The 5AX maskable memory security option protects contents of on chip memories, When this option is
chosen, no externally originating instruction can access on chip
5. MEMORY MAPPED REGISTE :
The data memory space contains memory mapped registers for CPU and onchip peripherals. These
registers are locked on data page sampling access to them.
6. CENTRAL PROCESSING UNIT:
The 5AX CPU is common to all its devices. The block diagram is given in 5AX CPU content.
7. 40 BIT ALU :
Two 40 bit accumulator register barred shift registers supporting A 16 to 31 shift range
8. MULTIPLY OR ACCUMULATOR BLOCK :
9. 16 Bit temporary registers, TRM compare, select and store unit exponent encoders.
Page 83
Page 84
9.STATUS REGISTERS:
STO & STI has status of various mode for 15x devices. STO has flag produced key arithimetic
operation and bit manipulation in status of mode and instruction executed by processor.
10.TRN REG:
It set the transistor device divide on half to new matrix to perform the algorithm.
RESULT:
Thus the architecture of TMS320C5416 was studied.
Page 85
ii) SUBRACTION
. mmregs
. global start;
start: ld # 1000h, a:
sub # 0100h,a
.end
iii) MULTIPLICATION
. mmregs
. global start;
start: ld # 1000h,a
mpy # 0100h,a
.end
iv) DIVISION
. mmregs
. global start;
start: ld # 1000h,a
Div # 0100h,a
.end
Page 86
DATE :
AIM:
To write an assembly language program to perform aritmmetic operation using TMS320C5416.
SOFTWARE USED:
TMS software
PROCEDURE:
Step 1: Start the program.
Step2: Get the data and check for the proper working.
Step3: Condition of the processor using diagonistic tools.
Step4: Create a new project & open a new source file and enter the source file and enter the
source code in it.
Step5: Add a source file command file and library file to the project created.
Step6: Load the program and run it
Step7: The required output is recorded
Page 87
Addition
Tabulation
1.
A=1000h
2.
A=2000h
3.
A=1FFFh
4.
A= 0002h
5.
A= 0020h
SUBTRACTION:
Instruction
After execution
1.
A= 1100h
2.
A= 1000h
Page 88
RESULT:
Thus the program is executed and output is verified.
Page 89
OUTPUT:
Page 90
DATE:
AIM:
To write a program in C language to generate sine wave series using TMS 320C5416.
SOFTWARE USED:
TMS 320C5416
PROCEDURE:
i) Check the processor working conditions of the processor with the diagnostic loads.
ii) Open a new project in that open a new source file and the program code.
iii) To that source add a command file library file and a command file.
iv) Now compile the source code.
v) Now load the program and run it.
vi) The required output is obtained.
RESULT:
Thus the program for generatig a sine wave is executed and the output is obtained.
Page 91
Page 92
DATE:
AIM:
To perform linear convolution using processor TMS 320 VC5416.
APPARATUS REQUIRED:
C5416 software processor.
PROCEURE:
i)Conect TMS v 5416 bit to pc
ii) Open code and compare studio and ensure working conditions of the processor with the
diagnostic loads.
iii) Open a new project in that open a new source file and the program code.
iv)To that source add a command file library file and a command file.
v) Now compile the source code.
vi) Now load the program and run it.
vii)The required output is obtained.
RESULT:
Thus the program for generating a sine wave is executed and the output is obtained
Page 93
Instructions
Before execution
After execution
Sxm=0
(0x105c)=0x0000
Bk=3
(0x105c)=0x4413
(AC1)=0xBEEF
(A)=105EH
(A)=0x0000
(A)=0x44C3
(A)=0xBEEF
(0x105E)=0xBEEF
(A)=0x0000
(A)=0x44C3
Page 94
DATE :
AIM:
To perform linear convolution using processor TMS 320 VC5416.
APPARATUS REQUIRED:
C5416 software processor.
PROCEDURE:
i)Conect TMS v 5416 bit to pc
ii) Open code and compare studio and ensure working conditions of the processor with the
diagnostic loads.
iii) Open a new project in that open a new source file and the program code.
iv)To that source add a command file library file and a command file.
v) Now compile the source code.
vi) Now load the program and run it.
vii)The required output is obtained.
RESULT:
Page 95
Page 96
DATE:
AIM:
To implement 64 point FFT using DIT algorithm in TMS 320 C 5416 DSP processor.
APPARATUS REQUIRED:
PC, TMS 320C5416 ,USB
PROCEDURE:
1.
2.
3.
4.
Open code composer studio and make sure bit is in proper working.
Start project and library file , command file and source file.
The compile program , build and loading is done.
Run program and output is received by graph.
Page 97
0;
}
}
FFT. C:
# define PTS 64
type def start { float, real , imag};
void fft ( composer xy , intu)
{
complex turn p, turnp2;
int upper = = log , lower leg;
int num stages;
int index- stages;
I = 1;
Do
{
num-stages + = 1;
i= I * 2
}
while ( i/ n);
leg diff = N/2;
for ( i= 0; I < num stages ; I ++);
{
index = 0;
for ( j =0; j ,
Page 98
Page 99
Page 100
INPUT
OUTPUT:
Page 101
Page 102
RESULT:
Thus program for 64 point FFT has been executed and output is obtained suddenly
Page 103
Page 104
Page 105
Page 106
DATE:
AIM
To write a program for calculating Fast Fourier Transform of given input signal using MATLAB software
package.
THEORY
FFT
The implementation of DFT through digital computers requires the memory to store x(n) and values of
coefficients WknN . The amount of accessing and storing of data in computation is directly proportional to
the number of arithmetic operations involved. Therefore, for direct computation of N- point DFT the
amount computation and computation time is proportional to N 2. From equation (1) observe that the direct
calculation of the DFT requires N2 complex multiplications and N (N-1) complex additions. Direct
computation of DFT is basically inefficient, primarily because it does not exploit the symmetry and
periodicity properties of the twiddle or phase factor WN.
As the value of N increases, the direct computation of DFT becomes a time taking and complex process,
which also leads to very high memory capacity requirements.
The computationally efficient algorithms, known collectively as Fast Fourier Transform (FFT) algorithms
exploit the symmetry and periodicity properties of the twiddle or phase factor WN. In particular, these two
properties are:
Wk+N/2 N = -WkN
Wk+N
= WkN
The FFT is a method for computing the DFT with reduced number of calculations. The computational
efficiency is achieved if we adopt a divide and conquer approach. This approach is based on the
decomposition of an N- point DFT into smaller DFTs.
Page 107
Page 108
In an N-point sequence, if N can be expressed as N= r m , then the sequence can be decimated into r- point
sequences. For each r- point sequence, r- point DFT can be computed. From the results of r-point DFT, r2point DFTs are computed. From the results of r2-point DFTs, the r3-point DFTs are computed and so on,
until we get rm-point DFT. In computing N-point DFT by this method a number of stages of computation
will be m times. The number is called Radix of the FFT algorithm.
Page 109
INPUT
Enter the input sequence : 1, 1, 0, 0
OUTPUT
Real Output = 2 1 0 1
Imaginary Output = 0 -1 0 1
Page 110
ALGORITHM
1. Initialize the variable Xn. Then find the length of the input sequence (Xn) and store the value
into variable N. It is the FFT order (4, 8, 16, .. point fft).
2. Find the FFT for the given input sequence and use the function fft (Xn, N). N refers the order
of FFT.
3. The FFT output is in complex form, so the output contains Real and Imaginary values. Use
stem (real(x)) to plot Real values and stem(imag(x)) is used to plot the imaginary values.
4. Then use the subplot and stem function to display the input and output in a single graph
window. Else use figure( ) function to display the input & output in separate window.
5. The title function is used to give the name to the waveform.
6. The xlabel & ylabel is used to find the unit for x & y axis.
RESULT
Thus the calculation of Fast Fourier Transform of input signal was verified and Real & imaginary values
are plotted.
Page 111
Page 112
ARCHITECTURE
The TMS320C6713 is a 32 bit floating point processor, operating at 225MHz which delivers up to
1350 million floating-point operations per second (MFLOPS) and 1800 million instructions per
second (MIPS). The C6713 uses a two-level cache-based architecture and has a powerful and
diverse set of peripherals. The level1 program cache (L1P) is a 4K-byte direct-mapped cache and
the level1 data cache (L1P) is a 4K-Byte 2-way set-associative cache. The level 2 memory/cache
(L2) consists of a 256K-Byte memory space that is shared between program and data space. The
C6713 has a rich peripheral set that includes two multichannel Audio Serial Ports (McBSPs), two
Inter-Integrated Circuit (I 2C) buses, one dedicated General-Purpose Input/Output(GPIO) module,
two general-purpose timers, a host-port interface (HPI), and a external memory interface (EMIF)
capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.
1.2.
Page 113
16
32
GPIO
Timer 0
Timer 1
I2C0
I2C1
McBSP0
McBSP1
McASP0
McASP1
EMIF
Enhanced
DMA
Controller
(16 channel)
L2
Memory
192K
Bytes
(Up to
4-way)
L2 Cache /
Memory
4 Banks
64K Bytes
Total
M1
D2
M2
D1
S2
In-circuit
Emulation
Interrupts
Control
Test
Control
logic
Control
registers
Power - Down
Logic
L2
Register file A
Register file A
S1
Data path B
C67 x TMCPU
Data path A
L1
Instruction Decode
Instruction Dispatch
Instruction Fetch
L1P Cache
Direct Mapped
4K Bytes Total
Page 114
g ni xel pi tl u Mni P
INTERNAL MEMORY
It is a part of 32-bit, byte-addressable address space. Internal (on-chip) memory is
organized in separate data and program spaces. When off-chip memory is used, these spaces
are unified on most devices to a single memory space via the external memory interface (EMIF).
The C6713 has two 32-bit internal ports to access internal data memory. Besides there is a single
internal port to access internal program memory, with an instruction-fetch width of 256 bits.
1.4
MEMORY AND PERIPHERAL OPTIONS
A variety of memory and peripheral options are available for the C6713 DSP:
*
Memories
- Large on-chip RAM, up to 7M bits
- Program cache
- 2-level caches
- 32-bit external memory interface supports SDRAM, SBSRAM, SRAM, and other
asynchronous memories for a broad range of external memory requirements and
maximum system performance.
DMA Controller transfers data between address ranges in the memory map without
intervention by the CPU. There are four programmable channels and a fifth auxiliary
channel inside the DMA block.
EDMA Controller performs the same functions as the DMA controller and is equipped with
16 programmable channels, as well as a RAM space to hold multiple configurations
for future transfers.
HPI is a parallel port through which a host processor can directly access the CPUs memory
space. The host device has easy access because it is the master of the interface. The host
and the CPU can exchange information via internal or external memory. In addition, the
host has direct access to memory-mapped peripherals.
Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF. The
expansion provides two distinct areas of functionality (host port and I/O port) which can coexist in a system. The host port of the expansion bus can operate in either asynchronous
slave mode, similar to the HPI, or in synchronous master/slave mode. This allows
the device to interface to a variety of host bus protocols. Synchronous FIFOs and
asynchronous peripheral I/O devices may interface to the expansion bus.
* The two McASP interface modules each support one transmit and one receive clock zone.
There are eight serial data pins in each McASP, which can be individually allocated to any
of the two zones. The serial port supports time-division multiplexing on each pin from 2 to
Page 115
McBSP (multichannel buffered serial port) is based on the standard serial port interface
found on the TMS320C2000 and C5000 platform devices. In addition, the port can buffer
serial samples in memory automatically with the aid of the DMA/EDNA controller. It
also has multichannel capability compatible with the T1, E1, SCSA, and MVIP networking
standards.
* The two I2C ports on the TMS320C6713 allow the DSP to easily control peripheral devices,
boot from a serial EEPROM, and communicate with a host processor.
*
Timers in the C6713 devices are two 32-bit general-purpose timers used for these functions:
*
Time events
Count events
Generate pulses
signaling mode that can be loaded by an internal or internal source. The timers inherit an
input pin and output pin, which can be configured for general purpose input and output
respectively. The input and output pins (T INP, TOUT) can function in timer clock input and
clock output.
*
Power-down logic allows reduced clocking to reduce power consumption. Most of the
operating power of CMOS logic dissipates during circuit switching from one logic state to
another. By preventing some or all of the chips logic from switching, you can realize
significant power savings without losing any data or operational context.
Page 116
There are two general-purpose register files (A and B) in the C6713 data paths. Each of
these files contains sixteen 32-bit registers (A0-A15 for file A and B0- B15 for file B). The
general-purpose registers can be used for data, data address pointers or condition registers.
The C6713 general-purpose register files support data ranging in size from packed 16-bit data
through 40-bit fixed-point and 64-bit floating point data.
Values larger than 32 bits, such as 40-bit long and 64-bit float quantities are stored in
register pairs. In these the 32 LSBs of data are placed in an even-numbered register and the
remaining 8 or 32 MSBs in the next upper register (which is always an odd- numbered
register). The C64x register file extends this by additionally supporting packed 8-bit types
and 64-bit fixed-point data types. The packed data types store either four 8-bit values or two
16-bit values in a single 32-bit register, or four 16-bit values in a 64-bit register pair. There are
16 valid register pairs for 40-bit and 64-bit data in the C6713 cores, and 32 valid register pairs
for 40-bit and 64-bit data in the C64x core, as shown in Table. In assembly language syntax, a
colon between the register names denotes the register pairs, and the odd-numbered register is
specified first.
Register Files
A
Applicable Devices
B
A1:A0
A3:A2
A5:A4
A7:A6
A9:A8
A11:A10
A13:A12
A15:A14
B1:B0
B3:B2
B5:B4
B7:B6
B9:B8
B11:B10
B13:B12
B15:B14
A17:A16
A19:A18
A21:A20
A23:A22
A25:A24
A27:A26
A29:A28
A31:A30
B17:B16
B19:B18
B21:B20
B23:B22
B25:B24
B27:B26
B29:B28
B31:B30
C62x/C64x/C67x
C64x ONLY
Page 117
ODD REGISTER
31
EVEN REGISTER 0
IGNORED
READ FROM
REGISTERS
39
32
31
0
40 - BIT DATA
WRITE TO
REGISTERS
ODD REGISTER
39
32
ZERO-FILLED
31 EVEN REGISTER 0
40 - BIT DATA
FUNCTIONAL UNITS
The eight functional units in the C6713 data paths can be divided into two groups of four; each
functional unit in one data path is almost identical to the corresponding unit in the other data
path. The functional units are described in Table 1-2.
Page 118
Functiona
l Unit
.L unit
(.L1,L2)
Fixed-Point Operations
.D unit (.D1,
.D2)
FloatingPoint
Operation
Arithmetic operations
s
DP6Sp, INT6DP,
INT6SP conversion
operations
Compare Reciprocal
and reciprocal squareroot operations
Absolute value
operations S P 6D P
conversion
operations
Page 119
One unit (.S2) can read from and write to the control register file, as shown in this section.
Table 1.3 lists the control registers contained in the control register file and describes each. If
more information is available on a control register, the table lists where to look for that
information. Each control register is accessed by the MVC instruction.
Additionally, some of the control register bits are specially accessed in other ways. For example,
arrival of a maskable interrupt on an external interrupt pin, INTm, triggers the setting of flag
bit IFRm. Subsequently, when that interrupt is processed, this triggers the clearing of IFRm
and the clearing of the global interrupt enable bit, GIE. Finally, when
that
interrupt
processing is complete, the B IRP instruction in the interrupt service routine restores the
pre-interrupt value of the GIE. Similarly, saturating instructions like SADD set the SAT
(saturation) bit in the CSR (Control Status Register).
Abbreviation
AMR
Register Name
Addressing mode
register
Description
Specifies whether to use linear or circular
addressing for each of eight registers also contains
sizes for circular addressing.
CSR
IFR
ISR
ICR
IER
Interrupt enable
register
ISTP
Interrupt service table
pointer
IRP
Page 120
maskable interrupt
Contains the address to be used to return from a
nonmaskable interrupt
Contains the address of the fetch packet that is in
the E1 pipel line stage.
Program counter, EI
phase
Fetch
Decode
Execute
All instructions in the C67x instruction set flow through the fetch, decode, and execute
stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions, and
the decode stage has two phases for all instructions. The execute stage of the pipeline
requires a varying number of phases, depending on the type of instruction. The stages of the
C67x pipeline are shown in Figure 1-3.
:
:
:
:
The C6713 uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed
through fetch processing together, through the PG, PS, PW, and PR phases. Figure 1-4(a) shows
the fetch phases in sequential order from left to right. Figure 1- 4(b) shows a functional diagram
of the flow of instructions through the fetch phases. During the PG phase, the program address is
generated in the CPU. In the PS phase, the program address is sent to memory. In the PW
phase, a memory read occurs. Finally, in the PR phase, the fetch packet is received at the CPU.
Figure 1-4(c) shows fetch packets flowing through the phases of the fetch stage of the pipeline.
Page 121
CPU
PG PS PW PR
(a)
Functional
Units
(b)
PR
Registers
PS
Memory
PG
(c)
PW
256
Fetch
LDW LDW
SHR
LDW LDW
LDW LDW
MVKLH
LDW LDW
MVK
SHR
SMPYH SMPHY
MV SMPYH
ADD
SHL
SADD
SMPY
LDW
MV
NOP
PG
MVK PS
MVK PW
LDW MVK PR
Decode
:
:
Instruction dispatch
Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute packets. Execute
packets consist of one instruction or from two to eight parallel instructions. During the DP
phase, the instructions in an execute packet are assigned to the appropriate functional
units. In the DC phase, the source registers, destination registers, and associated paths are
decoded for the execution of the instructions in the functional units. Figure 1-5(a) shows the
decode phases in sequential order from left to right. Figure 1- 5(b) shows a fetch packet that
contains two execute packets as they are p rocessed through the decode stage of the pipeline.
The last six instructions of the fetch packet(FP) are parallel and form an execute packet (EP).
This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each
Page 122
The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because
there is no execution associated with it. The first two slots of the fetch packet represent an
execute packet of two parallel instructions that were dispatched on the previous cycle. This
execute packet contains two MPY instructions that are now in decode (DC) one cycle before
execution. There are no instructions decoded for the .L, .S, and .D functional units for the
situation illustrated.
(a)
DP DC
(b)
Decode
32
32
32
32
32
ADD ADD STW
MPYH
L1
S1
M1
32
32
32
STW ADDK NOP1 DP
MPYH
DC
D1
Functional D2
units
M2
S2
L2
require different numbers of these phases to complete their execution. These phases of the
pipeline play an important role in your understanding the device state at CPU cycle
boundaries.
Pipeline Execution of Instruction Types.
Figure 1-6(a) shows the execute phases of the pipeline in sequential order from left to
right. Figure 1-6(b) shows the portion of the functional block diagram in which execution
occurs.
Page 123
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
(b)
Execute
E1
SADO
L1
B
S1
SMPY
M1
STH
D1
STH
D2
SMPYH
M2
SUB
S2
SADD
L2
32
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register file A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32
Data 1
Data 2
Register file B
32
32
16
0
16
16
16
6
Data address 1
Data address 2
Figure 1-6 Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C6713
Example Program
Write an Arithmetic Logic Program for the below mentioned equation, by using 6713 instruction set and
functional units. (Addressing modes)
40
a
n1
xn
A5++
Memory
Data
80001000
a0
A6++ 80001100
X0
80001004
a1
80001104
x1
8000109C an
8000119C
xn
PROGRAM
Page 124
Page 125
40, A2
MVK .S1
0, A4
MVK .S1
0x80001000, *A5
; an Input values
MVK .S1
0x80001100, *A6
; xn Input values
*A5++, A0
; A0 = a(n)
LDH .D1
*A6++, A1
; A1 = x(n)
MPY .M1
A0, A1, A3
; A3 = a(n) * x(n)
ADD .L1
A3, A4, A4
; Y = Y + A3
SUB
.L1
A2, 1, A2
.S1
loop
; if A2 = 0, branch
.D1
A4, *A7
; *A7 = Y
[A2] B
STH
Page 126
RESULT:
Thus the Study of various addressing modes of DSP(TMS320C6713 Processor) using simple programming
examples has been studied.
Page 127
Page 128
DATE:
AIM:
To write a C program for the design & Implementation of FIR filters for the given cutoff frequency using
frequency sampling method.
APPARATUS REQUIRED
1.
TMS320C6713 Kit
2.
Vi Debugger (6713)
3.
CCS Software
THEORY
In this experiment the FIR filters are implemented by using the cutoff frequency, sampling frequency and
Order of the filter N. In FIR filter is finite no of order and its has four types of filters.
Filter Type & Equations
In FIR filter perform Low Pass, High Pass, Band Pass, Band Reject operation to the input
frequency. The filter type equations are given below
i) Low Pass Filter
The low pass filter equation is
2 Fc
Hd ( n )
sin(Wc n) / n
n 0
n/2 n n/2
1 2 Fc
Hd (n)
sin (Wc n) / n
n 0
n/2 n n/2
Page 129
2( Fc2 Fc1)
Hd (n)
sin (Wc2 n) sin (Wc2 n) / n
n 0
n/2 n n/2
2( Fc1 Fc2)
Hd (n)
sin (Wc1 n) sin (Wc2 n) / n
n 0
n/2 n n/2
Page 130
Page 131
Page 132
Page 133
int *SocValue,*AdcValue;
int SocRead,*AdcStore;
int *DacOut;
short AdcOut;
int OutValue, Count,Inc;
float *Hd,*Hm;
float Val;
unsigned char *Led;
SocValue = (int *)0x9004000c;
AdcValue = (int *)0x90040008;
Page 134
Page 135
Page 136
int *SocValue,*AdcValue;
int SocRead,*AdcStore;
int *DacOut;
short AdcOut;
int OutValue,Count,Inc;
float *Hd,*Hm;
float Val;
unsigned char *Led;
SocValue = (int *)0x9004000c;
AdcValue = (int *)0x90040008;
AdcStore = (int *)0x80000000;
Hd = (float *)0x80010000;
Hm = (float *)0x80030000;
Page 137
Page 138
Page 139
Page 140
Page 141
*DacOut = OutValue;
*Led = 1;
}
}
Page 142
RESULT
Thus the design & Implementation of FIR Filter (LPF, HPF, BPF, BSF) for the given cut off frequency C
program was performed.
Page 143
DSP Mini-Project:
An Automatic Speaker Recognition System
http://www.ifp.uiuc.edu/~minhdo/teaching/speaker_recognition
Overview
Speaker recognition is the process of automatically recognizing who is speaking on the basis of
individual information included in speech waves. This technique makes it possible to use the speaker's
voice to verify their identity and control access to services such as voice dialing, banking by telephone,
telephone shopping, database access services, information services, voice mail, security control for
confidential information areas, and remote access to computers.
This document describes how to build a simple, yet complete and representative automatic speaker
recognition system. Such a speaker recognition system has potential in many security applications. For
example, users have to speak a PIN (Personal Identification Number) in order to gain access to the
laboratory door, or users have to speak their credit card number over the telephone line to verify their
identity. By checking the voice characteristics of the input utterance, using an automatic speaker
recognition system similar to the one that we will describe, the system is able to add an extra level of
security.
Page 144
Input
speech
Feature
extraction
Reference
model
(Speaker #1)
Maximum
selection
Identification
result
(Speaker ID)
Similarity
Reference
model
(Speaker #N)
Input
speech
Speaker ID
(#M)
Feature
extraction
Similarity
Reference
model
(Speaker #M)
Decision
Verification
result
(Accept/Reject)
Threshold
All speaker recognition systems have to serve two distinguished phases. The first one is referred to the
enrolment or training phase, while the second one is referred to as the operational or testing phase. In the
training phase, each registered speaker has to provide samples of their speech so that the system can build
or train a reference model for that speaker. In case of speaker verification systems, in addition, a speakerspecific threshold is also computed from the training samples. In the testing phase, the input speech is
matched with stored reference model(s) and a recognition decision is made.
Speaker recognition is a difficult task. Automatic speaker recognition works based on the premise that
a persons speech exhibits characteristics that are unique to the speaker. However this task has been
challenged by the highly variant of input speech signals. The principle source of variance is the speaker
himself/herself. Speech signals in training and testing sessions can be greatly different due to many facts
such as people voice change with time, health conditions (e.g. the speaker has a cold), speaking rates, and
so on. There are also other factors, beyond speaker variability, that present a challenge to speaker
recognition technology. Examples of these are acoustical noise and variations in recording environments
(e.g. speaker uses different telephone handsets).
Page 145
0.5
0.4
0.3
0.2
0.1
-0.1
-0.2
-0.3
-0.4
-0.5
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
Time (second)
A wide range of possibilities exist for parametrically representing the speech signal for the speaker
recognition task, such as Linear Prediction Coding (LPC), Mel-Frequency Cepstrum Coefficients (MFCC),
and others. MFCC is perhaps the best known and most popular, and will be described in this paper.
MFCCs are based on the known variation of the human ears critical bandwidths with frequency,
filters spaced linearly at low frequencies and logarithmically at high frequencies have been used to capture
the phonetically important characteristics of speech. This is expressed in the mel-frequency scale, which is
a linear frequency spacing below 1000 Hz and a logarithmic spacing above 1000 Hz. The process of
computing MFCCs is described in more detail next.
Page 146
continuous
speech
Frame
Blocking
mel
cepstrum
frame
Cepstrum
Windowing
mel
spectrum
FFT
spectrum
Mel-frequency
Wrapping
Frame Blocking
In this step the continuous speech signal is blocked into frames of N samples, with adjacent frames
being separated by M (M < N). The first frame consists of the first N samples. The second frame begins M
samples after the first frame, and overlaps it by N - M samples and so on. This process continues until all
the speech is accounted for within one or more frames. Typical values for N and M are N = 256 (which is
equivalent to ~ 30 msec windowing and facilitate the fast radix-2 FFT) and M = 100.
Windowing
The next step in the processing is to window each individual frame so as to minimize the signal
discontinuities at the beginning and end of each frame. The concept here is to minimize the spectral
distortion by using the window to taper the signal to zero at the beginning and end of each frame. If we
define the window as w(n), 0 n N 1, where N is the number of samples in each frame, then the result
of windowing is the signal
yl (n) xl (n)w(n), 0 n N 1
2n
w(n) 0.54 0.46 cos
, 0 n N 1
N 1
Page 147
X k xn e j 2kn / N ,
k 0,1,2,..., N 1
n 0
In general Xks are complex numbers and we only consider their absolute values (frequency
magnitudes). The resulting sequence {Xk} is interpreted as follow: positive frequencies 0 f Fs / 2
correspond to values 0 n N / 2 1 , while negative frequencies Fs / 2 f 0 correspond to
N / 2 1 n N 1. Here, Fs denotes the sampling frequency.
The result after this step is often referred to as spectrum or periodogram.
Mel-frequency Wrapping
As mentioned above, psychophysical studies have shown that human perception of the frequency
contents of sounds for speech signals does not follow a linear scale. Thus for each tone with an actual
frequency, f, measured in Hz, a subjective pitch is measured on a scale called the mel scale. The melfrequency scale is a linear frequency spacing below 1000 Hz and a logarithmic spacing above 1000 Hz.
Mel-spaced filterbank
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
1000
2000
3000
4000
Frequency (Hz)
5000
6000
7000
Page 148
Cepstrum
In this final step, we convert the log mel spectrum back to time. The result is called the mel frequency
cepstrum coefficients (MFCC). The cepstral representation of the speech spectrum provides a good
representation of the local spectral properties of the signal for the given frame analysis. Because the mel
spectrum coefficients (and so their logarithm) are real numbers, we can convert them to the time domain
using the Discrete Cosine Transform (DCT). Therefore if we denote those mel power spectrum
~
coefficients that are the result of the last step are S0 , k 0,2,..., K 1 , we can calculate the MFCC's, c~n , as
K
1
~
~c
(log
S
)
cos
n
k
n
k
k 1
2 K
n 0,1,..., K-1
Note that we exclude the first component, c~0 , from the DCT since it represents the mean value of the
input signal, which carried little speaker specific information.
Summary
By applying the procedure described above, for each speech frame of around 30msec with overlap, a
set of mel-frequency cepstrum coefficients is computed. These are result of a cosine transform of the
logarithm of the short-term power spectrum expressed on a mel-frequency scale. This set of coefficients is
called an acoustic vector. Therefore each input utterance is transformed into a sequence of acoustic
vectors. In the next section we will see how those acoustic vectors can be used to represent and recognize
the voice characteristic of the speaker.
Feature Matching
Overview
The problem of speaker recognition belongs to a much broader topic in scientific and engineering so
called pattern recognition. The goal of pattern recognition is to classify objects of interest into one of a
number of categories or classes. The objects of interest are generically called patterns and in our case are
sequences of acoustic vectors that are extracted from an input speech using the techniques described in the
previous section. The classes here refer to individual speakers. Since the classification procedure in our
case is applied on extracted features, it can be also referred to as feature matching.
Furthermore, if there exists some set of patterns that the individual classes of which are already known,
then one has a problem in supervised pattern recognition. These patterns comprise the training set and are
Page 149
Speaker 1
Speaker 1
centroid
sample
Speaker 2
VQ distortion
Speaker 2
centroid
sample
Page 150
Page 151
m<M
No
Stop
Split each
centroid
m = 2*m
Cluster
vectors
Find
centroids
Compute D
(distortion)
D = D
No
D ' D
Yes
Figure 6. Flow diagram of the LBG algorithm (Adapted from Rabiner and Juang, 1993)
Project
As stated before, in this project we will experiment with the building and testing of an automatic
speaker recognition system. In order to build such a system, one have to go through the steps that were
described in previous sections. The most convenient platform for this is the Matlab environment since
many of the above tasks were already implemented in Matlab. The project Web page given at the
beginning provides a test database and several helper functions to ease the development process. We
supplied you with two utility functions: melfb and disteu; and two main functions: train and test.
Download all of these files from the project Web page into your working folder. The first two files can be
treated as a black box, but the later two needs to be thoroughly understood. In fact, your tasks are to write
two missing functions: mfcc and vqlbg, which will be called from the given main functions. In order to
accomplish that, follow each step in this section carefully and check your understanding by answering all
the questions.
Speech Data
Down load the ZIP file of the speech database from the project Web page. After unzipping the file
correctly, you will find two folders, TRAIN and TEST, each contains 8 files, named: S1.WAV, S2.WAV,
, S8.WAV; each is labeled after the ID of the speaker. These files were recorded in Microsoft WAV
format. In Windows systems, you can listen to the recorded sounds by double clicking into the files.
Page 152
Speech Processing
In this phase you are required to write a Matlab function that reads a sound file and turns it into a
sequence of MFCC (acoustic vectors) using the speech processing steps described previously. Many of
those tasks are already provided by either standard or our supplied Matlab functions. The Matlab functions
that you would need are: wavread, hamming, fft, dct and melfb (supplied function). Type help
function_name at the Matlab prompt for more information about these functions.
Question 2: Read a sound file into Matlab. Check it by playing the sound file in Matlab using the function:
sound. What is the sampling rate? What is the highest frequency that the recorded sound can capture
with fidelity? With that sampling rate, how many msecs of actual speech are contained in a block of 256
samples?
Plot the signal to view it in the time domain. It should be obvious that the raw data in the time domain
has a very high amount of data and it is difficult for analyzing the voice characteristic. So the motivation
for this step (speech feature extraction) should be clear now!
Now cut the speech signal (a vector) into frames with overlap (refer to the frame section in the theory
part). The result is a matrix where each column is a frame of N samples from original speech signal.
Applying the steps Windowing and FFT to transform the signal into the frequency domain. This
process is used in many different applications and is referred in literature as Windowed Fourier Transform
(WFT) or Short-Time Fourier Transform (STFT). The result is often called as the spectrum or
periodogram.
Question 3: After successfully running the preceding process, what is the interpretation of the result?
Compute the power spectrum and plot it out using the imagesc command. Note that it is better to view
the power spectrum on the log scale. Locate the region in the plot that contains most of the energy.
Translate this location into the actual ranges in time (msec) and frequency (in Hz) of the input speech
signal.
Question 4: Compute and plot the power spectrum of a speech file using different frame size: for
example N = 128, 256 and 512. In each case, set the frame increment M to be about N/3. Can you
describe and explain the differences among those spectra?
The last step in speech processing is converting the power spectrum into mel-frequency cepstrum
coefficients. The supplied function melfb facilitates this task.
Page 153
Vector Quantization
The result of the last section is that we transform speech signals into vectors in an acoustic space. In
this section, we will apply the VQ-based pattern recognition technique to build speaker reference models
from those vectors in the training phase and then can identify any sequences of acoustic vectors uttered by
unknown speakers.
Question 7: To inspect the acoustic space (MFCC vectors) we can pick any two dimensions (say the 5 th
and the 6th) and plot the data points in a 2D plane. Use acoustic vectors of two different speakers and plot
data points in two different colors. Do the data regions from the two speakers overlap each other? Are
they in clusters?
Now write a Matlab function, vqlbg that trains a VQ codebook using the LGB algorithm described
before. Use the supplied utility function disteu to compute the pairwise Euclidean distances between the
codewords and training vectors in the iterative process.
Question 8: Plot the resulting VQ codewords after function vqlbg using the same two dimensions
over the plot of the previous question. Compare the result with Figure 5.
Page 154
innovations.
BEST OF LUCK
Page 155