Asm 02

Outline of todays lecture
Time, location and coverage for midterm
ITEC 1000A Midterm

Midterm time:
Tuesday (June 27): 18:00pm - 21:00pm
Summary of last weeks class

Class location: TEL 0001
Case study: two examples
Coverage: Chapter 1, 2, 3 , 4 and 6
Computer instructions
ITEC 1000
Introduction to Information Technologies
ITEC 1000
LMC Counterparts
Format of Midterm
4 LMC questions
similar in style to those in the book and the slides.
ALU
Input/output
interface
00
01
02
03
04
05
123
you should know how to write a short program.

456
3 short answer questions for definitions
Control unit
7 questions about number representation,

conversion and operations.
Program counter
p. 167
ITEC 1000
Program counter (PC)

Instruction register (IR)
Memory address register (MAR)
Memory data register (MDR)
Accumulator (ACC)
Status register
General purpose registers (R0, R1, )

Included on some CPUs
Used for high-speed temporary storage
ITEC 1000
Program Counter ( PC )
Registers
A register is a single permanent storage location
within the CPU used for a particular purpose.
Unlike memory, which is outside the CPU
Examples of registers:
123
05
Additionally 10's and 2's complement representation will be

included.
95
96
97
98
99
789
These questions will be similar in format to the questions in

the assignment#1.
ITEC 1000
123
500
199
500
399
A dedicated register in the CPU.

Contains the address in memory of the current
instruction being executed.
Incremented automatically after each instruction.
May be forced to change: eg jump instruction.
Usually initialize to zero when machine starts, or is
reset.
ITEC 1000
Instruction Register ( IR )
Memory registers
A dedicated register in the CPU which contains the

actual current instruction.
Op Code
What To Do
Contains Address in memory to find or

place data.
Address
Memory Data Register (MDR)

Contains Actual Data to be placed in
location given in MAR, or which has been
retrieved from location given in MAR.
Location of Data
1101 101101100100
Simple 16-bit example:

ITEC 1000
Memory Address Register (MAR)
ITEC 1000
Memory Unit
n bits
Accumulator
bit 0
A dedicated register (or set of registers) in the CPU

used for the actual manipulation of data.
0
1
2
3
4
Address decoder
bit 1
Default source (or destination) register.

Usually contains results of arithmetic or logical
operations.
2n-1
bit n - 1
0
m-1
Memory data register
MDR
ITEC 1000
Calculator in LMC
Memory cell
Memory address register
MAR
m bits
p. 160
ITEC 1000
Fetch-Execute Cycle
Generic CPU With Registers
Two steps, or cycles, in the execution of

every instruction
Program Counter ( PC )
Instruction Register ( IR )
Memory Address Register ( MAR )
Memory Data Register ( MDR )
Memory
Fetch fetch the code for the instruction from

memory and place it in the IR (instruction
register)
Execute execute the instruction
Accumulator ( A or Acc )
Fetch
Execute
time
ITEC 1000
ITEC 1000
The LOAD Instruction
Fetch
PC
MAR
MDR
IR
Fetch
MDR
MAR
Execute
IR
A + MDR
PC + 1
PC
MAR
time
A
PC
Text: Page 177, Revised.
Text: Page 177, Revised.

ITEC 1000
MAR
IR[address]
time
PC + 1
PC
MDR
IR[address]
Execute
The Add Instruction
ITEC 1000
Fetch-Execute Example: Load Accumulator

CPU Before PC increments
Assume:
Simple Eight bit system.

Thirty-two memory locations (0 to 31).
Load instruction is 010.
Value in location 15 is ten (ie: binary 00001010)
PC is at 5, about to increment.
The instruction, 01001111, is in location 6.
Location 31
PC:
00101
IR:
(previous)
MAR: (previous)
15: 00001010
MDR: (previous)
Then ...
A:
(previous)
06: 01001111
Location 0
ITEC 1000
ITEC 1000
Increment PC: PC = PC + 1
MAR loaded with PC: PC -> MAR

Location 31
Location 31
PC:
00110
PC:
00110
IR:
(previous)
IR:
(previous)
MAR: (previous)
15: 00001010
MDR: (previous)
A:
(previous)
MAR: 00110
MDR: (previous)
06: 01001111
A:
(previous)
Location 0
ITEC 1000
15: 00001010
06: 01001111
Location 0
ITEC 1000
Memory Location 00110 Accessed

and Contents Placed in MDR:
Memory Location 00110 Accessed

and Contents Placed in MDR:
Location 31
Location 31
PC:
00110
PC:
00110
IR:
(previous)
IR:
(previous)
MAR: 00110
15: 00001010
MAR: 00110
MDR: (previous)
A:
(previous)
MDR: 01001111
06: 01001111
A:
(previous)
Location 0
ITEC 1000
MDR copied to IR: MDR -> IR
IR [ address part ] -> MAR

Location 31
Location 31
PC:
00110
PC:
00110
IR:
01001111
IR:
01001111
15: 00001010
MAR: 01111
MDR: 01001111
A:
(previous)
06: 01001111
A:
(previous)
Location in MAR (01111) Accessed
Contents of 01111 loaded into MDR

Location 31
Location 31
PC:
00110
PC:
00110
IR:
01001111
IR:
01001111
15: 00001010
MAR: 01111
MDR: 01001111
A:
(previous)
15: 00001010
MDR: 00001010
06: 01001111
A:
(previous)
Location 0
ITEC 1000
06: 01001111
Location 0
ITEC 1000
MAR: 01111
15: 00001010
MDR: 01001111
Location 0
ITEC 1000
06: 01001111
Location 0
ITEC 1000
MAR: 00110
15: 00001010
06: 01001111
Location 0
ITEC 1000
Finished !
IR [op code] executed: MDR -> A

Location 31
Location 31
PC:
00110
PC:
00110
IR:
01001111
IR:
01001111
MAR: 01111
15: 00001010
MAR: 01111
MDR: 00001010
A:
00001010
MDR: 00001010
A:
06: 01001111
00001010
Location 0
ITEC 1000
15: 00001010
Location 0
ITEC 1000
06: 01001111
PC = PC + 1
Now:
Assume:
Location 31
Value in location 7 is 10110010.

Add instruction is 101.
Value in location 18 is seventy-one
(i.e.: binary 01000111)
Everything else is as we left it!
PC:
00111
IR:
01001111
MAR: 01111
18: 01000111
15: 00001010
MDR: 00001010
A:
Then ...
00001010
07: 10110010
06: 01001111
Location 0
ITEC 1000
ITEC 1000
PC -> MAR
MAR Accesses Location 00111

Location 31
PC:
00111
IR:
01001111
MAR: 00111
Location 31
PC:
00111
18: 01000111
IR:
01001111
15: 00001010
MAR: 00111
MDR: 00001010
A:
00001010
15: 00001010
MDR: 00001010
07: 10110010
06: 01001111
A:
00001010
Location 0
ITEC 1000
18: 01000111
07: 10110010
06: 01001111
Location 0
ITEC 1000
Contents of 00111 -> MDR
MDR -> IR
Location 31
PC:
00111
IR:
01001111
MAR: 00111
Location 31
PC:
00111
18: 01000111
IR:
10110010
15: 00001010
MAR: 00111
MDR: 10110010
A:
00001010
A:
00001010
IR [address] -> MAR
Location 10010 [MAR] Accessed

Location 31
00111
IR:
10110010
MAR: 10010
Location 31
PC:
00111
18: 01000111
IR:
10110010
15: 00001010
MAR: 10010
MDR: 10110010
A:
00001010
A:
Contents of [10010] -> MDR
00001010
IR:
10110010
MAR: 10010
IR [opcode] executed: A = A + MDR

Location 31
PC:
00111
18: 01000111
IR:
10110010
15: 00001010
MAR: 10010
MDR: 01000111
A:
00001010
18: 01000111
15: 00001010
MDR: 01000111
07: 10110010
06: 01001111
A:
01010001
Location 0
ITEC 1000
07: 10110010
06: 01001111
Location 31
00111
15: 00001010
Location 0
ITEC 1000
PC:
18: 01000111
MDR: 10110010
07: 10110010
06: 01001111
Location 0
ITEC 1000
07: 10110010
06: 01001111
Location 0
ITEC 1000
PC:
15: 00001010
MDR: 10110010
07: 10110010
06: 01001111
Location 0
ITEC 1000
18: 01000111
07: 10110010
06: 01001111
Location 0
ITEC 1000
LMC Instruction word format

To Continue:
If the next instruction were to load the Accumulator contents
into an area of memory reserved for screen output (for
example), then the number 81 should appear on the screen.
The process continues in the same fashion, more or less, until a
stop or halt instruction is encountered.
All communication between the LMC and the outside world

takes place using three-digit numbers
Instruction (Op Code )+ mailbox address (address field)
What To Do
Location of Data
3 25
ITEC 1000
ITEC 1000
LMC address field
A Simple 32-bit instruction

format
Unused (HALT- 000)

Extension of the op code (INPUT-901, OUTPUT902)
Contain the 2-digits address where data for the
instruction could be found ( LOAD-599) or was to
be placed (STORE -398)
To hold the location of the next instruction to be
executed (BR-614, BRZ-714, BRP-814)
Figure 7.14 A simple 32-bit instruction format

ITEC 1000
ITEC 1000
Data manipulation computer

instructions
Require the specification of at least 2

locations for the data :
Locations may be expressed :
ITEC 1000
One or more source locations

One destination location
Explicitly as address fields in the instruction
word
Implicitly as part of the definition of the
instruction itself.
Operands
The sources and destinations of data for an
instruction whether implicit or explicit are
also known as operands
Explicit address fields are known as
operand fields
ITEC 1000
Classification of instructions
Data movement instructions (LOAD, STORE, and
others)
Most frequently used, include instruction to move data
from memory to general registers, from general
registers to memory, between different general registers
Boolean logic instructions
Example: NOT, AND , OR instructions
Single operand manipulation instructions

Most of them operate on the value in the register, but
some of them operate on memory values as well
Example: increment a value, decrement a value or
resetting a value.
Arithmetic instructions
There may be several different integer arithmetic
instruction formats providing various combinations of
register and memory access in different addressing
modes
Bit manipulation instructions

Provide setting and resetting of individual bits in a
data word.
ITEC 1000
ITEC 1000
Shift and Rotate instructions
Shift and rotate instructions
Logical shift simply shift the data as you would expect,

and zeros are shifted in to replace the bit spaces that has
been vacated.
Arithmetic shift used to multiply or divide the original
value by a power of 2. The leftmost bit is not shift.
Rotate shift take the bits as they exit and rotate them
back into the other end of the register.
Page 192
Program control instructions control the flow of

a program, include jumps, branches and subroutine
CALL and RETURN instructions.
Figure 7.17 Typical register shifts and rotates
ITEC 1000
ITEC 1000
Shift and Rotate instructions
Stack instructions
10011001
-103
11001100
-52
11100110
-26
11110011
-13
Stack instructions
ITEC 1000
ITEC 1000
Stack data storage used to store data when

the most recently used data will be the first
needed. LIFO last-in, first-out structures.
Stacks are an efficient way of storing
intermediate data values during complex
calculations. Example: PUSH and POP
instructions
others
Using a Stack
Figure 7.19 Using a stack

ITEC 1000
Figure 7.22 Using a block of memory as a stack

ITEC 1000
Figure 7.18 Operation of CALL and RETURN instructions

ITEC 1000

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Outline of todays lecture

Time, location and coverage for midterm

ITEC 1000A Midterm

Summary of last weeks class

Introduction to Information Technologies

Introduction to Information Technologies

you should know how to write a short program.

3 short answer questions for definitions

7 questions about number representation,

Program counter (PC)

General purpose registers (R0, R1, )

Introduction to Information Technologies

Introduction to Information Technologies

Additionally 10's and 2's complement representation will be

These questions will be similar in format to the questions in

A dedicated register in the CPU.

Introduction to Information Technologies

A dedicated register in the CPU which contains the

Contains Address in memory to find or

Memory Data Register (MDR)

Simple 16-bit example:

Memory Address Register (MAR)

Introduction to Information Technologies

A dedicated register (or set of registers) in the CPU

Default source (or destination) register.

Memory data register

Memory address register

Introduction to Information Technologies

Introduction to Information Technologies

Generic CPU With Registers

Two steps, or cycles, in the execution of

Introduction to Information Technologies

Fetch fetch the code for the instruction from

Introduction to Information Technologies

Introduction to Information Technologies

The LOAD Instruction

Text: Page 177, Revised.

Text: Page 177, Revised.

The Add Instruction

Introduction to Information Technologies

Introduction to Information Technologies

Fetch-Execute Example: Load Accumulator

Simple Eight bit system.

Introduction to Information Technologies

Introduction to Information Technologies

MAR loaded with PC: PC -> MAR

Introduction to Information Technologies

Introduction to Information Technologies

Memory Location 00110 Accessed

Memory Location 00110 Accessed

Introduction to Information Technologies

MDR copied to IR: MDR -> IR

IR [ address part ] -> MAR

Location in MAR (01111) Accessed

Introduction to Information Technologies

Contents of 01111 loaded into MDR

Introduction to Information Technologies

Introduction to Information Technologies

Introduction to Information Technologies

Introduction to Information Technologies

IR [op code] executed: MDR -> A

Introduction to Information Technologies

Introduction to Information Technologies