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Table Of Contents
Introduction ...................................................................................................................................... 1
HDL Entry and Simulation Tutorial............................................................................................... 1
Introduction............................................................................................................................... 1
Starting Active-HDL.................................................................................................................. 1
Creating a New Workspace...................................................................................................... 2
Creating a New Design ............................................................................................................ 2
Code Editing ............................................................................................................................. 6
Simulation............................................................................................................................... 14
Introduction
HDL Entry and Simulation Tutorial
Introduction
This tutorial will guide you through the advanced Active-HDL design tool. This tutorial requires
basic knowledge of VHDL. If you have none, ALDEC EVITA Interactive Active-HDL Tutorial will
be a good starting point.
The Framework
The Active-HDL framework is based on a standard (Microsoft Foundation Class)-like GUI
interface. Each window can be docked, overlapped, or application-like. The main parts of ActiveHDL are:
Design Browser
Workspace/Design Explorer
HDL Editor
Block Diagram Editor
State Machine Editor
Standard Waveform Viewer/Editor
Accelerated Waveform Viewer
Console
Library Manager
Dataflow
Advanced Dataflow
List
Call Stack
Processes
Watch
Memory Viewer
Design Profiler
Code Coverage
Toggle Coverage
Code and Toggle Coverage Viewer
Starting Active-HDL
To start the program, go to the Start/Programs group and click the Active-HDL icon. The
Active-HDL should start loading, which is indicated by the The Active-HDL Welcome screen.
When the loading process finishes, the following dialog appears:
When the New Workspace wizard finishes its job, the New Design Wizard will be invoked.
Introduction
Entering the Design Name
In the next wizard dialog you will specify the design name, design folder, design type and working
library name.
Now, specify the name of the component, plus the name of its entity as shown on the picture
below.
CLK - in port
RESET - in port
Q[3:0] - out bus port , range [3:0]
After you have added a port, click the Type button. This will bring up a dialog that allows you to
choose the type of the port.
Introduction
.
The Design Browser Window After Compile Command.
Click the
Code Editing
sign
Introduction
HDL Editor
The HDL Editor is a text editor with HDL keywords coloring and standard editing features. ActiveHDL offers another useful feature that allows grouping, collapsing and expanding particular VHDL
constructs to improve readability of the code.
Introduction
Compiling Sources
Go to the Design Browser window, select the counter.vhd file and click the right mouse button.
Choose the Compile option from the shortcut menu.
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Simulation
Starting Simulation
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Introduction
To begin a simulation, you have to initialize the simulator first, using the Initialize Simulation
option from the Simulation menu. After the simulator has been initialized, you have to open a
new Waveform window. Click the New Waveform toolbar button . The new Waveform
window appears.
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Assigning Stimulators to Signals.
Choose the Stimulators option. The following window appears:
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Simulation results
Source Code Tracking
Active-HDL allows you to step through the code during simulation. The appropriate source code
is automatically opened while using Trace Into, Trace Over, or Trace Out buttons. The
statement which will be executed next, is shown in the HDL Editor window in yellow.
First you need to end the previous simulation run by selecting the End Simulation option from
the Simulation menu and reinitialize it by selecting Initialize option.
From the View menu choose the Watch, Processes and Call Stack options to invoke the
Watch, Processes and Call Stack windows.
The Processes window shows the status of design processes. The Watch window enables you
to examine values of signals and variables.
The Call Stack window is a debugging tool that displays a list of subprograms (procedures and
functions) being executed in the currently executed process. The term process is used here to
mean any concurrent statement modeling a sequential process in the elaborated model. Such
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Introduction
statements are process statements, concurrent signals assignment statements, concurrent
assertion statements, and concurrent procedure call statements (exactly the same as for the
Processes window). For each subprogram the window displays the following information:
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When a process is displayed in the center, it is represented as a rectangular box with input
signals on the left side and output signals on the right. Input signals are those read by the
process. Output signals are those updated by the process. When a signal is displayed in the
center, it is represented as a vertical thick line with processes connected to it on both sides.
Processes on the left side update the signal. Processes on the right side read the signal. You can
switch between these two views by clicking items in the Dataflow window.
In both views, signals are displayed with their names and processes are displayed with their
labels (either assigned explicitly by the user or generated automatically by the simulator). For
signals, the Dataflow window also displays their current values.
End the previous simulation run by selecting the End Simulation option from the Simulation
menu and reinitialize it by selecting Initialize option.
Select any signal from the Structure tab of the Design Browser window and choose the
Dataflow option from the context menu. As a result the Dataflow window shown below will be
invoked.
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