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Advance FPGA based Embedded and Digital System Designing By Ahsan Saeed
Advance FPGA based Embedded and Digital System Designing By Ahsan Saeed
Advance FPGA based Embedded and Digital System Designing By Ahsan Saeed

Advance FPGA based Embedded and Digital System Designing

By Ahsan Saeed

Agenda • Introduction • Manufacturers • Cost • Application Areas • Scope in Pakistan •
Agenda • Introduction • Manufacturers • Cost • Application Areas • Scope in Pakistan •
Agenda • Introduction • Manufacturers • Cost • Application Areas • Scope in Pakistan •

Agenda

Introduction

Manufacturers

Cost

Application Areas

Scope in Pakistan

Architecture

Language Basics

Testing Methodologies

Comparison with Microcontrollers

From where to start

“Device that can be re-program/re-configure to perform required task”
“Device that can be re-program/re-configure to perform required task”
“Device that can be re-program/re-configure to perform required task”

“Device that can be re-program/re-configure to perform required task”

“Device that can be re-program/re-configure to perform required task”
“Device that can be re-program/re-configure to perform required task”
How a FPGA Board Looks Like ?

How a FPGA Board Looks Like ?

How a FPGA Board Looks Like ?
FPGA Manufacturers • Xilinx and Altera are the current FPGA market leaders • Together, they

FPGA Manufacturers

Xilinx and Altera are the current FPGA market leaders

Together, they control over 80% of the market

Xilinx

Spartan Series (Low-Cost)

Kintex Series (Mid-Range)

Virtex Series (High-End)

Altera

Cyclone (Low-Cost)

Arria (Mid-Range)

Stratix (High-End)

Lattice Semiconductor

Atmel

MicroSemi

WILDSTAR 6 OpenVPX Card

WILDSTAR 6 OpenVPX Card
WILDSTAR 6 OpenVPX Card
WILDSTAR 6 OpenVPX Card
WILDSTAR 6 OpenVPX Card
WILDSTAR 6 OpenVPX Card
AMC Board Serves Up Dual Stratix IV FPGAs

AMC Board Serves Up Dual Stratix IV FPGAs

AMC Board Serves Up Dual Stratix IV FPGAs
How a FPGA Board Looks Like ?
How a FPGA Board Looks Like ?
How a FPGA Board Looks Like ?

How a FPGA Board Looks Like ?

How a FPGA Board Looks Like ?
How a FPGA Board Looks Like ?
How a FPGA Board Looks Like ?

How a FPGA Board Looks Like ?

How a FPGA Board Looks Like ?
Wideband Digital Receiver/Exciter Module Capable of digitizing analog input signals from below 50 MHz to
Wideband Digital Receiver/Exciter Module Capable of digitizing analog input signals from below 50 MHz to

Wideband Digital Receiver/Exciter Module

Capable of digitizing analog input signals from below 50 MHz to over 1.5 GHz

Wideband Digital Receiver/Exciter Module Capable of digitizing analog input signals from below 50 MHz to over
Wideband Digital Receiver/Exciter Module Capable of digitizing analog input signals from below 50 MHz to over
Wideband Digital Receiver/Exciter Module Capable of digitizing analog input signals from below 50 MHz to over
3U VPX Board Blends FPGA and TigerSHARC DSP hybrid signal processing architecture that takes advantage
3U VPX Board Blends FPGA and TigerSHARC DSP hybrid signal processing architecture that takes advantage

3U VPX Board Blends FPGA and TigerSHARC DSP

hybrid signal processing architecture that takes advantage of both FPGA and DSP technology

Blends FPGA and TigerSHARC DSP hybrid signal processing architecture that takes advantage of both FPGA and
Blends FPGA and TigerSHARC DSP hybrid signal processing architecture that takes advantage of both FPGA and
Blends FPGA and TigerSHARC DSP hybrid signal processing architecture that takes advantage of both FPGA and

6U FPGA-Based VME SBC Boasts Triple Redundancy

6U FPGA-Based VME SBC Boasts Triple Redundancy For some military embedded control applications and to ensure

For some military embedded control applications and to ensure the highest safety standards, the 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of the FPGA are triple-redundant.

standards, the 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of
standards, the 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of
standards, the 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of
standards, the 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of
Available in different sizes
Available in different sizes

Available in different sizes

Available in different sizes
Available in different sizes
Available in different sizes
Available in different sizes
Stratix V GX 100G Development Kit US$ 25,000
Stratix V GX 100G Development Kit US$ 25,000
Stratix V GX 100G Development Kit US$ 25,000
Stratix V GX 100G Development Kit US$ 25,000

Stratix V GX 100G Development Kit US$ 25,000

Stratix V GX 100G Development Kit US$ 25,000
Stratix V GX 100G Development Kit US$ 25,000
Stratix V GX 100G Development Kit US$ 25,000

FPGA Application Areas

Applications of FPGAs include

Digital Signal Processing

Software Defined Radio (SDR)

Space, aerospace and defense systems

ASIC prototyping

Medical imaging, bioinformatics

Computer vision, speech recognition

Cryptography

Computer hardware emulation

High speed communication, and a growing range of other areas

• Cryptography • Computer hardware emulation • High speed communication, and a growing range of other
• Cryptography • Computer hardware emulation • High speed communication, and a growing range of other
• Cryptography • Computer hardware emulation • High speed communication, and a growing range of other
Intel® Atom™ Processor E6x5C Series- Based Platform
Intel® Atom™ Processor E6x5C Series- Based Platform
Intel® Atom™ Processor E6x5C Series- Based Platform

Intel® Atom™ Processor E6x5C Series- Based Platform

Intel® Atom™ Processor E6x5C Series- Based Platform
National Instruments ® DAQ Cards

National Instruments ® DAQ Cards

National Instruments ® DAQ Cards
Broadcast/Audio/Video
Broadcast/Audio/Video
Broadcast/Audio/Video

Broadcast/Audio/Video

Broadcast/Audio/Video
Broadcast/Audio/Video
Broadcast/Audio/Video
Broadcast/Audio/Video
Broadcast/Audio/Video
Wireless
Wireless
Wireless

Wireless

Wireless
Wireless
Wireless
Wireless
Industrial, Test & Measurement
Industrial, Test & Measurement
Industrial, Test & Measurement
Industrial, Test & Measurement

Industrial, Test & Measurement

Industrial, Test & Measurement
Industrial, Test & Measurement
Industrial, Test & Measurement
Industrial, Test & Measurement
Consumer: Displays
Consumer: Displays
Consumer: Displays

Consumer: Displays

Consumer: Displays
Consumer: Displays
Consumer Gadgets
Consumer Gadgets

Consumer Gadgets

Consumer Gadgets
Consumer Gadgets
Consumer Gadgets
Consumer Gadgets
Consumer Gadgets
Consumer Gadgets

Scope of FPGA Technology

Different Public Sector R&D Organizations in Pakistan are working in FPGA based system designing

SUPARCO, Karachi and Lahore

AWC (Air Weapon Complex), Karachi

NDC (National Development Complex), Islamabad

Many Private Firms in Pakistan are developing Client based FPGA based system locally & internationally

Center for Advanced Research in Engineering (CARE), Islamabad

Digitek Engineering, Karachi

Ebryx, Lahore

Renzym, Islamabad

TeReSol (Technological Research Solutions), Islamabad

EPIC-Technologies, Islamabad

Lahore • Renzym, Islamabad • TeReSol (Technological Research Solutions), Islamabad • EPIC-Technologies, Islamabad
Lahore • Renzym, Islamabad • TeReSol (Technological Research Solutions), Islamabad • EPIC-Technologies, Islamabad
Lahore • Renzym, Islamabad • TeReSol (Technological Research Solutions), Islamabad • EPIC-Technologies, Islamabad
Technology Timeline
Technology Timeline
Technology Timeline

Technology Timeline

Technology Timeline
What is an FPGA? • Field Programmable Gate Array • Gate Array • Two-dimensional array

What is an FPGA?

Field Programmable Gate Array

Gate Array

Two-dimensional array of logic gates

Traditionally connected with customized metal

Every logic circuit (customer) needs a custom-manufactured chip

Field Programmable

Customized by programming after manufacture

One FPGA can serve every customer

FPGA: re-programmable hardware

Basic Internals of an FPGA Logic Logic Logic Element Element Element Logic Logic Logic Element
Basic Internals of an FPGA Logic Logic Logic Element Element Element Logic Logic Logic Element
Basic Internals of an FPGA Logic Logic Logic Element Element Element Logic Logic Logic Element

Basic Internals of an FPGA

Logic Logic Logic Element Element Element Logic Logic Logic Element Element Element Logic Logic Logic
Logic
Logic
Logic
Element
Element
Element
Logic
Logic
Logic
Element
Element
Element
Logic
Logic
Logic
Element
Element
Element
Element Logic Logic Logic Element Element Element Each logic element is programmed to to implement the

Each logic element is programmed to to implement the desired function

Programmable Connections

FPGA Architecture
FPGA Architecture
FPGA Architecture

FPGA Architecture

FPGA Architecture
Embedding a circuit in an FPGA • All done by CAD system • Chop up
Embedding a circuit in an FPGA • All done by CAD system • Chop up

Embedding a circuit in an FPGA

All done by CAD system

Chop up circuit into little pieces of logic

Each piece goes in a separate logic element (LE)

Hook them together with the programmable routing

y LE z f I/O Pad x
y
LE
z
f
I/O Pad
x

FPGA

f
f

Desired Circuit

x

(LE) • Hook them together with the programmable routing y LE z f I/O Pad x

y

z

I/O Pads

(LE) • Hook them together with the programmable routing y LE z f I/O Pad x
(LE) • Hook them together with the programmable routing y LE z f I/O Pad x
FPGA Logic Element • Look-Up Table (LUT) + register + extra … SRAM 0 LUT
FPGA Logic Element • Look-Up Table (LUT) + register + extra … SRAM 0 LUT

FPGA Logic Element

Look-Up Table (LUT) + register + extra …

SRAM 0 LUT Cell 0 0 Out 0 1 0 1 A B
SRAM
0
LUT
Cell
0
0
Out
0
1
0
1
A
B

A

B

… SRAM 0 LUT Cell 0 0 Out 0 1 0 1 A B A B

Out

FPGAs typically use 4-input or larger LUTs

Cyclone family (low cost): 4-inputs

or larger LUTs  Cyclone family (low cost): 4-inputs  Stratix II: Adaptive Logic Module implements
or larger LUTs  Cyclone family (low cost): 4-inputs  Stratix II: Adaptive Logic Module implements

Stratix II: Adaptive Logic Module implements 4 – 6 input LUTs efficiently

Virtex 5: 6 inputs

Connecting the Logic I/O Pads y LE z f I/O Pad x FPGA  Logic
Connecting the Logic I/O Pads y LE z f I/O Pad x FPGA  Logic
Connecting the Logic I/O Pads y LE z f I/O Pad x FPGA  Logic

Connecting the Logic

I/O Pads

y LE z f I/O Pad x
y
LE
z
f
I/O Pad
x

FPGA

Logic elements implement the pieces of the circuit

Now hook them up with the programmable routing

Programmable Routing • Programmable switches connect fixed metal wires • Choose pattern so any logic
Programmable Routing • Programmable switches connect fixed metal wires • Choose pattern so any logic

Programmable Routing

Programmable switches connect fixed metal wires

Choose pattern so any logic element can connect to any other

In2 Logic Block In1 Out
In2
Logic Block
In1
Out

SRAM

cell

fixed metal wires • Choose pattern so any logic element can connect to any other In2
fixed metal wires • Choose pattern so any logic element can connect to any other In2
fixed metal wires • Choose pattern so any logic element can connect to any other In2
Additional FPGA Components • Block RAM • Multiplier, Adder, MACs • Embedded Processor Core •

Additional FPGA Components

Block RAM

Multiplier, Adder, MACs

Embedded Processor Core

Clock Managers

High Speed Input Output Transceiver

DSP Blocks

Embedded Logic Analyzer

Processor Core • Clock Managers • High Speed Input Output Transceiver • DSP Blocks • Embedded
90nm Stratix II 2S60
90nm Stratix II 2S60
90nm Stratix II 2S60
90nm Stratix II 2S60

90nm Stratix II 2S60

FPGA vs Microcontroller Microcontroller FPGA Sequential execution Parallel execution One program instruction
FPGA vs Microcontroller Microcontroller FPGA Sequential execution Parallel execution One program instruction
FPGA vs Microcontroller Microcontroller FPGA Sequential execution Parallel execution One program instruction

FPGA vs Microcontroller

Microcontroller

FPGA

Sequential execution

Parallel execution

One program instruction executed at a time

Huge number of tasks can be performed simultaneously

State machine with 100 states

Change 100’s outputs at a time

Limited to on chip peripherals or on board peripherals

All needed digital hardware in one device

MCU has typically 3 to 5 on- chip timer

Huge number of timers and other peripherals

Limited number of Resources

Large number of Resources

Limited Speed

Fast can run upto Gb/s

Limited number of IO’s

 
We design Hardware in FPGA rather then Software
We design Hardware in FPGA rather then Software
We design Hardware in FPGA rather then Software

We design Hardware in FPGA rather then Software

We design Hardware in FPGA rather then Software

HDL Basics

HDL (Hardware Descriptive Language) is a Hardware Description Language. Used for FPGA Design Entry

It describes the hardware.

It enables specification of a digital system

Types:

Verilog HDL

VHDL

System Verilog (extension of Verilog )

C, C++ and System C ( Only in Vivado HLS for 7 series FPGAs and the Zynq Extensible Processing Platform only)

• C, C++ and System C ( Only in Vivado HLS for 7 series FPGAs and
• C, C++ and System C ( Only in Vivado HLS for 7 series FPGAs and
• C, C++ and System C ( Only in Vivado HLS for 7 series FPGAs and

Abstraction Level

Ground Level Details Flexibility in Programming
Ground Level Details
Flexibility in Programming

Not Used

Not Used Rarely Used Mostly Used Switch Level Gate Level Data Flow Level Behavioral Model

Rarely Used

Rarely Used

Mostly Used

Mostly Used

Switch Level

Gate Level

Data Flow Level

Behavioral

Model

Mostly, mixed Data Flow and Behavioral Modeling used

Modules • Basic Building Block in Verilog • A module is essentially a “box” or

Modules

Basic Building Block in Verilog

A module is essentially a “box” or “unit” containing the design like a Chip

A module is declared by the keyword module and ended with keyword endmodule

module must have a module_name & port_list

Port_list defines the input, output & inout ports of the module

module must have a module_name & port_list • Port_list defines the input, output & inout ports
module must have a module_name & port_list • Port_list defines the input, output & inout ports

Modules

module is like a CHIP

like Black Box when instantiates

module has some in, out or inout

there is logic inside a module that drives the output

Box when instantiates • module has some in, out or inout • there is logic inside
Box when instantiates • module has some in, out or inout • there is logic inside
Box when instantiates • module has some in, out or inout • there is logic inside
Box when instantiates • module has some in, out or inout • there is logic inside
Box when instantiates • module has some in, out or inout • there is logic inside
Modules Structure
Modules Structure
Modules Structure

Modules Structure

Modules Structure

Design Hierarchy

It is easy to structured the large complex logic into smaller elements/modules.

Design Hierarchy • It is easy to structured the large complex logic into smaller elements/modules.
Design Hierarchy • It is easy to structured the large complex logic into smaller elements/modules.
Design Hierarchy • It is easy to structured the large complex logic into smaller elements/modules.
Design Hierarchy • It is easy to structured the large complex logic into smaller elements/modules.
Design Hierarchy • It is easy to structured the large complex logic into smaller elements/modules.

Basic Design Example using Gate Level Modeling

Basic Design Example using Gate Level Modeling
Basic Design Example using Gate Level Modeling
Basic Design Example using Gate Level Modeling
Basic Design Example using Gate Level Modeling
Basic Design Example using Gate Level Modeling
4-Bit Full Adder using Data Flow Modeling modul e full_add er_ 4b it ( in1
4-Bit Full Adder using Data Flow Modeling modul e full_add er_ 4b it ( in1
4-Bit Full Adder using Data Flow Modeling modul e full_add er_ 4b it ( in1

4-Bit Full Adder using Data Flow Modeling

modul e full_add er_ 4b it ( in1 , in2 , ci n , sum
modul e full_add er_ 4b it ( in1 , in2 , ci n , sum , cout);
inpu t [ 3 : 0 ] i n 1, i n 2;
inpu t cin ;
output [3:0 ] sum ;
output out;
assign {sum,cou t } = in 1 + in 2 + ci n ;
endmodu le
4-1 Multiplexer using Behavioral Modeling module mux(in1, in2, in3, in4, sel, out); input in1, in2,
4-1 Multiplexer using Behavioral Modeling module mux(in1, in2, in3, in4, sel, out); input in1, in2,
4-1 Multiplexer using Behavioral Modeling module mux(in1, in2, in3, in4, sel, out); input in1, in2,

4-1 Multiplexer using Behavioral Modeling

module mux(in1, in2, in3, in4, sel, out); input in1, in2, in3, in4; input [1:0] sel;
module mux(in1, in2, in3, in4, sel, out);
input in1, in2, in3, in4;
input [1:0] sel;
output out;
always @(in1 or in2 or in3 or in4 or sel)
if(sel==2’b00)
out <= a;
else if(sel==2’b01)
out <= b;
else if (sel==2’b10)
out <= c;
else
out <= d;
endmodule
Test Methodologies • After Designing of the module, it is required to test and Verify

Test Methodologies

Test Methodologies • After Designing of the module, it is required to test and Verify the

After Designing of the module, it is required to test and Verify the module/design to check its functionality

Test Monitor could be simulation tools that simulate the design and check its output

Test Bench is a module that generate stimulus signals

good practice to keep the stimulus & design blocks separate

Finite State Machine (FSM) • A mathematical model of computation used to design both computer

Finite State Machine (FSM)

Finite State Machine (FSM) • A mathematical model of computation used to design both computer programs
• A mathematical model of computation used to design both computer programs and sequential logic
• A mathematical model of computation
used to design both computer programs
and sequential logic circuits
• Example: 01 & 10 Detector
Microcontroller Design in FPGA
Microcontroller Design in FPGA
Microcontroller Design in FPGA
Microcontroller Design in FPGA

Microcontroller Design in FPGA

Microcontroller Design in FPGA
Microcontroller Design in FPGA
Microcontroller Design in FPGA
Microcontroller Design in FPGA
Microcontroller Design in FPGA

Microcontroller Design in FPGA

Microcontroller Design in FPGA
FPGA Design Flow • Synthesis tools convert the actual design (Verilog code) to gate level

FPGA Design Flow

Synthesis tools convert the actual design (Verilog code) to gate level netlist

Implementation process include Map, Place & Route

Finally Bit Stream is created and downloaded into target technology (FPGAs)

Design is functionally tested on ModelSim Simulation Software

created and downloaded into target technology (FPGAs) • Design is functionally tested on ModelSim Simulation Software
Resources   Altera Xilinx Main Software Quartus II ISE and Vivado Programming Tool (Integrated)
Resources   Altera Xilinx Main Software Quartus II ISE and Vivado Programming Tool (Integrated)

Resources

 

Altera

Xilinx

Main Software

Quartus II

ISE and Vivado

Programming Tool

(Integrated)

Impact Tool

Embedded Logic Analyzer

SignalTap II

ChipScope Pro

Simulink ToolBox

DSP Builder

System Generator

Intellectual Properties (IP)

MegaWizard

CORE Generator

Simulation Software

Modelsim

Embedded Soft Processor

NIOS II

MicroBlaze / PicoBlaze

CORE Generator Simulation Software Modelsim Embedded Soft Processor NIOS II MicroBlaze / PicoBlaze
CORE Generator Simulation Software Modelsim Embedded Soft Processor NIOS II MicroBlaze / PicoBlaze
From Where to Start ?
From Where to Start ?
From Where to Start ?
From Where to Start ?
From Where to Start ?
From Where to Start ?

From Where to Start ?

Resources Required Software Required • ModelSim 10.1c • Used for simulation of the design •
Resources Required Software Required • ModelSim 10.1c • Used for simulation of the design •
Resources Required Software Required • ModelSim 10.1c • Used for simulation of the design •

Resources Required

Software Required

ModelSim 10.1c

Used for simulation of the design

Altera Quartus II 13.0sp1 Web Edition (available for free )

Used for Synthesis and Implementation of the design

SignalTap II (comes with Quartus II)

Used for Hardware-Software Co-Simulation

Qsys System Integration Tool (comes with Quartus II)

SOPC Builder tool (System On Programmable Chip)

DSP Builder (same version as that of Quartus II installed)

Implementing Simulink Code directly into FPGA

MATLAB (any version between R2010b to R2013a)

Version needs to be compatible with DSP builder version

Resources Required

Hardware Required

FPGA Boards

For Prototype Designing/Real time verification of the design

Programmer with cable

For Downloading FPGA Configuration (Bit Stream) File into Device

Books

FPGA Prototyping By Verilog Examples (Pong P. Chu)

Prerequisites

Digital Logic Design Basics (Flip Flops, Combinational and Sequential Circuits, Propagation Delays etc.)

State Machine Design Concept

and Sequential Circuits, Propagation Delays etc.) • State Machine Design Concept • Any programming language basics
and Sequential Circuits, Propagation Delays etc.) • State Machine Design Concept • Any programming language basics
and Sequential Circuits, Propagation Delays etc.) • State Machine Design Concept • Any programming language basics

Any programming language basics

Best Boards for Students and Beginners

Best Boards for Students and Beginners

Best Boards for Students and Beginners
Best Boards for Students and Beginners Altera DE Development and Education Boards
Best Boards for Students and Beginners Altera DE Development and Education Boards
Best Boards for Students and Beginners Altera DE Development and Education Boards
Best Boards for Students and Beginners Altera DE Development and Education Boards

Best Boards for Students and Beginners

Altera DE Development and Education Boards

Getting Insight
Getting Insight
Getting Insight
Getting Insight
Getting Insight
Getting Insight

Getting Insight

Digital Design Objectives

AREA on the chip required by the design

CRITICAL PATH DELAY of the design

TESTABILITY of the design

POWER dissipation by the circuit

the design • CRITICAL PATH DELAY of the design • TESTABILITY of the design • POWER
the design • CRITICAL PATH DELAY of the design • TESTABILITY of the design • POWER
the design • CRITICAL PATH DELAY of the design • TESTABILITY of the design • POWER
the design • CRITICAL PATH DELAY of the design • TESTABILITY of the design • POWER

DSP Implementation on FPGA

Y = (A * B) + (C*D) + (E*F) + (G*H)

DSP Implementation on FPGA Y = (A * B) + (C*D) + (E*F) + (G*H)
DSP Implementation on FPGA Y = (A * B) + (C*D) + (E*F) + (G*H)
DSP Implementation on FPGA Y = (A * B) + (C*D) + (E*F) + (G*H)
DSP Implementation on FPGA Y = (A * B) + (C*D) + (E*F) + (G*H)
Automotive • High Resolution Video & Graphics • Vehicle Networking and Connectivity • Unlike traditional

Automotive

High Resolution Video & Graphics

Vehicle Networking and Connectivity

& Graphics • Vehicle Networking and Connectivity • Unlike traditional multi-chip systems, Xilinx

Unlike traditional multi-chip systems, Xilinx Automotive single-device platforms greatly reduce BOM cost and increase system performance through programmable systems integration

Image Processing and Recognition

Image Processing and Recognition • High bandwidth to support camera systems requiring a minimum 30 frames/second

High bandwidth to support camera systems requiring a minimum 30 frames/second throughput

Processing and Recognition • High bandwidth to support camera systems requiring a minimum 30 frames/second throughput
Processing and Recognition • High bandwidth to support camera systems requiring a minimum 30 frames/second throughput
Processing and Recognition • High bandwidth to support camera systems requiring a minimum 30 frames/second throughput
Floating-point arithmetic on FPGAs IEEE 754 at a glance • specifies a common format for

Floating-point arithmetic on FPGAs

IEEE 754 at a glance

specifies a common format for representing floating-point numbers

comprises three basic components: the sign, the exponent, and the mantissa.

scientific representation of 30,064,771 is 3.0064771 x 10 7 , whereas 1.001 can be written as 1.001 x 10 0

3.0064771 is called the mantissa, 10 the exponent base, and 7 the exponent

1.001 can be written as 1.001 x 10 0 • 3.0064771 is called the mantissa, 10

Fixed-point arithmetic on FPGAs

Q-format notation

Has a specific number of bits (or digits) reserved for the integer part (the part to the left of the decimal point) and a specific number of bits reserved for the fractional part (the part to the right of the decimal point)

if N=16, 15 bit fractional representation Q15 format

part (the part to the right of the decimal point) • if N=16, 15 bit fractional
part (the part to the right of the decimal point) • if N=16, 15 bit fractional
part (the part to the right of the decimal point) • if N=16, 15 bit fractional
part (the part to the right of the decimal point) • if N=16, 15 bit fractional

Different Approaches ?

Working from scratch

Utilizing basic core and modifying/improving it

Using Intellectual Property (IP) Core

Using Simulink ToolBox

Using Embedded Processor

it • Using Intellectual Property (IP) Core • Using Simulink ToolBox • Using Embedded Processor
it • Using Intellectual Property (IP) Core • Using Simulink ToolBox • Using Embedded Processor
it • Using Intellectual Property (IP) Core • Using Simulink ToolBox • Using Embedded Processor
it • Using Intellectual Property (IP) Core • Using Simulink ToolBox • Using Embedded Processor
Using Intellectual Property (IP) Core • MegaWizard (Altera) • CORE Generator (Xilinx)
Using Intellectual Property (IP) Core • MegaWizard (Altera) • CORE Generator (Xilinx)

Using Intellectual Property (IP) Core

Using Intellectual Property (IP) Core • MegaWizard (Altera) • CORE Generator (Xilinx)

MegaWizard (Altera)

CORE Generator (Xilinx)

Using Intellectual Property (IP) Core • MegaWizard (Altera) • CORE Generator (Xilinx)
Using Intellectual Property (IP) Core • MegaWizard (Altera) • CORE Generator (Xilinx)

Using Simulink ToolBox

Using Simulink ToolBox • Design and simulate algorithms using MATLAB and Simulink. • DSP Builder (Altera)

Design and simulate algorithms using MATLAB and Simulink.

DSP Builder (Altera)

System Generator (Xilinx)

• Design and simulate algorithms using MATLAB and Simulink. • DSP Builder (Altera) • System Generator
• Design and simulate algorithms using MATLAB and Simulink. • DSP Builder (Altera) • System Generator
• Design and simulate algorithms using MATLAB and Simulink. • DSP Builder (Altera) • System Generator
• Design and simulate algorithms using MATLAB and Simulink. • DSP Builder (Altera) • System Generator
Using Simulink ToolBox

Using Simulink ToolBox

Using Simulink ToolBox
Using Embedded Processor • Altera • NIOS II • Qsys System Integration Tool • Eclipse
Using Embedded Processor • Altera • NIOS II • Qsys System Integration Tool • Eclipse

Using Embedded Processor

Altera

NIOS II

Qsys System Integration Tool

Eclipse IDE for Software Coding

MicroBlaze(Xilinx)

• Altera • NIOS II • Qsys System Integration Tool • Eclipse IDE for Software Coding
• Altera • NIOS II • Qsys System Integration Tool • Eclipse IDE for Software Coding
IP Core: Nios II Soft Processor • Three CPU Choices: • Nios II /f •
IP Core: Nios II Soft Processor • Three CPU Choices: • Nios II /f •
IP Core: Nios II Soft Processor • Three CPU Choices: • Nios II /f •

IP Core: Nios II Soft Processor

Three CPU Choices:

Nios II/f

Nios II/s

Nios II/e

Fast: Optimized for Performance

Standard: Faster and Smaller than Nios

Economy: Smallest FPGA Footprint

Choose peripherals you want

• SoPC Builder software builds bus interfaces, arbitration etc. Smaller Nios II/e Nios II/s Nios
• SoPC Builder software builds bus interfaces,
arbitration etc.
Smaller
Nios II/e
Nios II/s
Nios II/f
Faster
Soft Processors are Affordable Small Cyclone II 4600 LEs Nios II FPGA 600 LEs 13%
Soft Processors are Affordable Small Cyclone II 4600 LEs Nios II FPGA 600 LEs 13%
Soft Processors are Affordable Small Cyclone II 4600 LEs Nios II FPGA 600 LEs 13%

Soft Processors are Affordable

Small Cyclone II 4600 LEs

Nios II FPGA
Nios II
FPGA

600 LEs 13% of FPGA

Nios II/e “economy”

35¢ in lowest cost FPGA

Largest Stratix II 180,000 LEs

Nios II Nios II FPGA Nios II Nios II Nios II
Nios II
Nios II
FPGA
Nios II
Nios II
Nios II

1800 LEs, 1% of FPGA

Nios II/f “fast”

Massively Parallel Nios II Barco Media & Entertainment Olite 510 LED Display System Modular LED
Massively Parallel Nios II Barco Media & Entertainment Olite 510 LED Display System Modular LED
Massively Parallel Nios II Barco Media & Entertainment Olite 510 LED Display System Modular LED
Massively Parallel Nios II Barco Media & Entertainment Olite 510 LED Display System
Massively Parallel Nios II
Barco Media & Entertainment
Olite 510 LED Display System

Modular LED Display System 100 Nios II Processors per square meter!

Entertainment Olite 510 LED Display System Modular LED Display System 100 Nios II Processors per square

FPGA Used:

Entertainment Olite 510 LED Display System Modular LED Display System 100 Nios II Processors per square
Entertainment Olite 510 LED Display System Modular LED Display System 100 Nios II Processors per square
Entertainment Olite 510 LED Display System Modular LED Display System 100 Nios II Processors per square
• Email: ahsansaeed0@gmail.com
• Email: ahsansaeed0@gmail.com

Email: ahsansaeed0@gmail.com