DAC

Gain=

(1+R1/R2)

1.066

Theore
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

b3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

b1
b0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Device LSB =
Max/Min Values
Offset Error
Gain Error (zero offset)
Gain Error (incl offset)

Theoretical
0.00
0.33
0.67
1.00
1.33
1.67
2.00
2.33
2.67
3.00
3.33
3.66
4.00
4.33
4.66
5.00
0.333125000
0.00
7.14%
7.14%

Line
0.08
0.06
0.04
0.02
LSB

-1.38777878078145E-017
-0.02
-0.04
-0.06
-0.08
0

75.75

The full scale range is the difference between the output levels ideally corresponding t
and maximum input codes. It can be expressed either as a voltage or a current.
The practical full scale range is the difference between the most positive and most neg
outputs that can be achieved from the converter. It can be expressed either as a voltage

55.6 1.51515E-005
53.84
8.94352159
Fmax
656.5141403

SR = *Vo

fmax

660Hz input/sampling freq

Freq
dB
f1
3.6
f2
-15.2
f3
-17.6
f4
-20.8
f5
-24.4
f6
-24.4
f7
-28.4

66kHz
Gain
1.51356125
0.17378008
0.13182567
0.09120108
0.06025596
0.06025596
0.03801894

SFDR

Ideal SNR

SINAD

15.49914

ENOB = [SINAD - 1.76]/6.02.

ENOB=
2.282249

222816.9203

THD (dB)

18.8 dB

25.84

-15.50

660Hz

Comparison of Results (Ideal Design, Simulation and Practical)

Theoretical/Ideal Calculations
T_Segment
DNL_D
INL_D
Simulated
0
0
0.01
0.33
0.000000
0
0.34
0.33
0.000000
0
0.68
0.33
0.000000
0
1.01
0.33
0.000000
0
1.34
0.33
0.000000
0
1.67
0.33
0.000000
0
2.00
0.33
0.000000
0
2.33
0.33
0.000000
0
2.66
0.33
0.000000
0
3.00
0.33
0.000000
0
3.33
0.33
0.000000
0
3.66
0.33
0.000000
0
3.99
0.33
0.000000
0
4.32
0.33
0.000000
0
4.65
0.33
0.000000
0
4.99
0.00
0.331793333
0.000
0.000
0.01
7.12%
6.84%

Linearity Error

DNL_P
INL_P
DNL_D
INL_D
DNL_S
INL_S

6
Codes

10

12

14

ADC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

(theoretical)
b3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Gain=
b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

deally corresponding to the minimum

e or a current.
positive and most negative analog
sed either as a voltage or a current.

0.8000
0.6000
0.4000
0.2000
LSB

0.0000
-0.2000
-0.4000
-0.6000
-0.8000
0

-0.4000
-0.6000
-0.8000
0

2.4
-42.4
-46
-49.2
-51.6

nd Practical)
Simulation Results
S-Segment
0.33
0.33
0.34
0.33
0.33
0.33
0.33
0.33
0.34
0.33
0.33
0.33
0.33
0.33
0.34

DNL_P
INL_P
DNL_D
INL_D
DNL_S
INL_S

Unity
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Device LSB
Max/Min Values
Offset Error
Gain Error (zero offset)
Gain Error (incl offset)

voltage
0.32
0.68
1.11
1.43
1.68
1.95
2.35
2.64
2.93
3.15
3.37
3.73
4
4.29
4.55
4.8
0.298666667

Simulated Results
w simulated
DNL_S
0.36
0.43
0.32
0.25
0.27
0.4
0.29
0.29
0.22
0.22
0.36
0.27
0.29
0.26
0.25

0.2053571429
0.4397321429
0.0714285714
-0.1629464286
-0.0959821429
0.3392857143
-0.0290178571
-0.0290178571
-0.2633928571
-0.2633928571
0.2053571429
-0.0959821429
-0.0290178571
-0.1294642857
-0.1629464286
0.0
0.4397321429

0.32
6.64%
-0.5%

Linearity Error

8
Codes

10

8
Codes

10

Pr
DNL_S
0.000000
-0.002692
-0.002391
0.009665
-0.005405
-0.005405
-0.005405
-0.005405
-0.005405
0.024734
-0.005405
-0.005405
-0.005405
-0.005405
-0.005405
0.024734
0.00
0.025

INL_S
0.000000
-0.002692
-0.005083
0.004581
-0.000824
-0.006229
-0.011634
-0.017039
-0.022444
0.002291
-0.003114
-0.008519
-0.013924
-0.019329
-0.024734
0.000000

Practical
-0.06
0.27
0.61
0.95
1.28
1.62
1.96
2.3
2.64
2.99
3.33
3.67
3.99
4.32
4.66
5
0.337333333

-0.025
-0.06
7.23%
8.52%

Device LSB =
Max/Min INL
Max/Min DNL
Offset Error
Gain Error (zero offset)
Gain Error (incl offset)

INL_S
0
0.2053571429
0.6450892857
0.7165178571
0.5535714286
0.4575892857
0.796875
0.7678571429
0.7388392857
0.4754464286
0.2120535714
0.4174107143
0.3214285714
0.2924107143
0.1629464286
0
0.796875

1
voltage
0.00
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
0.312500000
Max/Min Values
Offset Error
Gain Error (zero offset)
Gain Error (incl offset)

w ideal
0
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31

Design Ideal Results

DNL_D
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000

0.00
7.14%
7.14%

DNL_D
INL_P
DNL_P
INL_D
DNL_S
INL_S

10

12

14

10

12

14

SNR

Vref
Practical Unit Results
P_Segment
DNL_P
0
0.33
-0.0217391304
0.34
0.0079051383
0.34
0.0079051383
0.33
-0.0217391304
0.34
0.0079051383
0.34
0.0079051383
0.34
0.0079051383
0.34
0.0079051383
0.35
0.0375494071
0.34
0.0079051383
0.34
0.0079051383
0.32
-0.0513833992
0.33
-0.0217391304
0.34
0.0079051383
0.34
0.0079051383
0.00
0.038

Device LSB =
Max/Min INL
Max/Min DNL
Offset Error
ain Error (zero offset)
ain Error (incl offset)

Design
0.333125000
0.00
0.00
0.00
7.14%
7.14%

INL_P
0
-0.0217391304
-0.0138339921
-0.0059288538
-0.0276679842
-0.0197628458
-0.0118577075
-0.0039525692
0.0039525692
0.0415019763
0.0494071146
0.057312253
0.0059288538
-0.0158102767
-0.0079051383
0

5.00
Code
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0.057

Simulation
0.331793333
-0.025
0.025
0.01
7.12%
6.84%

Practical
0.337333333
0.057
0.038
-0.06
7.23%
8.52%

eal Results
INL_D
non ideal voltages
0.000000
0.08
0.000000
0.32
0.000000
0.6
0.000000
0.92
0.000000
1.24
0.000000
1.56
0.000000
1.92
0.000000
2.24
0.000000
2.56
0.000000
2.88
0.000000
3.16
0.000000
3.52
0.000000
3.8
0.000000
4.12
0.000000
4.48
0.000000
4.8
Device LSB
0.3146666667
Max/Min Values
Offset Error
Gain Error (zero offset)
Gain Error (incl offset)

Vfs
N
Vref

5
4
5.33

Practical Unit Results

w non ideal
0.24
0.28
0.32
0.32
0.32
0.36
0.32
0.32
0.32
0.28
0.36
0.28
0.32
0.36
0.32

0.08
7.02%
5.23%

volts
bits
volts

DNL_P

-0.2372881356
-0.1101694915
0.0169491525
0.0169491525
0.0169491525
0.1440677966
0.0169491525
0.0169491525
0.0169491525
-0.1101694915
0.1440677966
-0.1101694915
0.0169491525
0.1440677966
0.0169491525
0.0
-0.2372881356

1kHz input/sampling freq 132kHz

Freq
dB
f1
2.8
f2
-17.2
f3
-22
f4
-28

SFDR

Gain
1.3803842646
0.1380384265
0.0794328235
0.0398107171

THD (dB)

-18.49

20

37
SNR=

18.804560645

(volts)
error
0%
-18.9%
-8.4%
-4.9%
-3.9%
-2.7%
-1.9%
-1.4%
-0.9%
-0.3%
0.0%
0.2%
-0.2%
-0.2%
-0.1%
0.1%

offset
-0.06
-0.063125
-0.05625
-0.049375
-0.0525
-0.045625
-0.03875
-0.031875
-0.025
-0.008125
-0.00125
0.005625
-0.0075
-0.010625
-0.00375
0.003125

Offset Error =
Gain Error

INL_P
0
-0.237288
-0.347458
-0.330508
-0.313559
-0.29661
-0.152542
-0.135593
-0.118644
-0.101695
-0.211864
-0.067797
-0.177966
-0.161017
-0.016949
0

error

offset

-0.347458

Device LSB =
Max/Min INL
Max/Min DNL
Offset Error
Gain Error (zero offset)
Gain Error (incl offset)

Design
0.312500000
0.00
0.00
0.00
7.14%
7.14%

Simulated
0.298666667
0.797
0.440
0.320
6.64%
-0.47%

Practical
0.314666667
-0.347
-0.237
0.08
7.02%
5.23%

dB

18.19544

SNR

Code

Analogue

UoM

V(0000)
V(1111)

-0.06
5
8.5%

volts
volts