Solid-State Electronics xxx (2015) xxxxxx

Contents lists available at ScienceDirect

Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse

A comparative mismatch study of the 20 nm Gate-Last and 28 nm

Gate-First bulk CMOS technologies
Lama Rahhal a,b,, Aurelie Bajolet a, Jean-Philippe Manceau c, Julien Rosa a, Stephane Ricq a,
Sebastien Lassere c, Gerard Ghibaudo b
a
b
c

STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles, France

IMEP-LAHC, Minatec/INPG, BP 257, 38016 Grenoble, France
IBM, 850, rue Jean Monnet, 38926 Crolles, France

a r t i c l e

i n f o

Article history:
Available online xxxx
The review of this paper was arranged by
B. Gunnar Malm
Keywords:
Vt
b
ID
Rsd
Mismatch
20 nm Gate-Last
28 nm Gate-First
EOT (Tox)

a b s t r a c t
In this work the threshold voltage (Vt), the current gain factor (b), and the drain current (ID) mismatch
trends for 20 nm Gate-Last bulk CMOS technology integrating High-k/metal gate are investigated. The
reported results indicate that the high k/metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the Vt mismatch and good performance in terms of the b mismatch. This study further demonstrates that the ID variability mainly depends on the mismatch trends of Vt and b, and on the
contributions of the transconductance divided by the drain current (Gm/ID) and the source drain series
resistance (Rsd) terms. The 20 nm Gate-Last technology exhibits signicant improvement in the Vt and
b mismatch performance as compared to the 28 nm Gate-First counterpart. The evolution of the Vt and
b mismatch parameters, iADVt and iADb/b, is further analyzed as a function of the electrical oxide thickness
EOT (Tox) along the technology nodes from 90 nm to 20 nm. A clear trend towards a reduction of the yaxis intercept (i.e. offset) of the linear plot of iADVt as a function of EOT is observed starting at the 28 nm
Gate-First technology, with the offset approaching zero for the 20 nm Gate-Last technology node. This
observation point out a considerable decrease of the gate material contribution to mismatch
performances.
2015 Published by Elsevier Ltd.

1. Introduction
For correct operation, analogue and digital applications such as
power ampliers or Static Random Access Memories (SRAM) cells
require pairs of transistor devices. These pairs should be identically
designed and laid out in an identical environment in order to
ensure identical electrical performances. Real devices, however,
suffer from variations in the electrical parameters, a problem
known as mismatch. This problem is mainly due to intrinsic
sources of random dispersions. These sources arise from stochastic
variations inherent to the discrete nature of dopant impurities,
point defects, or, more generally, the random character of processing steps.
The rst mismatch studies have started in 1972 with Hoeneisen
and Mead [1]. They observed that random dopant uctuation in the
MOSFETs body can result in unpredictable threshold voltage val Corresponding author at: IMEP-LAHC, Minatec/INPG, BP 257, 38016 Grenoble,
France.
E-mail address: lama.rahhal@st.com (L. Rahhal).

ues, and that such unpredictability can gravely hinder advances

in MOSFET technologies. The same problem was also studied by
Keyes [2], whose work was focused on the creation of a model to
predict the amplitude of the threshold voltage variations, without
considering the MOSFET operation. Shyu et al. also created a complete mismatch model for MOS capacitors and MOS transistors [3]
by considering as source of variability the uctuations in the physical dimensions of the active zone and in the process parameters.
Based on this model, Lakshmikumar et al. experimentally demonstrated the dimensional dependence of mismatch in MOS devices
[4]. In 1989 Pelgrom et al. indicated a direct dependency between
the local uctuations of an electrical parameter P and the channel
area (denoted as S) through a coefcient A [5]. This is known as Pelgroms Law, expressed in (1),

rDP p :
S

These preliminary studies, in combination with the miniaturization of MOSFET devices, have set the ground for increasing
research efforts aimed at achieving a deeper understanding of

http://dx.doi.org/10.1016/j.sse.2014.12.006
0038-1101/ 2015 Published by Elsevier Ltd.

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.006

L. Rahhal et al. / Solid-State Electronics xxx (2015) xxxxxx

Table 1
Characteristics of the devices under test.
20 nm Gate-Last
EOT (Tox)

PMOS
transistors

GO1: 12.48 A
/12.7 A
(NMOS/
PMOS)
0

High k
Metal Gate

28 nm Gate-First

(NMOS/
GO2: 31.6
A/32.9 A
PMOS)
SiON/HFO2
Based on TiN/TaN/Al
(NMOS/PMOS)
Si channel

GO1: 15.7 A
/17.1 A
(NMOS/
PMOS)

identical environment and are electrically independent with symmetrical connections.

The dimensions of the devices used in this study are detailed in
Table 2 for 20 nm Gate-Last and 28 nm Gate-First technologies.
Tests have been performed in linear regime with:

HFSION
TiN/AO (NMOS)
TiN/AO/TiN/Al/TiN
(PMOS)
SiGe channel

the causes of mismatch phenomena and characterizing their

effects, with the objective of guaranteeing reliable integrated circuits performance.
Recent mismatch studies such as [69] demonstrated that the
main contributing factors to the threshold voltage (Vt) mismatch
in advanced Bulk High-k/metal gate technology are the Random
Dopant Fluctuations (RDF), the Line Edge Roughness (LER), and
the Metal Gate Granularity (MGG).
The implantation and activation of self-aligned source and drain
induces a poly-crystallization of the metal gate [10,11]. The created
grains have inconsistent orientation and work functions, and grow
in size until reaching dimensions that are comparable to the gate
length. This phenomenon is known as Metal Gate Granularity
(MGG). One of the proposed solutions to eliminate the variability
due to MGG is the use of Gate-Last technology, in which the metal
gate is deposited after the implantation and the activation processes. The metal does not undergo high temperature treatments
and maintains therefore its amorphous phase, with nanometerscale grain sizes [12,13]. The adoption of Gate-Last technology in
advanced bulk MOSFETs integrating High-k and metal gate is thus
a promising solution that can help to reduce the Vt mismatch.
Some simulation studies by Asenov et al. [14] have been
reported in literature on the advantages of Gate-Last technology
in terms of reducing the Vt mismatch as compared to Gate-First
technology. Moreover a recent work by Fukutome et al. [15]
showed that low Vt mismatch can be obtained for Gate-Last technology by using embedded SiGe interface engineering, resulting
in lower interface states density.
In this study the threshold voltage Vt, the current gain factor b,
and the drain current ID mismatch performances are investigated
in the recent 20 nm Gate-Last bulk CMOS technology. The values
of Vt and b for this technology are also compared to those observed
in the 28 nm Gate-First bulk technology. Finally, the trends of the
Vt and b mismatch parameters across the nodes from 90 nm ST
technology down to 20 nm Gate-Last technology are plotted and
conclusions drawn.

2. Experimental details
Electrical characterization was performed on bulk NMOS/PMOS
transistors on two wafers processed with 20 nm Gate-Last International Semiconductor Development Alliance (ISDA) and 28 nm
Gate-First technologies, with integrated High-k gate oxide and
metal gate. The characteristics of the devices under test are
detailed in Table 1. Note that, for the 20 nm Gate-Last technology,
two equivalent gate oxide thicknesses are available (GO1 versus
GO2). For matching measurements, a sample of 76 pairs of identical MOS transistors has been considered. The two MOSFETs of the
pair are spaced by the minimum allowed distance, laid out in an

Drain voltage |VD| = 0.05 V and gate voltage 0 6 |VG| 6 0.9 V for
20 nm GO1 devices.
Drain voltage |VD| = 0.1 V and gate voltage 0 6 |VG| 6 1.8 V for
20 nm GO2 devices.
Drain voltage |VD| = 0.05 V and gate voltage 0 6 |VG| 6 1 V for
28 nm GO1 devices.
All presented results refer to measurements performed at 25 C.
For matching studies, an electrical parameter P is measured for
each of the two devices in the pair. The variation of P noted DP (or
DP/P) within the pair is calculated. This method is then repeated
for the 76 samples present on each wafer. A recursive lter is then
applied to this population to exclude erroneous data. The number
of rejected data points ranges between 0 and 5 in all wafers tested
for this work. Once the ltered data is proven to follow a Gaussian
distribution centered on 0, the standard deviation rDP (or rDP/P) of
the distribution is calculated.
With the miniaturization of MOS transistors, different phenomena affecting the Vt values are observed, such as short channel
effects (SCE) or the effect of pocket implants in the channel. These
phenomena may cause various deviations from Pelgroms law, as
in the example case of ADP (P = Vt in this case), which is not constant any more [1618]. An individual constant of matching (iADP)
is thus introduced, allowing the evaluation of the mismatch values
for each channel dimension (Length (L) and width (W)), as shown
in (2),

iADP rDP 

p
W L

This parameter is used in this study with the purpose of evaluating the mismatch properties in the 20 nm Gate-Last technology
and comparing the performances to the 28 nm Gate-First
technology.
3. Comparison between devices with channel pocket implants
and different oxide thicknesses EOT (Tox) in 20 nm Gate-Last
technology
The Vt, b, and ID mismatch are analyzed in the 20 nm Gate-Last
technology by comparing GO1 and GO2 devices with different
oxide thicknesses shown in Table 1. This comparison enables a discussion on the possibility of reducing or suppressing the metal gate
granularity effect in the 20 nm Gate-Last technology.
3.1. Threshold voltage variability
The Vt values were rst measured, using the maximum slope
method [19], for GO1 and GO2 devices with thinner and thicker
gate oxide, respectively. The results are plotted in Fig. 1 as a function of the gate length (L). NMOS GO2 devices exhibit higher |Vt|
values compared to PMOS GO2 devices. Moreover, for GO2 PMOS
devices a width (W) effect is observed. Indeed for the same gate
length, when W is increased Vt is decreased. For example in
Fig. 1, for L = 0.1 lm, when W values vary from 2 lm down to
0.16 lm, the corresponding Vt values are increasing from 0.48 V
up to 0.53 V.rDVt values for GO1 and GO2 N/PMOS devices of
20 nm Gate-Last technology are then calculated and plotted as a
function of 1/W  L in Fig. 2. This Graph shows that while GO1 N/
PMOS transistors follows Pelgroms Law except for very large areas,
GO2 devices are much more dispersed. This higher dispersion may

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.006

L. Rahhal et al. / Solid-State Electronics xxx (2015) xxxxxx

Table 2
The dimensions of the devices under test for 20 nm Gate-Last and 28 nm Gate-First.
20 nm Gate-Last GO1

20 nm Gate-Last GO2

W (lm)

L (lm)

W (lm)

L (lm)

W (lm)

L (lm)

0.072
0.072
0.45
0.9
0.9
0.9
4.5
9
9
0.45
0.9
0.9
0.072
0.45
0.9
0.45

0.03
0.048
0.093
0.03
0.048
0.903
0.453
0.03
0.903
0.03
0.057
0.219
0.903
0.453
0.093
0.219

0.06
0.2
0.3
0.5
1
0.06
0.2
0.2
0.2
0.3
1
0.06
0.2
1
0.5
0.5
1
0.5
1
0.5
1
0.5
0.5

0.02
0.02
0.02
0.02
0.02
0.024
0.026
0.028
0.024
0.024
0.024
0.034
0.034
0.034
0.024
0.034
0.06
0.06
0.08
0.08
1
1
2

0.32
0.16
0.5
0.32
0.16
0.5
0.32
0.16
2
2
2
2
2
2
2
0.5

0.15
0.15
0.1
0.1
0.1
0.07
0.07
0.07
0.5
0.3
0.2
0.15
0.12
0.1
0.07
0.15

0.06
0.05

Vt (V)

28 nm Gate-First GO1

0.07

0.04
0.03

NMOS GO1

0.02

NMOS GO2
PMOS GO1

0.01

PMOS GO2

0
0

10

20

1/ W.L (1 /

30

m2)

Fig. 2. Pelgrom plot: comparison of rDVt (V) as a function of the transistor surface 1/
W  L (1/lm2) between GO1 and GO2 for NMOS and PMOS devices of the 20 nm
Gate-Last technology.

9
8
7

iAVt(mV.m)

0.7
0.6

|Vt| (V)

0.5
0.4

5
4
3
NMOS, GO1
NMOS, GO2
PMOS, GO1
PMOS, GO2

0.3

NMOS,GO1
NMOS,GO2
PMOS,GO1
PMOS,GO2

0.2
0.1
0.0
0.01

0.1

0
1E-3

0.01

0.1

W.L (m )
Fig. 3. Comparison of iADVt (mV lm) as a function of the transistor surface W  L
(lm2) between GO1 and GO2 for NMOS and PMOS devices of the 20 nm Gate-Last
technology.

L (m)
Fig. 1. Comparison of |Vt| (V) as a function of the transistor length L (lm) between
GO1 and GO2 for NMOS and PMOS devices of the 20 nm Gate-Last technology.

due to process variations that might be not well controlled for GO2
devices. Note that in the future, further investigations should be
done to understand and quantify this phenomenon.
The individual mismatch constant is then calculated using (2),
for each geometry, and plotted as a function of the transistor surface W  L (lm2) in Fig. 3. The graph shows higher degradation of
the iADVt values in N/PMOS GO2 devices as compared to N/PMOS
GO1 devices for different values of W  L (lm2).
To explain the observed phenomenon, the effective channel
doping (Na) was extracted for long devices W = 1 lm/L = 1 lm
(GO1) and W = 2 lm/L = 0.5 lm (GO2) using (3) and (4) detailed
in [20], with the bulk bias shown in Table 3:

dV t
Cd

dV b
C ox
s

 
Na
C d Na q  esi  Na
4  K  T  ln
ni

where Cd is the channel depletion capacitance, Cox is the oxide

capacitance, esi is the channel permittivity, ni is the intrinsic carrier
concentration, K is the Boltzmann constant, and T is the measurement temperature in Kelvin.
The obtained values for Na, detailed in Table 4, show very feeble
difference between GO1 and GO2 devices. The individual mismatch
parameter of the channel depletion charge Qd was then calculated
using (5) in order to normalize the Vt mismatch and eliminate the
Tox dependency.

rDQd Cox  rDVt

5
2

The results, plotted in Fig. 4 as a function of W  L (lm ), interestingly show that N/PMOS GO1 and GO2 devices exhibit comparable iADQd values over the studied range of W  L. This similarity
suggests that the Vt mismatch scales with Tox and further indicates,
based on (6) [18], that in the 20 nm Gate-Last technology the channel contribution to the Vt mismatch is much more pronounced
than the gate contribution.

s
t 2ox q  Q d
AVt t ox

;
e2ox 4

where eox is the oxide permittivity.

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
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L. Rahhal et al. / Solid-State Electronics xxx (2015) xxxxxx

Table 3
Bulk bias values used to extract the channel effective doping (Na).
GO1 devices (W = 1 lm/
L = 1 lm)

GO2 devices (W = 2 lm/

L = 0.5 lm)

3.0

Vb = 0.5 V & Vb = 0 V
Vb = 0.5 V & Vb = 0 V

Vb = 1 V & Vb = 0 V
Vb = 1 V & Vb = 0 V

2.5

i A / (% . m )

NMOS
PMOS

3.5

Table 4
Effective channel doping in the 20 nm Gate-Last technology.

Na NMOS
Na PMOS

GO1 devices
(W = 1 lm/L = 1 lm) (cm3)

GO2 devices
(W = 2 lm/L = 0.5 lm) (cm3)

1.21  1018
1.90  1018

1.12  1018
9.98  1017

NMOS, GO1
NMOS, GO2
PMOS, GO1
PMOS, GO2

2.0
1.5
1.0
0.5
0.0
1E-3

0.01

0.1

W.L (m )
Fig. 5. Comparison of iADb/b (% lm) as a function of the transistor surface W  L
(lm2) between GO1 and GO2 for NMOS and PMOS devices of the 20 nm Gate-Last
technology.

-4

1.4x10

i A Q d (F. m V. m)

-4

1.2x10

-4

1.0x10

NMOS, GO1
NMOS, GO2
PMOS, GO1
PMOS, GO2

compared to GO2 devices for NMOS transistors and improved mismatch values for PMOS transistors. Note also that, for large areas,
GO1 and GO2 PMOS devices are more dispersed.
To understand the phenomenon observed in the measurement
data for ID mismatch, the Croon model [21] expressed in (7) and
the improved Croon model [22] equated in (8) were plotted for
GO1 and GO2 NMOS transistors in Fig. 7a and b respectively.

-5

8.0x10

-5

6.0x10

-5

4.0x10

-5

2.0x10

0.01

0.1

W.L (m

)
2

Fig. 4. Comparison of iADQd (F mV lm) as a function of W  L (lm ) between GO1

and GO2 for NMOS and PMOS devices of the 20 nm Gate-Last technology.

The two previous conclusions demonstrate that by using a

Gate-Last technology and thus improving the MGG effect, the gate
contribution to the Vt mismatch can be effectively suppressed.
3.2. Current gain factor variability
The current gain factor (b) was also extracted using the maximum slope method [19]. The b individual constant of mismatch
was then calculated using (2) for each transistor geometry. The
results are plotted in Fig. 5, indicating that both N/PMOS GO1
devices exhibit signicant improvement and lower b mismatch
dispersion as compared to GO2 transistors.
3.3. Drain current variability
The drain current mismatch was nally investigated in GO1 and
GO2 devices. The drain current was measured in linear regime with
|VD| = 0.05 V and |VG| = 0.9 V for GO1 (N/P) devices and |VD| = 0.1 V
and |VG| = 1.8 V for GO2 devices. The individual constant of mismatch was then calculated using (2) and the results plotted in
Fig. 6.
The graph of Fig. 6 shows that, for small devices
(W  L < 0.1 lm2), no signicant variation is observed between
GO1 and GO2 N/PMOS transistor devices. The values for GO1 and
GO2 PMOS devices are however very dispersed. For larger dimensions (W  L P 0.1 lm2), GO1 exhibit degraded mismatch values as

 2
Gm
Gm
 r2DVt r2Db=b  2
rDV T  rDb=b
ID
ID
 qDVt; Db=b

r2DID =ID

 2
Gm
Gm
 r2DVt 1  Gd  Rsd 2  r2Db=b  2
ID
ID
 1  Gd Rsd  rDV T  rDb=b  qDVt; Db=b

Fig. 7a shows that Croons model and the improved Croon

model reproduce the measured ID mismatch data, indicating that
the Rsd contribution to the ID mismatch is negligible in GO1 devices.
The graph also shows that for W  L 6 0.1 lm2, the b mismatch
term is more pronounced than the Vt mismatch term, dominating
the ID mismatch as a function of W  L. As for W  L > 0.1 lm2 the

3
2.5

iA ID/ID (%.m)

0.0
1E-3

r2DID =ID

NMOS GO1
NMOS GO2
PMOS GO1
PMOS GO2

2
1.5
1
0.5
0
0.001

0.01

W.L (m2)

0.1

Fig. 6. Comparison of iADID/ID (% lm) as a function of the transistor surface W  L

(lm2) between GO1 and GO2 for NMOS and PMOS devices of the 20 nm Gate-Last
technology.

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.006

L. Rahhal et al. / Solid-State Electronics xxx (2015) xxxxxx

0.1

0.5

Vt(V)

0.01

( ID/ID )2

0.6

(ID/ID)2 measured
Croon model Eq.7
Improved Croon Model Eq.8
Vt mismatch Term in Eq.8
mismatch Term in Eq.8

0.001

0.1

(a)

GO1

0.00001
0.001

0.01

0.1

(W.L)
1

0.01

PMOS 20 nm Gate last

PMOS 28nm Gate first
NMOS 20 nm Gate last
NMOS 28nm Gate first

0
0.01

(m 2)

9
8
7

iA Vt (mV.m)

0.0001
0.00001
GO2

(b)
0.1

W.L

(m 2)

PMOS 20 nm Gate last

PMOS 28nm Gate first
NMOS 20 nm Gate last
NMOS 28nm Gate first

6
5
4
3
2

Fig. 7. 20 nm Gate-Last technology: measured rDID/ID, Croon model and improved

Croon Model as a function of the transistor surface W  L (lm2) for (a) GO1 and (b)
GO2 NMOS devices.

3.5

Fig. 9. Comparison of |Vt| (V) as a function of L (lm) between NMOS and PMOS
devices of the 28 nm Gate-First and 20 nm Gate-Last technologies.

0.001

0.000001
0.01

0.1

L (m)

(ID/ID)2 measured
Croon model Eq. 7
Improved Croon Model Eq.8
Vt mismatch Term in Eq.8
mismatch Term in Eq. 8

0.1

( ID/ID)2

0.3
0.2

0.0001

Gm/ID (Simens/A)

0.4

1
0
0.01

0.1

L (m)

NMOS GO1
NMOS GO2
PMOS GO1
PMOS GO2

Fig. 10. Comparison of iADVt (mV lm) as a function of L (lm) between NMOS and
PMOS devices of the 28 nm Gate-First and 20 nm Gate-Last technologies.

2.5
2

Table 5
Effective channel doping in the 20 nm Gate-Last and 28 nm Gate-First technologies.

1.5

W = 1 lm/L = 1 lm
Na NMOS
Na PMOS

20 nm Gate-Last (cm3)
18

1.21  10
1.90  1018

28 nm Gate-First (cm3)
1.98  1017
1.65  1017

0.5
0
0.001

0.01

0.1

W.L (m 2)
Fig. 8. Comparison of Gm/ID (Simens/A) as a function of the transistor surface W  L
(lm2) between GO1 and GO2 for NMOS and PMOS devices of the 20 nm Gate-Last
technology.

Vt mismatch term is more pronounced than the b mismatch term,

dominating the ID mismatch as a function of W  L. Fig. 7b shows
that while Croons model (7) does not t the measured data, the
improved Croon model (8) better reproduces the experimental
trend. This indicates that the Rsd contribution is an important factor
in the ID mismatch across the whole range of W  L. Fig. 7b also
shows that the b mismatch term dominates the ID mismatch across
the whole range of W  L. Similar results were obtained for PMOS
devices.

The presented results show that the improved Croon Model better reproduces the measured ID mismatch for all devices (GO1/GO2
and N/PMOS) and that the Rsd contribution is signicant in GO2,
but negligible in GO1 devices.
The last investigation conducted in this study is focused on the
|Gm/ID| contribution to the Vt mismatch term in (8). This parameter
is plotted in Fig. 8 for the whole range of W  L. The graph shows a
signicant gap between the |Gm/ID| values of GO1 and GO2 devices.
The lower Gm/ID in the case of GO2 is related to the higher VGS value
(1.8 V) adopted with respect to GO1 (VGS = 0.9 V). Moreover, the
trend of |Gm/ID| as a function of W  L is very similar to that observed
for iADID/ID in Fig. 6. This suggests that, while the Vt and b mismatch
are considerably degraded in GO2 devices as compared to GO1
devices, the ID mismatch measurements on the two devices exhibit
less difference due to the Rsd contribution and the |Gm/ID| gap.

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.006

L. Rahhal et al. / Solid-State Electronics xxx (2015) xxxxxx

iA / (%.m)

2.5

4.1. Threshold voltage variability

PMOS 20 nm Gate last

PMOS 28nm Gate first
NMOS 20 nm Gate last
NMOS 28nm Gate first

2
1.5
1
0.5
0
0.01

0.1

L (m)
Fig. 11. Comparison of iADb/b (% lm) as a function of L (lm) between NMOS and
PMOS devices of the 28 nm Gate-First and 20 nm Gate-Last technologies.

4. Comparison between 28 nm Gate-First and 20 nm Gate-Last

Bulk technologies
After demonstrating that MGG can be effectively suppressed in
the 20 nm Gate-Last technology, a comparison between this
technology and the previous 28 nm Gate-First technology is proposed. Note that, for both technologies, this study considers GO1
devices with pocket implants and thin, yet different oxide
thicknesses.

The Vt values were rst measured using the maximum slope

method [19] for 20 nm Gate-Last and 28 Gate-First GO1 devices.
The results are plotted in Fig. 9 as a function of the gate length
(L), showing that N/PMOS devices of the 28 nm technology exhibit
reverse short channel effects on the whole range of L, while 20 nm
Gate-Last devices are affected by smaller Vt variations as a function
of L and less signicant short channel effects for L < 0.06 lm. Note
that both 20 nm and 28 nm technologies present pocket implants
in the channel. Also note that a width effect is observed for
28 nm NMOS Gate-First technology. Indeed for the same gate
length, when W is increased Vt is decreased. For example in
Fig. 9, for L = 0.0.3 lm, when W values are decreasing from
10 lm to 0.08 lm, the corresponding Vt values are increasing from
0.34 V to 0.55 V.
The individual Vt mismatch parameter is thus calculated from
the Vt values for 20 nm and 28 nm technologies and plotted in
Fig. 10 as a function of L (lm). For nominal devices, very promising
iADVt values of 1.79 mV lm and 1.3 mV lm are observed for N and
P MOS devices respectively. Furthermore, Fig. 10 shows that, for
short devices where the pockets are close one to another, 20 nm
Gate-Last devices presents improved iADVt values as compared to
28 nm Gate-First devices for both N and P MOS transistors.
As for long devices, the 20 nm technology shows smaller hump
at L = 1 lm. Note that the improvement of iADVt over the whole
range of L is more pronounced for PMOS devices. For long devices,
the effective channel doping (Na) was extracted for W = 1 lm/
L = 1 lm using (3) and (4), where Vt was obtained for bulk bias values as shown in Table 3. The extracted values of Na are detailed in
Table 5.

iA Vt (mV.m)

C090 (Poly,CoSi2)

NMOS

7
6

C065 (Poly,CoSi2)

5
C045 (Poly,SiON)

4
3

C028 Gate-First
(HFSION,TiN/AO)

(a)

1
0

20

40

C020 Gate-Last
(TiN/TaN,SiON/HfO2)
60

Tox (A)
7

C090 (Poly,CoSi2)

iA Vt (mV.m)

PMOS

C065 (Poly,CoSi2)

C045 (Poly,SiON)

3
C028 Gate-First (HFSION,
TiN/AO/TiN/Al/TiN)

(b)

1
0

20

40

C020 Gate-Last
(TiN/TaN,SiON/HfO2)
60

Tox (A)
Fig. 12. Trend of iADVt (mV lm) as a function of the oxide thickness Tox () from 90 nm ST Bulk technology to 20 nm Gate-Last Bulk technology (a) for NMOS devices and (b)
for PMOS devices.

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1.6

C090 (Poly,CoSi2)

NMOS

1.4
1.2

iA / (%.m)

C065 (Poly,CoSi2)

1
C045 (Poly,SiON)

0.8
0.6

C028 Gate-First
(HFSION,TiN/AO)

0.4

C020 Gate-Last
(TiN/TaN,SiON/HfO2)

(a)

0.2
0
0

20

40

60

Tox (A)

1.6

iA / (%.m)

1.4

C090 (Poly,CoSi2)

PMOS

1.2

C065 (Poly,CoSi2)

1
C045 (Poly,SiON)

0.8
0.6

C028 Gate-First (HFSION,

TiN/AO/TiN/Al/TiN)

0.4

C020 Gate-Last
(TiN/TaN,SiON/HfO2)

(b)

0.2
0

20

40

60

Tox (A)
Fig. 13. Trend of iADb/b (% lm) as a function of the oxide thickness Tox () from 90 nm ST Bulk technology to 20 nm Gate-Last Bulk technology (a) for NMOS devices and (b) for
PMOS devices.

Mezzomo et al. demonstrated that higher levels of pocket doping induce mismatch degradation in both short and long transistors, and that long transistors are additionally affected by larger
Vt mismatch as the contrast between the doping level in the pockets and in the rest of the channel increases [18]. With regard to the
mismatch data, this suggests that the pocket implants in 20 nm
Gate-First devices are less doped compared to 28 nm Gate-Last
devices. As for long devices, Table 4 shows that Na is higher in
20 nm Gate-Last devices compared to 28 nm Gate-First devices,
suggesting that the contrast between the pockets and the rest of
the channel is less pronounced in the 20 nm node than in the
28 nm node. The combined contrast of pockets and channel doping
induces the observed improvement in Vt mismatch and the smaller
hump for lengths approaching L = 1 lm.
4.2. Current gain factor variability
The current gain factor (b) was also extracted using the maximum slope method [19]. The b individual constant of mismatch
was then calculated using (2) for each transistor geometry and
the results are plotted in Fig. 11. This graph shows that the
20 nm technology exhibits signicant improvement and less dispersion of the b mismatch values as compared to 28 nm technology for both N and P MOS devices.
5. Vt and b mismatch trends as a function of Tox
The benchmark plot of Fig. 12 illustrates the trend of iADVt for
NMOS and PMOS transistors from the 90 nm ST node down to
the 20 nm Gate-Last ISDA node, as a function of Tox (EOT). The

graph shows that the linear trends of iADVt for older technologies
until the 45 nm Poly-Gate node have a non-zero offset (y-axis
intercept). Asenov et al. showed that such offset is directly related
to the material-Gate contribution, which does not scale with Tox
and approaches zero starting from the 28 nm Metal Gate technology [23]. This suggests that the gate mismatch contribution is negligible compared to the channel contribution. This phenomenon is
more pronounced in the 20 nm Gate-Last technology, exhibiting
large iADVt improvement for thin Tox. The Gate-Last technology
therefore enables a reduction of the MGG contribution to the Vt
mismatch, and the gap between 28 nm Gate First and 20 nm
Gate-Last technologies is of 0.5 mV lm corresponding to iADVt values of 2.4 mV lm for 28 nm Gate-First and to 1.9 mV lm for 20 nm
Gate-Last. Note that the values of iADVt were calculated using Pelgroms law, where iADVt is constant for varying L. The same conclusions were also drawn for PMOS devices from Fig. 12b, which
indicates a higher gap of 0.9 mV lm between the 28 nm Gate-First
and the 20 nm Gate-Last technologies.
Similarly, for the b mismatch the values of iADb/b were calculated using Pelgroms law, since iADVt is a constant versus L. The
iADb/b parameter for NMOS transistors was plotted as a function
of Tox (EOT) for the nodes from 90 nm ST bulk technology to the
20 nm Gate-Last ISDA node. The corresponding graph shown in
Fig. 13a does not indicate any specic variation as a function of
Tox or technology-dependent trend. Note that GO1 devices
(NMOS/PMOS) of the 20 nm Gate-Last technology exhibit
improved b mismatch as a function of Tox. However, for thick Tox,
the b mismatch value is comparable to the older ST technologies.
The same conclusions were also drawn for PMOS devices from
Fig. 13b. In this case, however, the values of iADb/b for the 20 nm

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
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Gate Last-technology are comparable to those measured for the

other technologies and do not exhibit signicant improvement.
6. Summary and conclusions
This paper reports a study on the Vt, b, and ID mismatch trends
in 20 nm Gate-Last bulk technology and presents a comparison
with the previous 28 nm Gate-First bulk technology. The results
obtained from the comparison between GO1 and GO2 devices of
the 20 nm Gate-Last technology reveal superior Vt and b mismatch
performance in thinner gate oxide (GO1) devices due to the larger
gate coupling. As for the ID mismatch, similar results were
observed in GO1 and GO2, N/PMOS devices. The similarity was
explained by tting the experimental data with the improved
Croon model [22], which is able to reproduce the measurements
and proves that the observed trend is a direct consequence of the
Rsd and |Gm/ID| contributions.
With regard to the channel depletion charge (Qd) mismatch,
GO1 and GO2 devices exhibit identical iADQd values. This similarity
suggests that the Vt mismatch scales with Tox and that the channel
contribution to the Vt mismatch is more prominent than the gate
contribution. By introducing improvements in the MGG effect,
the Gate-Last technology allows suppressing the gate contribution
to the Vt mismatch. Furthermore, the presented comparison
between the 20 nm Gate-First and 28 nm Gate-Last technologies
shows that the former benets from improved Vt and b mismatch
performance.
Finally, the trends of Vt and b mismatch as a function of Tox were
plotted for the nodes from 90 nm ST technology to 20 nm Gate-Last
ISDA technology. iADb/b does not exhibit any specic trend, neither
as a function of Tox nor over the different technologies. iADVt shows a
linear trend as a function of Tox with an offset greater than zero for
all nodes until the 45 nm Poly-Gate technology. Such offset
approaches zero when moving from the 28 nm Metal Gate technology to the 20 nm Gate-Last technology, conrming that the MGG
induced mismatch is negligible. This also conrms that, for 28 nm
Metal Gate technology and 20 nm Gate-Last technology, the principal contributor to Vt mismatch remains the channel doping.
Acknowledgements
The authors would like to acknowledge and thank the ISDA alliance team for the use of their 20 nm process wafers and the data
used in this paper.

[2] Keyes RW. The effect of randomness in the distribution of impurity atoms on
FET thresholds. Appl Phys A: Mater Sci Process 1975;8(3):2519.
[3] Shyu J-B, Temes C, Krummenacher F. Random error effects in matched MOS
capacitors and current sources. IEEE J Solid-State Circ 1984;SSC-19(6):94855.
[4] Lakshmikumar KR, Hadaway RA, Copeland MA. Characterization and modeling
of mismatch in MOS transistors for precision analog design. IEEE J Solid-State
Circ 1986;SSC-21(6):105766.
[5] Pelgrom MJM, Duinmaijer ACJ, Welbers APG. Matching properties of MOS
transistors. IEEE J Solid-State Circ 1989;24(5):14339.
[6] Roy G et al. Simulation study of individual and combined sources of intrinsic
parameter uctuations in conventional nano-MOSFETs. Trans Electron Dev
2006;53(12):306370.
[7] Cathignol A et al. Quantitative evaluation of statistical variability sources in a
45 nm technological node LP N-MOSFET. IEEE Electron Dev Lett
2008;29(6):60911.
[8] Asenov A et al. Origin of the asymmetry in the magnitude of the statistical
variability of n- and p-channel poly-Si gate bulk MOSFETs. IEEE Electron Dev
Lett 2008;29(8):9135.
[9] Wang Xingsheng. Simulation study of dominant statistical variability sources
in 32-nm high-k/metal gate CMOS. Electron Dev Lett, EEE 2012;33(5):6435.
[10] Bai WP et al. Three layer laminated metal gate electrodes with tunable work
functions for CMOS applications. IEEE Electron Dev Lett 2005;26(4):2313.
[11] Fillot F et al. Investigations of titanium nitride as metal gate material,
elaborated by metal organic atomic layer deposition using TDMAT and NH3.
Microelectron Eng 2005;82(3/4):24853.
[12] Mistry K, et al. A 45 nm logic technology with high-k + metal gate transistors,
strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pbfree packaging. In: Electron devices meeting IEDM tech dig.; 2007. p. 24750.
[13] Ohmori K, et al. Impact of additional factors in threshold voltage variability of
metal/high-k gate stacks and its reduction by controlling crystalline structure
and grain size in the metal gates. In: Electron devices meeting IEDM tech. dig.;
2008. p. 40912.
[14] Asenov, et al. Metal-gate-rst FD-SOI will be very good but metal-gate last
could be spectacular, GSS news. <http://www.goldstandardsimulations.com/
index.php/news/blog_search/fd-soi/>.
[15] Fukutome, et al. Comprehensive extensibility of 20 nm low power/high
performance technology platform featuring scalable high-k/metal gate
planar transistors with reduced design corner. In: Electron devices meeting
(IEDM); 2012. p. 3.5.1.4.
[16] Croon J et al. IEEE Solid State Circ 2002;37(8).
[17] Rochereau K, et al. Impact of pocket implant on MOSFET mismatch for
advanced CMOS technology. In: IEEE international conference on
microelectronics test structures (ICMTS); 2004. p. 12326.
[18] Mezzomo C et al. Modeling local electrical uctuations in 45 nm heavily
pocket-implanted bulk MOSFET. Solid-State Electron 2010;54(11):135966.
[19] Hao C et al. Experimental determination of short channel MOSFET parameters.
Solid State Electron 1985;28:102530.
[20] Ghibaudo G. Critical MOSFETs operation for low voltage/low power ICs: ideal
characteristics, parameter extraction, electrical noise and RTS uctuations.
Microelectron Eng 1997;39:3157.
[21] Croon J et al. An easy to use mismatch model for MOS transistor. IEEE J Solid
State Circ 2002;37(8).
[22] Rahhal L, et al. New methodology for drain current local variability
characterization using Y function method. In: IEEE international conference
on microelectronics test structures (ICMTS); 2013. p. 99103.
[23] Asenov A et al. Polysilicon gate enhancement of the random dopant induced
threshold voltage Fluctuations in sub-100 nm MOSFETs with ultrathin gate
oxide. IEEE Trans Electron Dev (TED) 2000;47(4):80512.

References
[1] Hoeneisen B, Mead CA. Currentvoltage characteristics of small size MOS
transistors. IEEE Trans Electron Dev 1972;ED-19(3):3823.

Please cite this article in press as: Rahhal L et al. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies.
Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.006