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EEE588

Digital IC Design

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Version No. 2.00


Prerequisite: Objectives:
This course is preparatory for study in the field of Very Large Scale Integrated (VLSI) digital circuits
and engineering practice. The course focuses upon the systematic analysis and design of basic digital
integrated circuits in CMOS technology. Problem solving and creative circuit design techniques are
emphasized throughout. This course provides the foundation for subsequent courses in the design
of digital integrated circuits and systems. Basic principles, methodologies, and ad-hoc analysis and
design techniques are emphasized.
Expected Outcome:
After completion of this course the students will be familiar with modern VLSI circuits and will be
able to design most of them.
Unit I
Introduction
Issues in Digital IC Design. Quality Metrics of a Digital Design. MOS Transistor. Manufacturing
CMOS Integrated Circuits. Design Rules. Layouts.
Unit II
The CMOS inverter:
Static CMOS Inverter: Static and Dynamic Behavior Practices of CMOS Inverter. Components of
Energy and Power: Switching, Short-Circuit and Leakage Components. Technology scaling and its
impact on the inverter metrics.
Unit III
CMOS Combinational Logic Circuit Design:
Static CMOS Design: Complementary CMOS, Ratioed Logic, Pass Transistor Logic. Dynamic
CMOS Design: Dynamic Logic Design Considerations. Speed and Power Dissipation of Dynamic
logic, Signal integrity issues, Cascading Dynamic gates.
Unit IV
CMOS Sequential Logic Circuit Design
Introduction. Static Latches and Registers. Dynamic Latches and Registers. Pulse Based Registers.
Sense Amplifier based registers. Latch vs. Register- based pipelines structures.
Unit V
Interconnect and Timing Issues
Interconnects: Resistive, Capacitive and Inductive Parasitics. Computation of R, L and C for given
inter-connects. Buffer Chains.
Timing Issues: Timing classification of digital systems. Synchronous Design - Origins of Clock
Skew/Jitter and Impact on Performance. Clock Distribution Techniques. Latch based clocking.
Synchronizers and Arbiters. Clock Synthesis and Synchronization using a Phase-Locked Loop
Textbooks :
1. Jan M. Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design
Perspective, (2/e), PHI 2005.
2. Neil..H..E..Weste, David Harris, Ayan Banerjee, CMOS VLSI Design: A Circuit and Systems
Perspective, (3/e). Pearson Education. 2006.
Reference Books
1. David A Hodges, Horace G Jackson and Resve A Saleh, Analysis and Design of Digital
Integrated Circuits in Deep Submicron Technology TMH.2005.
2. Sung-Mo Kang, Yusuf Leblebicii, CMOS Digital Integrated Circuits- Analysis and Design
McGraw-Hill International Edition.
Mode of Evaluation:

CAT- I & II, Assignments/ Quiz, Term End Examination.

Proceedings of the 29th Academic Council [26.4.2013]

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Digital IC Design Lab


Expected Outcome:
At the completion of the design project, students should be able to:
1. Understand how transistor behaves as a device and describe transistor operations in digital
domain.
2. Design an interface circuitry for different IC technologies.
3. Understand and apply low-power high-performance design techniques in their design.
4. Do a layout of a small IC block, including the routing.
5. Understand and apply advanced layout techniques to minimize the effects of parasitics,
especially on high-speed circuitries.
List of Experiments
1. Introduction to Cadence environment; setup Linux environment; create schematic and
symbol, introduction to netlist, technology library and other stuff
2. DC and transient analysis of CMOS inverter
3. Layout, DRC, LVS, RCX and post-layout simulation of CMOS Inverter
4. Design and Analysis of NAND, NOR and complex gates
5. Layout of CMOS NAND, NOR and complex gates
6. Design and characterization of Latches and Flip-flops
7. Design of Memory cells
8. Design of I/O PADs
9. Modeling of interconnects
10. Mini-project
Mode of Evaluation:

Continuous Assignments/ Quiz/ Project work, Term End


Examination.

Proceedings of the 29th Academic Council [26.4.2013]

248