Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad

CAD OF ELECTRONICS LAB (EEC-751)
EEC 751 CAD OF ELECTRONICS LAB
PSPICE Experiments
1. Transient Analysis of BJT inverter using step input.
2. DC Analysis (VTC) of BJT inverter with and without parameters.
3. Transient Analysis of NMOS inverter using step input.
4. Transient Analysis of NMOS inverter using pulse input.
5. DC Analysis (VTC) of NMOS inverter with and without parameters.
6. Analysis of CMOS inverter using step input.
7. Transient Analysis of CMOS inverter using step input with parameters.
8. Transient Analysis of CMOS inverter using pulse input.
9. Transient Analysis of CMOS inverter using pulse input with parameters.
10. DC Analysis (VTC) of CMOS inverter with and without parameters.
11. Transient & DC Analysis of NOR Gate inverter.
12. Transient & DC Analysis of NAND Gate

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
Experiment No:1
Aim: Transient analysis of BJT inverter using Step input
Software Used: PSPICE
Theory:
1. Ideal Inverter Digital Gate
The ideal Inverter model is important because it gives a metric by which we can judge the quality of
actual implementation. Its VTC is shown in figure 1.1 and has the following properties:
Infinite gain in the transition region, and gate threshold located in the middle of the logic swing, with
high and low margins equal to the half of the swing. The input and output impedance of the ideal gate
are infinity and zero, respectively.

2. Dynamic Behavior of Inverter Digital Gate

Figure1.2 illustrates the behavior of the inverter digital gate using BJT

There are three regions for the above voltage transfer characteristic
1. Cut-off region.
2. Forward Active region.
3. Saturation region.
BJT Inverter can be best expressed by its voltage transfer characteristic (VTC) or DC transfer
characteristic as shown in figure 1.3. That relates the output voltage to the input one.
If:
Vi = Vol, Vo = Voh = Vcc (VTC) or DC Transfer Characteristic The transistor is OFF.

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
Vi = Vil
The transistor Begins to turn on.
Vil < Vi < Vih. The transistor is in forward active region and operates as Amplifier.

Vi = Voh .The transistor will be deep is saturation, Vo = Vce(sat).

A measure of sensitivity to noise is called Noise Margin (NM) which can be expressed by:
Nml = Vil Vol.
Nmh = Voh Vih.
Schematics:

Simulation waveforms:

Result: The transient analysis of BJT inverter using step unit in PSPICE has been successfully done and
the waveforms were plotted successfully. The waveforms tally with the expected behavior of the BJT
inverter.

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
Experiment No:8
Aim: Transient analysis of CMOS inverter using pulse input
Software Used: PSPICE
Theory:
Figure below shows the circuit diagram of a static CMOS inverter. Its operation is readily understood
with the aid of the simple switch model of the MOS transistor, the transistor is nothing more than a switch
with an infinite off resistance (for |VGS| < |VT|), and a finite on-resistance (for |VGS| > |VT|).

Fig 3.1: Static CMOS inverter. VDD stands for the supply voltage.
This leads to the following interpretation of the inverter. When Vin is high and equal to VDD, the NMOS
transistor is on, while the PMOS is off. This yields the equivalent circuit of Figure 3.2. A direct path
exists between Vout and the ground node, resulting in a steady-state value of 0V. On the other hand, when
the input voltage is low (0 V), NMOS and PMOS transistors are off and on, respectively. The equivalent
circuit of Figure 5.2b shows that a path exists between VDD and Vout, yielding a high output voltage. The
gate clearly functions as an inverter.

Fig 3.2 Switch models of CMOS inverter.

The nature and the form of the voltage-transfer characteristic (VTC) can be graphically deduced by
superimposing the current characteristics of the NMOS and the PMOS devices. Such a graphical
construction is traditionally called a load-line plot. It requires that the I-V curves of the NMOS and
PMOS devices are transformed onto a common coordinate set. We have selected the input voltage Vin, the
output voltage Vout and the NMOS drain current IDN as the variables of choice. The PMOS I-V relations
can be translated into this variable space by the following relations (the subscripts n and p denote the
NMOS and PMOS devices, respectively):

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
IDSp = IDSn
VGSn = Vin ; VGSp = Vin VDD
VDSn = Vout ; VDSp = Vout VDD
The load-line curves of the PMOS device are obtained by a mirroring around the xaxis and a horizontal
shift over VDD. This procedure is outlined in Figure 5.3, where the subsequent steps to adjust the original
PMOS I-V curves to the common coordinate set Vin,Vout and IDn are illustrated.

Figure 3.3 Transforming PMOS I-V characteristic to a common coordinate set (assuming VDD = 2.5 V).

Figure 3.4 Load curves for NMOS and PMOS transistors of the static CMOS inverter (VDD =
2.5 V). The dots represent the dc operation points for various input voltages.
The resulting load lines are plotted in Figure 3.4. For a dc operating points to be valid, the currents
through the NMOS and PMOS devices must be equal. Graphically, this means that the dc points must be
located at the intersection of corresponding load lines. A number of those points (for Vin = 0, 0.5, 1, 1.5,
2, and 2.5 V) are marked on the graph. As can be observed, all operating points are located either at the
high or low output levels. The VTC of the inverter hence exhibits a very narrow transition zone. This
results from the high gain during the switching transient, when both NMOS and PMOS are
simultaneously on, and in saturation. In that operation region, a small change in the input voltage results
in a large output variation. All these observations translate into the VTC of Figure 3.5.

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)

Figure 3.5 VTC of static CMOS inverter, derived from Figure 5.4 (VDD = 2.5 V). For each operation
region, the modes of the transistors are annotated off, res(istive), or sat(urated).
Schematics:
VCC

XSC1

3.3V
Q3

Ext Trig
+
_
B

V1
0 V 3.3 V
6usec 12usec
Vi

0.5u
1.25u
Q1

Vo
C1
500fF

0.5u
1.25u

Fig 3.6: CMOS inverter with pulse input schematic circuit

Simulation waveforms:

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)

Result: The transient analysis of CMOS inverter using pulse input in PSPICE has been successfully done
and the waveforms were plotted successfully. The waveforms tally with the expected behavior of the
CMOS inverter.

Experiment No:6

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
Aim: Transient analysis of CMOS inverter using step input
Software Used: PSPICE
Theory:
Figure below shows the circuit diagram of a static CMOS inverter. Its operation is readily understood
with the aid of the simple switch model of the MOS transistor, the transistor is nothing more than a switch
with an infinite off resistance (for |VGS| < |VT|), and a finite on-resistance (for |VGS| > |VT|).

Fig 3.1: Static CMOS inverter. VDD stands for the supply voltage.
This leads to the following interpretation of the inverter. When Vin is high and equal to VDD, the NMOS
transistor is on, while the PMOS is off. This yields the equivalent circuit of Figure 3.2. A direct path
exists between Vout and the ground node, resulting in a steady-state value of 0V. On the other hand, when
the input voltage is low (0 V), NMOS and PMOS transistors are off and on, respectively. The equivalent
circuit of Figure 5.2b shows that a path exists between VDD and Vout, yielding a high output voltage. The
gate clearly functions as an inverter.

Fig 3.2 Switch models of CMOS inverter.

The nature and the form of the voltage-transfer characteristic (VTC) can be graphically deduced by
superimposing the current characteristics of the NMOS and the PMOS devices. Such a graphical
construction is traditionally called a load-line plot. It requires that the I-V curves of the NMOS and
PMOS devices are transformed onto a common coordinate set. We have selected the input voltage Vin, the
output voltage Vout and the NMOS drain current IDN as the variables of choice. The PMOS I-V relations
can be translated into this variable space by the following relations (the subscripts n and p denote the
NMOS and PMOS devices, respectively):

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
IDS p = IDS n
VGS n = Vin ; VGS p = Vin VDD
VDS n = Vout ; VDS p = Vout VDD
The load-line curves of the PMOS device are obtained by a mirroring around the xaxis and a horizontal
shift over VDD. This procedure is outlined in Figure 5.3, where the subsequent steps to adjust the original
PMOS I-V curves to the common coordinate set Vin,Vout and IDn are illustrated.

Figure 3.3 Transforming PMOS I-V characteristic to a common coordinate set (assuming VDD = 2.5 V).

Figure 3.4 Load curves for NMOS and PMOS transistors of the static CMOS inverter (VDD =
2.5 V). The dots represent the dc operation points for various input voltages.
The resulting load lines are plotted in Figure 3.4. For a dc operating points to be valid, the currents
through the NMOS and PMOS devices must be equal. Graphically, this means that the dc points must be
located at the intersection of corresponding load lines. A number of those points (for Vin = 0, 0.5, 1, 1.5,
2, and 2.5 V) are marked on the graph. As can be observed, all operating points are located either at the
high or low output levels. The VTC of the inverter hence exhibits a very narrow transition zone. This
results from the high gain during the switching transient, when both NMOS and PMOS are
simultaneously on, and in saturation. In that operation region, a small change in the input voltage results
in a large output variation. All these observations translate into the VTC of Figure 3.5.

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)

Figure 3.5 VTC of static CMOS inverter, derived from Figure 5.4 (VDD = 2.5 V). For each operation
region, the modes of the transistors are annotated off, res(istive), or sat(urated).
Schematics:
VCC

XSC1

3.3V
Q3

Ext Trig
+
_
B

V2

0.5u
1.25u

5nsec

Q1

Vo
C1
500fF

0.5u
1.25u

Fig 3.7: CMOS inverter with step input schematic circuit

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
Simulation waveforms:

Result: The transient analysis of CMOS inverter using step input in PSPICE has been successfully done
and the waveforms were plotted successfully. The waveforms tally with the expected behavior of the
CMOS inverter.

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)
CMOS NAND Gate:
Figure 10.2 shows a two input CMOS NAND gate, output pull-up is provided by
two PMOS in parallel connections, while two NMOS with series connection
provide an output pull-down to ground.

Output High State:

This state is obtained by two cases:
If both inputs are low, the two PMOS are in active operation providing an output pull-up to
VDD, while the two NMOS are off, so ID,PA = ID,PB = 0, and VDS,PA = VDS,PB = 0.
With a single input low, an output pull up path to VDD is exist through the corresponding
PMOS, with the corresponding NMOS is off and no current is pass through NMOS .
In each case: VOH = VDD.
Output Low State:
This state is obtained only if the two inputs are high as follow, if A and B inputs are high, NA and NB
are in active operation , while PA and PB are off, so no output pull up path to VDD is available and
the currents ID,NA = ID,NB = 0, and VOL = 0.

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)

CMOS NOR Gate:

Figure 10.3 shows a two input CMOS NOR Gate, the NOR function can be
obtained with CMOS pairs; PMOS devices in series to provide pull-up
configuration and NMOS devices in parallel to provide pull-down configuration.

Output Low State:

The output low can be obtained by two cases:
If bothe input are high, the gate to source voltage for both NMOS brings them into active
operation providing an active pull-down to ground, while PMOS's are off.
If any input in high the corresponding NMOS is in active operation to provide an output pulldown to ground.
In each cases:
VOL = 0.
Output High State:
This state can be occurred only if the two inputs are low, where both NA and NB are off, while the
PMOS devices are in active operation to provide an output pull-up to VDD.
VOH = VDD.

Procedure:
Part 1:
1. Construct the circuit shown in Figure 10.1, VDD = 5V
2. Find the truth table filling the following

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)

3. Filling the following table and Draw the VTC of this gate :

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad .

Department of Electronics & Communication Engineering

SET, IFTM University, Moradabad
CAD OF ELECTRONICS LAB (EEC-751)