296

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

Development of Power Interface With FPGA-Based

Adaptive Control for PEM-FC System
Alben Cardenas, Member, IEEE, Kodjo Agbossou, Senior Member, IEEE, and Nilson Henao, Student Member, IEEE

AbstractThis paper presents the development of a power interface for a fuel cell (FC) system supplying an ac load. The proposed system comprises a two stages conditioning system, including a switched capacitor dcdc boost converter and a full bridge
insulated-gate bipolar transistor (IGBT) single-phase inverter
(dcac converter). A fully digital control structure is proposed to
manage both power converters using the same control device. The
control strategy takes advantage of the parallelism of the field programmable gate arrays (FPGA) technology to share in real-time the
controllers information addressing the common problem of lowfrequency ripple of FC current when supplying ac loads. The control system has been implemented and evaluated by co-simulation,
and by experimentation with a proton exchange membrane fuel
cell (PEM-FC) system. The results show that the proposed system
allows a safe operation of the FC by limiting the current ripple
under 3%. These results also confirm that the transient response
of the conversion system permits to correctly supply the ac load.
Index TermsCurrent ripple, energy conversion, fuel cells
(FCs), neural networks, power electronics, programmable logic
arrays.

I. INTRODUCTION
UEL CELLS (FCs) are nowadays proposed as clean energy sources for stationary and mobile power applications.
Commonly stationary applications of FC are stand-alone and
grid-tied power systems [1], [2]. Power conditioning systems
(PCSs) are employed to interface FC voltage with ac loads. The
PCS includes a dcdc boost converter to adapt the FC dc output
voltage, which is normally below 50 V, to a higher dc voltage,
and a dcac converter in order to produce the ac voltage to
supply the load.
Low-frequency current ripple is a commonly related problem
in the literature, which appears when FC systems are employed
to supply ac loads. Several studies have proven that the current ripple affects the FC life duration, as well as the available
output power and its efficiency [3][6]. Those studies on one
hand reveal that an energy-efficient operation of an FC system
imposes that the current ripple must be limited to 20%. On the

Manuscript received February 3, 2014; revised May 30, 2014 and August
11, 2014; accepted August 13, 2014. Date of publication September 4, 2014;
date of current version February 16, 2015. This work was supported in part

by the Laboratoire des Technologies de lEnergie

LTE-Hydro-Quebec, the
Bureau de lefficacite et de linnovation e nergetiques du Quebec, and the
Natural Science and Engineering Research Council of Canada. Paper no. TEC00075-2014.
The authors are with the Departement de Genie e lectrique et Genie Informatique, Hydrogen Research Institute, University of Quebec at TroisRivieres (UQTR), Trois-Rivieres, QC G9A 5H7, Canada (e-mail: Alben.
cardenasgonzalez@uqtr.ca; kodjo.agbossou@uqtr.ca; Nilson.Henao@uqtr.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TEC.2014.2349653

other hand, in order to reduce the impact of the current ripple

on the FC conditions, the ripple must be controlled below 4%.
Current ripple can be reduced by adding intermediary storage systems including capacitors, ultra capacitors or batteries.
However, this option increases the overall cost of the PCS. Alternatively, design strategies of voltage and current feedback loops
and power electronics circuitry have been proposed to reduce
the low-frequency ripple of FC current [7][14]. It is to remark,
that most of the strategies, proposed to reduce the current ripple,
have been only analyzed on steady-state operation.
Recently, progress in very large scale integration (VLSI) technologies have permitted the introduction of field programmable
gate arrays (FPGAs) as new target devices for a wide variety of
applications, including signal processing, information technology, telecommunication, and control. FPGAs are semiconductor
devices with high density of programmable resources, including memory and logic operators, arranged as configurable logic
blocks (CLBs), which can be reconfigured allowing the parallel
processing of different functions. The FPGA is considered a
promising technology in control and signal processing applications [15][18], mainly because it permits the implementation
of several applications inside a single device, allowing multithreats and multicore processing systems, eliminating the realtime communication constraints of multiple processors control
systems.
This paper presents the development and control of a power
electronics interface for an FC power source supplying an ac
load; the developed system includes the power electronics circuits and the FPGA implementation of the control algorithms
for the PCS. The proposed control algorithms, embedded in
one FPGA device, offer good transient response and a significant reduction of the FC current ripple. Hardware-in-the-loop
(HIL) co-simulation and experimental results are provided to
corroborate the validity of the proposed system.
This paper is organized as follows. Section II presents the
developed power electronics system. Section III describes the
proposed control algorithms. Sections IV and V present the HIL
co-simulation and the experimental results. Section VI provides
some concluding remarks.
II. POWER ELECTRONICS INTERFACE FOR PROTON EXCHANGE
MEMBRANE FUEL CELL (PEM-FC)
Fig. 1 illustrates blocks diagram of the PCS used to interface a
PEM-FC with an ac load. As previously mentioned, FC systems
present low output voltage, normally up to tens of volts, and the
peak ac voltage of hundreds of volts.
The output voltage of the FC system (Hydrogenics HyPM XR
8 FC power module) used in this study varies between 20 and

0885-8969 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

CARDENAS et al.: DEVELOPMENT OF POWER INTERFACE WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM

Fig. 1.

297

Block diagram of FC interface.

Fig. 3. Discharging time for different discharging power and different V D C H ,

V D C L = 180 V and C H V C = 2650 F.

Fig. 2.

Minimal dcdc gain for different FC voltage.

40 V according to its operational characteristics (output power,

temperature, etc.) [19]. The development of high-gain boost
dcdc converters is essential to integrate green power sources
with low output voltage, like the renewables and FCs, into
the utility grid or to directly supply high-voltage loads
[20][28].
The minimum input voltage Vdc for a the single-phase inverter
can be defined by

VDCL > 2 Vac |cos(R )|

(1)
where Vac is the root-mean-square (rms) ac voltage and R is the
rated phase angle. This relation must be satisfied to maintain the
sinusoidal
current waveform [29]. Normally, Vdc is set higher

than 2 Vac , above 170 V for a 120-V single-phase inverter.

So the minimum gain of the dcdc converter can vary according
to the FC voltage as illustrated in Fig. 2.
The dcdc converters without intermediary storage system
employ a high-voltage capacitor (HVC). This capacitor must be
well chosen to allow enough energy storage to ensure a proper
operation of the inverter. The inverter input voltage is supplied
by this capacitor and must be kept within the low and high
operating limits VDCL and VDCH , respectively. The discharging
time (D ) of the HVC from the high to the low dc voltage limits
VDCH and VDCL can be computed by
 2

2
(1/2)CHVC VDCH
VDCL
(2)
D >
PFC Pac PL
where PFC is the power coming from the FC, Pac is the power
of the ac load, and PL corresponds to the conversion losses. The
difference between the PFC and the Pac + PL corresponds to
the discharging power.
The discharging times computed for different discharging
power, different VDCH values, VDCL = 180 V, and CHVC =
2650 F are plotted in Fig. 3. The results show that, if VDCH
is 195 V and the discharging power is higher than 500 W, the

Fig. 4. Comparison of discharging time for C H V C = 2650 F and C H V C =

6000 F. Different discharging power, different V D C H , and V D C L = 180 V.

dc voltage falls below VDCL within one electric cycle. On the

other hand, if VDCH is 220 V and the discharging power is
the same, the dc voltage falls below VDCL within 2.7 electric
cycles.
A comparison of the discharging times for CHVC = 2650 F
and CHVC = 6000 F is presented in Fig. 4. It is observed that
the discharging times obtained using 2650 F at VDCH = 220 V
are similar to the ones using 6000 F at VDCH = 200 V.
In this study, the PEM-FC is interfaced by means of a highgain, low-ripple dcdc switched capacitor boost converter as
proposed in [20][23] and a developed insulated-gate bipolar transistor (IGBT) inverter as illustrated in Fig. 5. The
main characteristics of the conversion system are presented
in Table I.
The basic operation of the switched capacitor boost converter
(SCBC) has been discussed in detail in [23], where the authors
demonstrate that this converter topology is well adapted when
requiring low input current ripple, low output voltage ripple,
and high voltage gain, as required in our case. The static gain of
the SCBC can be computed using the duty cycle (D) by
G=

2
.
1D

(3)

The control of the dcdc and dcac power electronics converters when the system operates as autonomous power source
must allow a good transient response and a steady-state behavior according to the standards [30]; moreover, as mentioned earlier, the low-frequency ripple of FC current must be controlled
to be below 4%. In particular, the 120-Hz oscillation must be

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Fig. 5.

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

General diagram of the developed power electronics interface for PEM-FC system.

TABLE I
SYSTEM CHARACTERISTICS
Description
PEM-FC
HydrogenicsHyPMXR8
Rated power
DC output voltage
DCDC converter
Type
Working input voltage range
Maximum output voltage
Input capacitor (LVC)
Input inductors (L1 , L2 )
Switched capacitors (SC1, SC2)
Output capacitor (C3)
Filter inductor (L3 )
Filter capacitor (HVC)
Switching frequency
Power switching devices: Ultrafast diode
IGBT
DCAC Converter
Bridge Type
Rated voltage/current
Nominal dc-source voltage
Operating voltage/frequency
Switching frequency
Filter and Line Impedance
Filter inductor (L D 1 + L D 2 )
Filter capacitor (Cf )
Coupling Inductor (Lo)
Line impedance (L, R)

Value

8 kW
2035 V
One-Stage Switched Capacitor Boost
Converter
2035 V
250 V
1000 F
1.4 mH
1000 F
10 F
0.8 mH
2650 F
6 kHz
FFH60UP40S APT75GN120LG

IGBT Power Module (PS21A7A)

600 V/30 A
200 V
120 V/60 Hz
10 kHz
1.6 mH
20 F
1 mH
1.17 H, 17.6 m

In this study, the output power of the FC system is limited to 3 kW.

Line impedance corresponds to load connection cable.

limited. This ripple limitation is necessary to prevent damage or

premature degradation of the FC.
III. PROPOSED VOLTAGE AND CURRENT CONTROL
The control of power electronics interface is divided in two
parts, the first one is the ac voltage control and the second one
is the dc voltage and current control.

Fig. 6. Simplified diagram of the control structure of dcac converter based

on VF-ADALINE with FLL [31].

A. AC Voltage Control
The ac voltage control implemented in this study is based
on the ADALINE&FLL [31]. This control scheme offers good
transient and steady-state behavior and has been previously evaluated with linear and nonlinear loads. A simplified diagram of
the control structure is presented in Fig. 6.
In this voltage control structure, the instantaneous signal error (S ) is computed as the difference between the reference

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299

and the measured signal (4), and compensated by means of a

proportional controller with gain KPac (5)
S (k) = VREF (k) VC (k)

(4)

CS (k) = KPac S (k).

(5)

The error of the orthogonal components of voltage (W 0 and

W 1 ) is compensated by means of a proportional and integral
(PI) controller with gains KPdc and KIdc .
CW 0 (k) = KPdc W 0 (k) + KIdc

k


W 0 ()

(6)

W 1 ().

(7)

=0

CW 1 (k) = KPdc W 1 (k) + KIdc

k

=0

The compensation signal [see (8)] is then the result of the

partial compensations of (5), (6), and (7)

CS (k) +CW 0 (k) sin(2 f k TS )
CT (k) =
(8)
+CW 1 (k) cos(2 f k TS )
where the sines and cosines signals are generated by the VFDDS. The modulating signal VPW M can be obtained from the
reference voltage and the signal compensation using the following:
VPW M (k) = VREF (k) + CT (k).

(9)

Fig. 7. Proposed control structure of dcdc and dcac converters for the ac
voltage control of an FC system.

B. DC Voltage and Current Control

This section focuses on the control stage, which is devoted to
maintain the output voltage of the dcdc converter at a desired
value (input voltage of the inverter) in order to guarantee a
correct operation of whole system, even if the FC voltage and
the load power change.
The voltage control of the dcdc converter can be obtained
by means of two modified PI controllers as illustrated in Fig. 7.
The first one acts as a voltage controller (10), and the second
one as current controller (11). The rms current absorbed by the
ac load Irm s is estimated by means of the VF-ADALINE&FLL,
and it is fed back and used to anticipate the current set point for
the dcdc converter


KIV
IFCR = (VDCR VDCM ) KPV +
+ Irm s Gdc
s

D = (IFCR IFCM ) KPI +

KII
s

(10)
(11)

where Gdc is the actual dc gain of system computed by using

the actual FC and dc-link voltages using
Gdc =

VDCM
.
VFC

(12)

As illustrated in Fig. 7, the feedback variables, like the dclink voltage (Vdc ), the load current (Irm s ), and the FC current
and voltage (IFC , VFC ), are filtered by means of the auxiliary
ADALINE low-pass filter bank (ADALINE-LPF). This filter
bank is synchronized with the ac load frequency by means

of the ADALINE&FLL permitting to eliminate the harmonic

components present on the measured signals and improving the
transient and the steady-state controller behavior. The estimated
signal using the ADALINE-LPF can be represented by
y(k) = W (k)T X(k)

(13)

where X is the input pattern vector considering a number N of

harmonics and defined by

1
sin(2 f k TS )

cos(2 f k TS )

.
(14)
X(k) =

sin(2 N f k TS )
cos(2 N f k TS )
where Ts is the sampling period of the direct digital synthesis
block (DDS); W is the weight vector, which is updated considering the estimation error e(k) and the learning factor using

e(k) X(k) .
W (k + 1) = W (k) +
(15)
N
The mean or dc signal can be the computed by
ydc (k) = W (0, k) X(0, k)

(16)

eliminating the ac components present on the measured signal,

which are directly related with the harmonics of the ac load
current.

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The proposed method, as other proposed techniques, permits

to reduce the ripple of the FC current by subtracting the lowfrequency components of the feedback voltage signal; however,
the accurate load frequency tracking and the harmonics decomposition are special characteristics of the ADALINE-LPF
allowing a much better reduction of the ripple present on the
feedback signals and without negative impact on the dynamic
performance of the controller. In contrast to classic solutions as
using proportional-resonant (PR) controllers or bandpass filters
(BPFs), tuned at a fixed frequency [7], [11], the adaptive property of the method proposed in this study permits to operate
the system at a fixed load frequency or at a variable frequency;
consequently, it can be widely used for a stand-alone microgrid
or connected to the main grid mode.
It is to highlight that classic solutions only consider the 120 Hz
(or 100 Hz) as the component to be attenuated or eliminated.
Some techniques permit to eliminate the 120 Hz component but
generate other harmonic components [13]. Additionally, modern
ac loads may introduce other non-negligible harmonic components which must be also eliminated of the feedback signals.

TABLE II
MAIN CHARACTERISTICS OF MEASUREMENT SYSTEM
Description (Units)
Measurement and Control System
Sample time of measurement system (s)
FPGA clock period (ns)
ADALINE-FLL
Number of analyzed harmonics
DDS sample time T 0 (s)
Number of implemented WVU T 0
WVU T 0 learning factor
FLL gain G F L L
FLL sampling period T F L L (s)
FLL error threshold M I N
FLL sliding window period T S W (ms)

Value

10
10
32
1
3
0.1
3.5
10 s
0.1
20

C. DC Voltage Droop Scheme

As illustrated in Figs. 3 and 4, the HVC discharging and
charging times are mainly dependent on two parameters: the
capacity and the voltage. Hence, if low-capacity and fixed
Vdc are employed, the capacitor voltage regulation can be
largely affected by the load fluctuations if the FC transient response is not fast enough. A dc voltage droop scheme is proposed to improve the transient response of converter without
increasing the capacity of HVC. This voltage droop scheme
can be defined by
VDCR = VDCN + mdc (PNOM Pac )

(17)

where VDCR is the set point of Vdc ; VDCN is the nominal value of
Vdc ; Pac is the measured load ac power; PNOM is the rated power
of the FC (or dcac converter); and mdc is the droop coefficient
(in volts per watt). In the dc-droop scheme, the operating voltage
at the rated power corresponds to the nominal value, and higher
operating voltages are set for operating powers under the rated
power. In other words, if the system is working at very low power
the dc-link voltage is set at its highest value; consequently, if
the power demand increases the dc-link voltage naturally falls
down. Otherwise, when the system is working at its maximum
power the dc-link voltage is set at its lowest value; thus, if the
power demand falls down the dc-link voltage naturally rises.
The controllers gains can be obtained offline from the transfer function of the system by means of the SISO design or
PID tuner graphical user interfaces (GUIs) of MATLAB software (MATLAB-SISOTool or MATLAB-PIDTool); tuning of
PI controller can be also obtained online by automatic tuning
techniques [32].
IV. HIL CO-SIMULATION RESULTS
The proposed control system of FC power electronic interface has been implemented and evaluated by HIL co-simulation
using the Xilinx Virtex-5 XC5VLX110T FPGA as target device

Fig. 8. HIL co-simulation results of (a) current and (b) voltage ripple when
the mean FC current is 90 A. Controllers use tuning 1.

[33]. The main characteristics of the measurement system and

the implemented ADALINE-FLL are presented in Table II.
The operation of the FC system has been evaluated for different loading conditions. Fig. 8 shows the plot of FC current and dc-link voltage waveforms when the system supply a
3-kW ac load with 120 V/60 Hz voltage. In order to analyze the
performance of the proposed control structure, the ripple factor
of the FC current is computed by using
=

IRipplerm s
100%
IFCm ean

(18)

where IFCm ean is the mean value of the FC current and

IRipplerm s is the rms value of the FC current ripple. In the
same way, the dc-link voltage ripple factor is also computed.
Two different tunings of the integral gain for the current controller (KI I ) have been used. Using the characteristics presented
in Table III, tuning 1 offers faster response than tuning 2. The
HIL co-simulation results of Fig. 8 are obtained using tuning 1,

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301

TABLE III
SETUP OF CONTROLLERS USED IN THE HIL CO-SIMULATION
Description

Tunning 1

Tunning 2

DC Voltage Controller
DC current controller (K P I , K I I )
DC voltage controller (K P V , K I V )
V d c nominal
Operating V d c (Vm i n Vm a x )
DC voltage droop (m d c )
Controller sample time

0.005, 5
1, 0.01
200 V
170240 V
3.3 mV/W
10 s

0.005, 1
1, 0.01
200 V
170240 V
3.3 mV/W
10 s

1
0.0432, 42.35
250 s
6 kHz

1
0.0432, 42.35
250 s
6 kHz

AC Voltage Controller
Signal error controller (K P a c )
Orthogonal components controller (K P d c , K I d c )
Controller sample time
Switching frequency

Fig. 10.

HIL co-simulation results of current ripple for different ac load power.

TABLE IV
COMPARISON OF FC CURRENT RIPPLE AND CAPACITOR SIZE

Description
Low voltage capacitor (LVC)
Switching capacitors (SC1 +
SC2)
HVC
Rated power (static
converters)
LVC + SC capacitor/power
HVC capacitor/power
Steady-state current ripple

Fig. 9. HIL co-simulation results of (a) current and (b) voltage for different
power of ac load. Controllers use tuning 2.

the ripple factor of FC current and voltage are 2.95% and 2.1%,
respectively.
Fig. 9 shows the results for the transient response of the
FC system using tuning 2; in this test, the inverter is started
at t = 100 ms with an initial ac load of 100 W; also at the
times t = 300 ms, t = 800 ms, and t = 1.3 s, the load power is
increased each time of 500 W. Fig. 9(a) shows the FC current,
and Fig. 9(b) shows the dc-link voltage (at HVC). The effect of
the voltage droop scheme on the dc-link voltage, following the
variations of the output power of the system, is well illustrated in
this figure. These results show a good behavior of the controller.
Fig. 10 shows the results of the ripple factor of the FC current for
different load power and considering the two different tunings
of the integral gain of current controller (KI I ). According to
these results, the ripple factor is always under 3% and meet

References [8], [9]

This study

6600 F

1000 F
2000 F

2200 F
1.20 kW

2650 F
3 kW

5.5 F/W
1.83 F/W
2.0%

1 F/W
0.88 F/W
2.95% (Tuning 1) 2.05%
(Tuning 2)

the recommended ripple limits ( < 4%) to reduce the negative

impact of the inverter load on the FC conditions [7].
As illustrated in Fig. 10, the current ripple can be attenuated
by reducing the speed of the current compensator, which is possible by reducing the gain KI I , as in the tuning 2 case. However,
it is to highlight that the speed of the current compensator must
remain high enough to warrant the safe operation of the system.
Table IV shows a comparison of the results obtained by using
the proposed control structure with the ones obtained in [8] and
[9]. It is appropriate to remark that in this study the sizes of
the LVC and the HVC have been reduced to 18% and 48%,
respectively, compared to the ones used in [8], [9].
In order to provide a better indication of the different available solutions of ripple mitigation, a summary of some recently
published methods with a brief description of achievements and
the characteristics of each one is given in Table V.
V. EXPERIMENTAL RESULTS
The proposed control for an FC system has been evaluated
experimentally using a water-cooled PEM-FC system connected
to the developed PCS (switched capacitor boost converter and
IGBT inverter prototypes) and a measurement system based on
Xilinx Virtex-5 development board [33]. The system supplies
a variable power load represented by a set of commercial light
bulbs. Fig. 11 presents a real view of the implemented SCBC,
and Fig. 12 shows the whole test bench.
A. Static Gain of DCDC Converter
The developed prototype of dcdc converter has been preliminary tested using a dc load in order to verify the steady-state

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IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

TABLE V
SUMMARY OF RECENTLY PROPOSED CURRENT RIPPLE MITIGATION
TECHNIQUES
Year

Technique

Characteristics

2010

Dual-loop dcdc converter control

with BPF [11]

2010

DC-active filter with a center tap

[12].

2013

Waveform control [13].

Experiments show that the technique

permits to reduce the current ripple to
4%. The dcdc converter used in this
study consists of a current fed
pushpull converter with auxiliary
circuit (flyback converter).
With this technique, the ripple current
can be decreased to 20% compared to
the conventional circuit (without
compensation). Experiments show an
input current total harmonic distortion
(THD) over 10%, depending on the
output power.
Experiments show a 100 Hz current
ripple of 11.9% for a dc current of
1.84 A. A 200 Hz current ripple of
8.9% appears. THD of ac voltage is
slightly increased. Ripple of dc-link
voltage (or FC voltage) is not
presented.
The 120 Hz component of input
current is reduced to 0.3%.
Peak-to-peak ripple current is 1.32 A
(3.2% of 14.4 A). DC-link voltage
ripple is 27 V (7.63% of 250 V).

2014

Feed-forward control scheme

[14].

Fig. 12.

Real view of the implemented test bench of FC power system.

Fig. 13. Experimental dcdc static gain of converter prototype operating in

open loop.

Fig. 11.

Real view of the implemented SCBC.

voltage gain (G) for different duty cycle (D). The experimental results of the static gain of the dcdc converter are plotted
in Fig. 13 for the open-loop operation, and in Fig. 14, for the
closed loop. The obtained experimental values are close to those
of the theory obtained by using (3). The experimental gain is
lower than the theoretical value, which can be explained by the
converter losses.
B. Inverter Load Operation
The operation of the FC system has been validated with different ac load conditions. The first test has been carried out by
using optimal tuning of classic PI controllers for the current and
voltage loops obtained by the classic ZieglerNichols rule with

Fig. 14. Experimental results of static gain of the dcdc converter working in
closed loop at two different operation points, V d c = 180 V and V d c = 200 V.

MATLAB-SISOTool. Fig. 15 presents the results of FC and ac

load currents; it is observed that the current ripple is over 4%
even if, in that case, the power is low (Iacrm s = 4.2 A).
The proposed controller, illustrated in Fig. 7, has been also
evaluated for different operating powers; the current ripple has
been computed for each case by postprocessing using MATLAB
software from data collected by means of the user interface
(Windows-MATLAB-Xilinx). Fig. 16 presents a summary of
the experimental results of FC current ripple for different ac
load power corresponding to different mean FC current (limited
to 40 A). It is to remark that the ripple factor remains well
under 4% and near to 2% confirming the results obtained by
co-simulation.

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303

Fig. 15. Experimental results of inverter load operation at low load power
(Ia c rm s = 4.2 A) (classic control with optimal controller tuning using ZieglerNichols rule with MATLAB SISOTool).

Fig. 16. Experimental results of current ripple for different ac load power (the
proposed control scheme using tuning 2).

Fig. 17 provides the plots of the measured voltages (dc link,

FC, and ac load) and currents (dcdc converter, FC, and ac
load), when the mean FC current is 25.6 A (corresponding to a
sinusoidal load current of 7 A rms); in this case, the computed
FC current ripple is 1.85%. The plots of the measured voltages
and currents when the mean FC current is 39.9 A (corresponding
to a sinusoidal load current of 11 A rms) are shown in Fig. 18;
in this case, the computed FC current ripple is 1.99%.
C. Evaluation of the Conversion Efficiency
The efficiency of the power electronics converter has been
experimentally evaluated for different operating powers; the results, plotted in Fig. 19, show a mean efficiency of over 94%.
D. Evaluation of Dynamic Performance
The dynamic performance of the proposed strategy has been
experimentally verified confirming that the transient response
of the voltage controller is kept fast enough to maintain the dclink voltage and to warrant a correct ac load supply. Figs. 20
and 21 show the experimental results applying a transient load
power by switching ON (see Fig. 20) and OFF (see Fig. 21) a
commercial light bulb. The reference of dc-link voltage was intentionally set to 196 V (<< 220 V) considering the low-power
transient used in the test, and as expected, according to Fig. 3, the
dc-link voltage was maintained over 180 V when the transient
load power was introduced. This behavior can be only achieved
if the time response of the voltage controller is fast enough to
start a corrective action within one electric cycle (<17 ms).
A better response of voltage regulation will be obtained if the

Fig. 17. Experimental results of inverter load operation at low load power
(Ia c rm s = 7 A, IF C m e a n = 25.6 A). (a) Voltage waveforms and (b) current
waveforms with the proposed control scheme using tuning 2.

reference of the dc-link voltage is set to 220 V as suggested in

Fig. 4.
As observed in Fig. 20(a), the dc-link voltage regulation is
rapidly achieved (within 20 ms) without any overshoot or oscillation. The voltage is once again set at the working value
with a settling time of 35 ms (considering a 2% of error). As
the commercial light bulbs used in this test present very low
impedance when switched ON, their start-up power demand is
three times higher than their nominal power; this fact permits
to introduce a power transient near to 500 W using a single
150-W lamp.
The results presented in Fig. 21 confirm the transient response
of the proposed voltage controller when the load power falls
down. For the power decreasing case, the dc-link voltage is well
regulated, preventing from undesired overshoots or oscillations;
and similarly to the previous case, the FC current is adjusted
within a short time (<20 ms) following the ac load variations.
In order to evaluate the dynamic response of the proposed
controller face to the variations of the reference voltage, a square
signal of 10 V at 1 Hz has been momentarily applied in a short
period of time to the actual reference voltage. The results of the
dc-link voltage tracking response are presented in Fig. 22(a);
here the reference of dc-link voltage and the mean dc-link
voltage obtained through the ADALINE low-pass filter bank
(ADALINE-LPF) and used as the feedback signal are plotted.
Fig. 22(b) shows the current and the voltage of the FC during
the same time interval.
The results of the step response of the entire conversion system have been used to compute the settling time. This computation has been carried out by means of the MATLAB lsiminfo

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Fig. 18. Experimental results of inverter load operation at low load power
(IF C m e a n = 39.9 A). (a) Voltage waveforms and (b) current waveforms with
the proposed control scheme using tuning 2.

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

Fig. 20. Experimental results of transient response (a) dc-link voltage regulation, and (b) FC current and voltage. Power transient of 150 W by switching
OFF a commercial light bulb.

Fig. 19. Experimental results of converters efficiency (the proposed control

scheme using tuning 2).

function; the obtained result is 96 ms, which corresponds to a

time constant of 24.6 ms (considering a first-order approximation and a tacking error of 2%). In the results, it is important to
remark that the system presents a time constant lower than two
electric cycles.
Also, it must be highlighted that in this study the bandwidth
of the voltage control loop was set to 5 Hz, which permits a
good tracking of the reference voltage; most of literature works
use bandwidths lower than 10 Hz (much lower than 120 Hz) for
the voltage control loop, e.g., the strategy of ripple reduction
proposed in [8] and [9] has been evaluated with a bandwidth of
voltage control loop of 1.2, 2, and 4 Hz, and the best results were
obtained when 1.2 Hz was employed. In this study, a higher
bandwidth is possible due to the use of the ADALINE lowpass filter bank, which permits to reduce the 120 Hz ripple of
the voltage feedback signal without important delay improving

Fig. 21. Experimental results of transient response (a) dc-link voltage regulation, and (b) FC current and voltage. Power transient of +150 W by switching
ON a commercial light bulb.

CARDENAS et al.: DEVELOPMENT OF POWER INTERFACE WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM

305

REFERENCES

Fig. 22. Experimental results of voltage controller response face to steps on

the reference voltage: (a) dc-link voltage response; and (b) FC current and
voltage.

the transient response and mitigating the steady-state ripple of

the FC current.

VI. CONCLUSION
The development of a power interface for an FC system supplying an ac load has been presented. The proposed system
includes a prototype of dcdc and dcac converters, and all the
control is implemented in FPGA. The proposed control includes
the ADALINE&FLL structure implemented in hardware, which
is used to control in parallel both the inverter and the SCBC.
Additionally, a dc voltage droop scheme is adopted to improve
the response of the dcdc converter even with the low size of
the HVC.
The proposed system has been experimentally validated
showing many advantages compared with classic solutions some
of them are the low current ripple, the fast transient response,
and a reduced dc-link capacitor compared to the classic and
recently proposed alternative solutions.
All control blocks have been embedded in a single FPGA
device, working in parallel and sharing in real time the main
variables information. This fact demonstrates the validity and
potential of the proposed system by using modern digital control
systems.

ACKNOWLEDGMENT
The authors would like to thank the Xilinx University Program for the hardware, software, and technical support.

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univ/xupv5-lx110t.htm

Kodjo Agbossou (M98SM01) received the B.S.,

M.S., and Ph.D. degrees in electronic measurements
from the Universite de Nancy I, Nancy, France, in
1987, 1989, and 1992, respectively.
He is currently the Head of the Engineering School, Universite du Quebec a` Trois-Rivi`eres
(UQTR), Trois-Rivi`eres, QC, Canada. He was a Postdoctoral Research Fellow in the Electrical Engineering Department, UQTR (19931994), where he was
a Lecturer (19971998). Since 1998, he has been an
Associate Professor, and since 2004, he has been a
Full Professor in the Electrical and Computer Engineering Department, UQTR.
He was the Head of the Electrical and Computer Engineering Department. He
was also the Director of Graduate Studies in Electrical Engineering. He is the
author or coauthor of more than 180 publications and has 4 patents. His current
research include in the areas of renewable energy, smart grid, integration of
hydrogen production, storage and electrical energy generation system, hybrid
electrical vehicle, control, and measurements. He is a member of the Hydrogen
Research Institute and Research group Group de reserche en e lectronique industrielle (GREI), UQTR.
Dr. Agbossou is a Member of the IEEE Power and Energy Society, the Industry Applications Societies, the Communications Society, and the Industrial
Electronics Society Technical Committee on Renewable Energy Systems. He
was the Chair of the IEEE Section Saint Maurice, QC, Canada. He is a Professional Engineer and joined the Ordre des Ingenieurs du Quebec in 1998.

Alben Cardenas (S09M12) received the B.S.

degree in electronic engineering from the Antonio
Narino University, Villavicencio, Colombia, in 2003,
and the M.S. and PhD. degrees in electrical engineering from the Universite du Quebec a` Trois-Rivi`eres
(UQTR), Trois-Rivi`eres, QC, Canada, in 2008 and
2012, respectively.
He is currently a Researcher at the Hydrogen Research Institute (HRI), and a Lecturer in the Electrical and Computer Engineering Department, UQTR.
His current research interests include renewable energy, distributed generation, power electronics, and very large scale integration
(VLSI) technologies for energy conversion and power quality applications.
Dr. Cardenas is a Member of the Ordre des Ingenieurs du Quebec, and a
Member of the IEEE Power and Energy Society and the IEEE Industrial Electronics Society.

Nilson Henao (S14) received the B.S. degree in

electronics engineering from the Universidad de los
Llanos, Villavicencio, Colombia, in 2010, and the
M.Sc. degree in electrical engineering from the University of Quebec at Trois-Rivieres (UQTR), TroisRivieres, QC, Canada in 2013, where he is currently
working toward the Ph.D. degree with the Department of Electrical and Computer Engineering.
His current research interests include fuel cell control and optimization, and energy management for hybrid electric vehicles. He is currently involved in machine learning techniques for nonintrusive appliance load monitoring (NIALM)
to disaggregate and track device electrical signatures.