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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016

SL.NO

YEAR

2014 T

2014 T

2014 T

2014 T

2014 T

2014 T

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2014 T
2014 T
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2014 J

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2014 J

TITLE
32 Bit32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling
Multiplier With Operands Scheduler.
A parallel radix-sort-based VLSI architecture for nding the rst W
maximum/minimum values.
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter
With Low Adaptation-Delay.
Data encoding techniques for reducing energy consumption in
NOC.
Fully reused VLSI architecture of FM0/Manchester encoding
using SOLS technique for DSRC applications.
Low complexity low latancy architecture for matching of data
encoding with hard systematic error corrections codes
An Optimized Modified Booth Recoder for Efficient Design of the
Add-Multiply Operator.
Area delay power efficient carry select adder.
Fast radix 10 multipliation using redudant BCD codes.
Recursive Approach to the Design of a Parallel Self-Timed Adder.
Analysis and design of low power double tail comparator.
A Novel Modulo 2N-2K-1 Adder for Residue Number System.
Area-Delay Efficient Binary Adders in QCA.
Low-Complexity Multiplier for GF(2m) Based on All-One
Polynomials.
Smart Reliable Network-on-Chip.
Design of Low Power TPG BIST Technique using LP-LFSR
Design and Implementation of Adder for Modulo 2n+1 addition
Implementation and Analysis of High Speed Multipliers A
Vedic Multipliers Approach.
Design of High Speed, Area Efficient, Low Power Vedic
Multiplier using Reversible Logic Gate.
A Low Power Single Phase Clock Distribution Using VLSI
Technology.
Dynamic Multi Resolution Tracer for on Chip Bus with Real Time
Compression.
Design and Estimation of delay, power and area for Parallel
prefix adders.
Design and Implementation of Wishbone Bus Interface
Architecture for SoC Integration USING Verilog

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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016

SL.NO

YEAR

24

2013 T

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26

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2013 J

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2013 J

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2013 J

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2013 J

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45

2013 J

TITLE
A Low-Cost, Systematic Methodology for Soft Error Robustness
of Logic Circuits.
Design of Testable Reversible Sequential Circuits.
Multioperand Redundant Adders on FPGAs.
Reducing the Cost of Implementing Error Correction Codes in
Content Addressable Memories.
Reducing the Cost of Implementing Error Correction Codes in
Content Addressable Memories.
The LUT-SR Family of Uniform Random Number Generators for
FPGA Architectures.
Algorithm and Architecture Design of Bandwidth-Oriented
Motion Estimation for Real-Time Mobile Video Applications.
Error Detection in Majority Logic Decoding of Euclidean
Geometry Low Density Parity Check (EG-LDPC) Codes.
An Efficient Interpolation-Based Chase BCH Decoder.
VLSI Implementation of a Low-Cost High-Quality Image Scaling
Processor.
Pipelined Radix- Feedforward FFT Architectures.
A New VLSI Architecture of Parallel MultiplierAccumulator
Based on Radix-2 Modied Booth Algorithm.
Ultralow-Voltage Process-Variation-Tolerant Schmitt-TriggerBased SRAM Design.
Design and Simulation of ZIGBEE Transmitter Using Verilog.
A High Speed Binary Floating Point Multiplier Using Dadda
Algorithm.
FPGA Implementation of Efficient Hardwarefor the Advanced
Encryption Standard.
Design and Implementation of 32 Bit Unsigned Multiplier Using
CLAA and CSLA.
VLSI Based Robust Router Architecture
Fast Search Algorithm Based Anti-collision Technique For RFID
Passive Tags.
Design of On-Chip Bus with OCP Interface
High Speed and Low Power implementation of 3-Weight Pattern
Generation Based on accumulator.
Design & Implementation Of 32-Bit Risc (MIPS) Processor

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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016

SL.NO

YEAR

46

2013 C

47

2013 C

48

2013 C

49
50
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2013 C
2013 C
2013 C

52

2013 C

53

2012 T

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2012 T

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2012 T

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2012 T

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2012 T
2012 J

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2012 J

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2012 J

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2012 C

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2012 C

66

2011 T

TITLE
VLSI implementation of Fast Addition using Quaternary Signed
Digit Number System.
High Performance and Power Efficient 32-bit Carry Select Adder
using Hybrid PTL/CMOS Logic Style.
An FPGA Based High Speed IEEE-754 Double Precision Floating
Point Multiplier Using Verilog.
RTL Design and VLSI Implementation of an efficient
Convolutional Encoder and Adaptive Viterbi Decoder .
VLSI Implementation of a High Speed Single Precision Floating
Point Unit Using Verilog.
Design and implementation of truncated multipliers for precision
improvement.
Design of High Speed and Low Power 15-4 Compressor.
Design of an Error Detection and Data Recovery Architecture for
Motion Estimation Testing Applications.
An Efcient Architecture for 3-D Discrete Wavelet Transform,
High-Speed Low-Power Viterbi Decoder Design for TCM
Decoders.
Low-Power and Area-Efcient Carry Select Adder.
Period Extension and Randomness Enhancement Using HighThroughput Reseeding-Mixing PRNG.
An On-Chip AHB Bus Tracer With Real-Time Compression and
Dynamic Multiresolution Supports for SoC.
An On-Chip Delay Measurement Technique Using Signature
Registers for Small-Delay Defect Detection.
Accumulator Based 3-Weight Pattern Generation.
Implementation of Power Efficient Vedic Multiplier.
Design and Implementation of OFDM (Orthogonal Frequency
Division Multiplexing) using VHDL and FPGA.
Implementing of an CAN Protocol Using Verilog
A Novel Approach for Parallel CRC generation for high speed
application.
A High Speed and Area Efficient Booth Recoded Wallace Tree
Multiplier for fast Arithmetic Circuits.
Reducing the Computation Time in (Short Bit-Width) Twos
Complement Multipliers

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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016

SL.NO

YEAR

67

2011 T

68

2011 C

TITLE
Self-Immunity Technique to Improve Register File Integrity
against Soft Errors.
Design and Implementation of Low Power Digital FIR Filter
based on low power multipliers and adders on xilinx FPGA
** T- Transaction
**J- Journal
**C- Conference

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