Documente Academic
Documente Profesional
Documente Cultură
with VxWorks
A
Technical Report
Submitted By
Vaibhawa Mishra
This flow will cover all specific changes which must occur in all tool flows in order to
integrate the PowerPC wrappers with any custom partial or static VHDL modules.
Following these steps it should be possible to create the entire design. This experimental
system is for ML410 board for other boards the same step can be followed. When
configuration is needed from the FLASH, use TestApp_Peripheral form flash.c file in the
resource folder.
Tools required
1. ISE design suit 9.1 service pack 2
2. EDK 9.1 service pack 2
3. PlanAhead 10.1
Platform Used
Windows XP Professional
Installation of tools
1. Install ISE and EDK 9.1[ SetUp files available in ISE folder]
2. Enter the Registration ID, which is available in ISE folder as License.txt
3. Update ISE and EDK with patches ISE sp2 and EDK sp2 by double click on
these update patches[available in ISE folder]
4. Install PlanAhead 10.1 tool[ Move to Xilinx10i_completeSuite folder and Run
setup.exe, Choose ONLY PlanAhead 10.1 and Uncheck rest of the options and
continue installation]
5. Install PR9.1 tools
a. Unzip PartialFlow_91i_PR10_nt.zip into a temporary directory.[folder
already unzipped]
b. Ready to install partial reconfiguration implementation tools by
executing from a command prompt in the temporary directory:
xilperl PRinstall.pl PRfiles_nt.txt
Open XPS by selecting Start Programs Xilinx Platform Studio 9.1 Xilinx
Platform Studio. Refer to figure 1.
Use default setting of Base System Builder wizard and click OK as in figure 2
Click OK
Check the option I would like to create a new design. Click Next. As in figure 5
Xilinx in Board vendor, ML410 Evaluation Platform in Board name, and C in Board
revision fields, and then click Next as in shown 5
Select
o
o
o
o
Deselect MGT_wraper.
Click Next.
Select DDR2_SDRAM_32Mx_64 with use interrupt as the peripheral from this dialog
box. Both are shown in figure 12.
Select plb_bram_if_cntlr with 128 kb memory size as shown in the figure 13.
Click Next software Setup window will appear.
As in figure 14, deselect Memory test and select Peripheral Self-test options, and then
click next.
Note : Take care STDIN is selected with RS232_UART_1 from dropdown box
Next window leave as it is, and then click next twice and then generate option.
After copying of folder is done. Select Project Rescan User Repositories, in XPS, to
make the opb_dcr_socket visible in IP Catalog tab as in figure 16.
Select Addresses filter as in figure 19 and set 4KB, 64KB, 64KB, and 16 bytes for
opb2dcr_bridge_0, opb_hwicap_0, and opb_dcr_socket_0, opb_dcr_socket_1,
opb2dcr_bridge_0
opb_hwicap_0
opb_dcr_socket_0 --- SOPB
opb_dcr_socket_1 --- SOPB
opb_dcr_socket_2 --- SOPB
opb_dcr_socket_0 --- SDCR
opb_dcr_socket_1 --- SDCR
opb_dcr_socket_2 --- SDCR
SPI_EEPROM
4KB
64KB
64KB
64KB
64KB
16 bytes
16 bytes
16 bytes
64K
Note: You need to differentiate bytes & Kbytes from the dropdown. SDCR 16 bytes &
SOPB 64K
click Generate
Addresses.
Open Port_intro.rtf file located in resources folder and copy and paste the contents as
instructed in Port_intro.rtf in system.mhs file to add and bring out the ports at the toplevel.
After all desired hardware modifications, click on Generate Bit stream button, in
Hardware tab to synthesize the system as shown in the figure 20.
Select Software Software Platform Settings, and click on xilfats and xilmfs check
box to select the fatfs file system ddr file system support as in figure 21.
In drivers panel, make sure that opb_hwicap is set to use driver version 1.00.c as in
figure 22 (00. file is available in hwicap_v1_00_c folder @Resource.
Create a NEW folder named Drivers and copy the folder as it is & In EDK
ReScan)
Select Software Generate Libraries and BSPs to generate library files as in the file
23.
Open TestApp_Peripheral.c from the project resource folder and copy to
TestApp_Peripheral.c in application tab. ( All you need to do is, Replace the contents (i.e.
code) provided in Resource Folder)
Select Software Build All Users Applications to run LibGen to generate library files
and compiler to compile the application as in the figure 24.
Upto these steps, the system has been synthesized and application is ready.
Now, the following steps will show the designing of PRRs (Partial Reconfigurable
Region).
Step 2
In this step, the PRRs are designed separately in EDK and synthesized in ISE with
some precautions. Synthesizing of PRRs has different steps unlike the normal synthesis flow.
In this context, the steps for designing a PPR have been taken for only one module, rest of the
modules also have the same steps.
Select Create template for a new Peripherals click next as in figure 27.
Select OPB bus for this peripheral as in figure 30 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 31
Using drop-down button, select 2 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the 32 and click Next.
Click Next.
Click Next.
Click Next.
Above steps are only PRM 1 (adder of integer type ) for Reconfigurable Region 1. The
coming steps for PRM 2 (multiplier of integer type ) for Reconfigurable Region 1.
Select Create template for a new Peripherals click next as in figure 39.
Select OPB bus for this peripheral as in figure 42 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 42
Using drop-down button, select 2 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the 42 and click Next.
Click Next.
Click Next.
Click Next.
Above steps are only PRM 2 (multiplication of integer type) for Reconfigurable Region 1.
The coming steps for PRM 3 (division of integer type ) for Reconfigurable Region 1.
Select Create template for a new Peripherals click next as in figure 49.
Select To anXPS
project option, click Browse button, browse to
E:\vab_test_doc\edk_system\pcores (it depends on your project location), and click
OK as in figure 50.
Click Next.
Select OPB bus for this peripheral as in figure 52 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 53
Using drop-down button, select 2 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 54 and click Next.
Click Next.
Click Next.
Click Next.
Above steps are only PRM 3 (division of integer type) for Reconfigurable Region 1. The
coming steps for PRM 4 (subtraction of integer type) for Reconfigurable Region 1.
Select Create template for a new Peripherals click next as in figure 60.
Select OPB bus for this peripheral as in figure 63 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 64
Using drop-down button, select 2 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 65 and click Next.
Click Next.
Click Next.
Click Next.
Step 3
In this step, the PRMs (floating type arithmetic) are designed for PRR2 separately in
EDK and synthesized in ISE with some precautions. Synthesizing of PRRs has different steps
unlike the normal synthesis flow.
Select Create template for a new Peripherals click next as in figure 72.
Select OPB bus for this peripheral as in figure 75 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 76
Using drop-down button, select 4 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 76 and click Next.
Click Next.
Click Next.
Click Next.
to
Above steps are only PRM 1 (adder of floating point unit) for Reconfigurable Region 2. The
coming steps for PRM 2 (subtraction of integer type) for Reconfigurable Region 2.
Select Create template for a new Peripherals click next as in figure 83.
Select OPB bus for this peripheral as in figure 86 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click next. Shown in the figure 87
Using drop-down button, select 4 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 88 and click Next.
Click Next.
Click Next.
Click Next.
to
Above steps are only PRM 2 (subtraction of floating type) for Reconfigurable Region 2. The
coming steps for PRM 3 (division of float type) for Reconfigurable Region 2.
Select Create template for a new Peripherals click next as in figure 94.
Select To an XPS
project option, click Browse button, browse to
E:\vab_test_doc\edk_system\pcores (it depends on your project location), and click
OK as in figure 95.
Click Next.
Select OPB bus for this peripheral as in figure 97 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 98
Using drop-down button, select 4 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 100 and click Next.
Click Next.
Click Next.
Click Next.
resource\float\div
to
Above steps are only PRM 3 (division of floating type) for Reconfigurable Region 2. The
coming steps for PRM 4 (multiplication of float type) for Reconfigurable Region 2.
Select Create template for a new Peripherals click next as in figure 107.
Select To anXPS
project option, click Browse button, browse to
E:\vab_test_doc\edk_system\pcores (it depends on your project location), and click
OK as in figure 108.
Click Next.
Select OPB bus for this peripheral as in figure 110 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 111
Using drop-down button, select 4 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 112 and click Next.
Click Next.
Click Next.
Click Next.
to
Step 4
In this step, the PRMs (FFT calculation) are designed for PRR3 separately in EDK
and synthesized in ISE with some precautions. Synthesizing of PRRs has different steps
unlike the normal synthesis flow.
Select Create template for a new Peripherals click next as in figure 118.
Select OPB bus for this peripheral as in figure 114 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 115
Using drop-down button, select 5 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 116 and click Next.
Click Next.
Click Next.
Click Next.
resource\fft\fft4
to
Above steps are only PRM 1 (4 point fft calculation) for Reconfigurable Region 3. The
coming steps for PRM 2 (8 point fft calculation) for Reconfigurable Region 3.
Select Create template for a new Peripherals click next as in figure 123.
Select OPB bus for this peripheral as in figure 126 and click Next.
Select User logic S/W register support as the only support in IPIF Service form and
click next. Shown in the figure 127
Using drop-down button, select 5 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the figure 128 and click Next.
Click Next.
Click Next.
Click Next.
resource\fft\fft8
to
Synthesize Peripherals
Step 4
Start ISE by selecting Start Programs Xilinx ISE 9.1i Project Navigatoras
shown in figure 133
Open math [adder] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_a\devl\projnav and selecting math.ise
Open math [multiplier] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_b\devl\projnav and selecting math.ise
Open math [div] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_c\devl\projnav and selecting math.ise
Open math [sub] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_d\devl\projnav and selecting math.ise
Open prr [add] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_a\devl\projnav and selecting prr.ise
Open prr [sub] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_b\devl\projnav and selecting prr.ise
Open prr [div] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_c\devl\projnav and selecting prr.ise
Open prr [mul] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_d\devl\projnav and selecting prr.ise
Open fft [fft4] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\fft_v1_00_a\devl\projnav and selecting fft.ise
Select fft module in Sources window, right-click on it, and go to Add Source option.
Browse to E:\vab_test_doc\edk_sys\pcores\fft_v1_00_a\hdl\vhdl then select all files
except user_logic.vhd and fft.vhd file . These file will be added to the project.
Open fft [fft8] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\fft_v1_00_b\devl\projnav and selecting fft.ise
Step 5
Select File New Project to create a new ISE project as in figure 138
Let the name of the project be top in the project namefield (note that the directory
path is also appended with the name) as shown in figure 140.
Click Next.
Click Add Source, browse to resource folder given, and select top.vhd, leaving
copy to project box checked as shown in figure 142.
Step 6
This step is performed to create a floor plan of the reconfigurable region and placment of
bus macros, clock and other resources.
Open PlanAhead as shown in figure 145 by selecting Start Programs Xilinx ISE
Design Suit 10.1 Xilinx PlanAhead 10.1. the Planahead will be open as shown in
figure 146.
Click on Create A New Project. Window like figure 147 will be opened. Click Next.
Browse to E:\vab_test_doc directory, as shown in the figure 148. Notice that the Project
name selected is project_1 (if you already have a project in that directory then the tool
will pick next project number) click Next.
Select Yes, import a synthesized (EDIF or NGC) fileand click Next as shown in the
figure 149.
Figure 150-Selecting top.ngc and other required macros for the project
Select the device family from the Choose Product Family page as in figure 151.
Click Next to go to the Select device family part as in figure 152 form and select
XC4VFX60FF1152-11 device, and then click OK followed by click on Next to go to
Import Constraints form.
In Import Constraints form, click on Add button as in figure 153 and browse to
E:\vab_test_doc\edk_system\data directory and select system.ucf file. Click OK to
add it.
Select File Set PR Project to set the current project (project_1.ppr) as a PR project as
shown in figure 154.
Step 7
Select U1 (Math) module in Netlist panel, right-click and select Draw Pblock, and
draw a rectangle covering SLICE_X30Y208:SLICE_X41Y255 as in figure 155. This
will create area group.
Name it as d as the divider netlist was selected when the project was created. Shown in
figure 157
The Previous steps are again executed to create PRR2 and PRR3.
Select U2 (prr) module in Netlist panel, right-click and select Draw Pblock, and draw a
rectangle covering SLICE_X56Y128:SLICE_X71Y255.
This will create area
group.Select U2 (prr) module, right-click and select Set Reconfigurable option.
Name it as d as the divider netlist was selected when the project was created.
Select U3 (fft) module in Netlist panel, right-click and select Draw Pblock, and draw a
rectangle covering SLICE_X54Y0:SLICE_X73Y93. This will create area group.Select
U3 (fft) module, right-click and select Set Reconfigurable option.
Name it as 8 as the fft8 netlist was selected when the project was created.
For U1, select the option Add Reconfigurable Moduleas shown in figure 158.
Select Create Site Constraint Mode by clicking appropriate tool button (shown in Red
colour) as shown in figure 162 (This will allow us to place components in floorplan
window).
NTopPrmitivesABUS_0_BM _Generate[1].ABUS chk
ABUS_0_BM _Generate[2].
ABUS_0_BM _Generate[3].
ABUS_0_BM _Generate[4].
Control_1_0_BM
Control_2_0_BM
DBUS_0_BM _Generate[1].
DBUS_0_BM _Generate[2].
DBUS_0_BM _Generate[3].
DBUS_0_BM _Generate[4].
SDBUS_0_BM_Generate[0]
SDBUS_0_BM_Generate[1]
SDBUS_0_BM_Generate[2]
SDBUS_0_BM_Generate[3]
Abus_
0_BM
_gen
[0]
to[4]
Place all bus macros on the left edge of the all PR regions example is as given in figure
163. (Two Inner & Two Outer)
Click OK
At this stage, the ExploreAhead Runs tab should show static and 10 RM modules entry
as in figure 165
Run PR Flow
Step 7
This is last and final step. In this step, we assemble and merge the PRRs into full design.
Before we run the PR Implementation flow, we need to set path to system_stub.bmm file
in order to generate system_stub_bd.bmm file after the implementation.
For this, select options tab in Run Properties view. Select bm option under ngdbuild
and click anywhere in the field.
Browse to E:\vab_test_doc\edk_sys\implementation, select system_stub.bmm file, and
click Open. As shown in the figure 167
Select static in ExploreAhead Runs tab, right-click, and select Launch Run and
click OK to complete implementation as in figure 168
Same as above, select UI_d in ExploreAhead Runs tab, right-click, and select Launch
Runs as shown in the figure 169.
The last step in the PR Implementation flow is to run PR Assemble and PR Verify
design steps, which can be launched simultaneously by right-clicking one of the RM
modules and selecting Run PR Assemble. As shown in the figure 171.
Window will be pop-up as shown in the figure 172 to select the initial RM to be included
in static_full bit stream. Select divider as the initial RM module for region 1, select
divider as the initial RM module for region 2, select 8 as the initial RM module for
region 3 and
PR Assemble window will be popped out & process is in execution mode and keep
waiting, till you get OK dialog box as shown in Figure 173.
click OK to start the step.
When the step is completed, click OK and Close buttons as shown in the figure 174.
Step 8
Using
Windows
Explorer,
browse
to:\vab_test_doc\project_1
\project_1.runs\floorplan_1\merge directory and copy pblock_u1_blank.bit,
u1_a_partial.
bit,
cu1_m_partial.
bitu1_d_partial.bit,
u1_s_partial.bit,
pblock_u2_blank.bit,
u2_a_partial.bit,
u2_m_part-ial.bit,
u2_d_partial.bit,
u2_s_partial.bit, pblock_u3_blank.bit, u3_8_partial.bit, u3_4_partial.bit and place
them as vaba_b.bit, vaba_a.bit, vaba_m.bit, vaba_d.bit, vaba_s.bit, vabb_b.bit,
vabb_a.bit, vabb_m.bit, vabb_d.bit, vabb_s.bit, vabc_b.bit, vabc_8.bit, vabc_4.bit
respectively in E:\vab_test_doc\bits folder
pblock_u1_blank.bit
vaba_b.bit
u1_a_partial. bit
vaba_a.bit
u1_m_partial. bit
vaba_m.bit
u1_d_partial.bit
vaba_d.bit
u1_s_partial.bit
vaba_s.bit
pblock_u2_blank.bit
vabb_b.bit
u2_a_partial.bit
vabb_a.bit
u2_m_part-ial.bit
vabb_m.bit
u2_d_partial.bit
vabb_d.bit
u2_s_partial.bit
vabb_s.bit
pblock_u3_blank.bit
vabc_b.bit
u3_8_partial.bit
vabc_8.bit
u3_4_partial.bit
vabc_4.bit
Using Windows Explorer, browse to E:\vab_test_doc\project_1\project_1.runs\floorplan_1\merge directory and copy static_full.bit and place it in
E:\vab_test_doc\bits folder
Using Windows Explorer, browse to E:\vab_test_doc\edk_sys\TestApp_Peripheral
directory and copy executable.elf and place it in E:\vab_test_doc\bits folder
Using Windows Explorer, browse to E:\vab_test_doc\edk_sys\implementation
directory and copy system_stub_bd.bmm and place it in E:\vab_test_doc\bits folder
Under software platform verify that vxworks6_3 is selected for ppc405_0. As shown in
the figure 2.
Select sfgnu (software floating point) from the Tool chain drop-down menu.
Click Next.
Click Finish.
Include: C++ Components. Some components are pre-checked, leave them checked.
As shown in figure 13
Click Next and note the image size; then click Finish.
As shown in figure 14
Check WDB task breakpoints clickNext and then Finish. As shown is Figure 15
Click Next and include module manager and target unloader and then click next and
finish as shown in figure 16
Figure 16
Figure 17
Give the name of the file as test.c and Finish. As in figure 22. This file is given in
resource folder.
Using Windows Explorer, browse to E:\vab_test_doc\project_1\project_1.runs\floorplan_1\merge directory and copy static_full.bit and place it in
E:\vab_test_doc\bits folder
Using Windows Explorer, browse to E:\vab_test_doc\edk_sys\bootloopsdirectory and
copy ppc405.elf and place it in E:\vab_test_doc\bits folder
Open cmd shell by selecting Start Run go to the directory E:\vab_test_doc\bits
Execute the following command to generate download.bit file (having software
component included) from static_full.bit (having just hardware component)
Using Windows Explorer copy all files (13 partial bits) from bits folder into CF card
(Make sure that there are no files in CF card before copying). The Format of CF should
be FAT12.
Place the CF card into board, start HyperTerminal window with 9600 baud rate, and
download download.bit file through impact.
Run cd
vab.
Then typevab.
Do as instructed in menu
---------------------
Good Luck
----------------------------