Code.

No: 44027
R07 SET-1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
DIGITAL IC APPLICATIONS
(ELECTRONICS & INSTRUMENTATION ENGINEERING)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) Draw the circuit diagram of basic CMOS gate and explain the operation.
b) Distinguish between static and dynamic power dissipation of a CMOS circuit.
Derive the expression for dynamic power dissipation. [8+8]

2.a) Mention the D.C noise margin levels of ECL 10K family.
b) Design a three input NAND gate using diode logic and a transistor inverter.
Analyze the circuit with the help of transistor characteristics. [8+8]

3.a) Write a VHDL entity and architecture for the following functions.
F(x) =
b) Explain with an example the syntax and function of the following VHDL
statements.
i) Process statement
ii) Constant
iii) Variable and signal
iv) Case and loop statements [8+8]

4.a) Briefly describe the programming structure of VHDL.

b) Write down the VHDL program for comparing 8-bit unsigned integers. [8+8]

5.a) Draw the digits created by 74X49 seven-segment decoder for non-decimal inputs
1010 through 1111.
b) Write data flow style VHDL program for a simple 8-bit multiplexer. [8+8]

6. A 16-bit barrel shifter is a combinational logic circuit with 16-data inputs, 16-data
outputs and 4 control inputs. The input word is rotated by a number of bit
positions specified by control bits. Write a VHDL code for the above
implementation. [16]

7.a) Discuss the circuit of 74x377 register. Write a VHDL code for the above logic.
b) Design a modulo-64 counter using 74x163 IC. [8+8]

8.a) Draw the basic cell structure of dynamic RAM. What is the necessity of refresh
cycle? Explain the timing requirements of refresh operation.
b) With the help of timing waveforms, explain read and write operations of SRAM.
[8+8]
*******
Code.No: 44027
R07 SET-2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
DIGITAL IC APPLICATIONS
(ELECTRONICS & INSTRUMENTATION ENGINEERING)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) Compare HC, HCT, VHCT COMS logic families with the help of output
specifications with Vcc from 4.5V to 5.5V.
b) Explain the following terms with reference to CMOS logic
i) Logic levels
ii) D.C noise margin
iii) Power Supply rails
iv) Propagation delay [8+8]

2.a) List out different categories of characteristics in a TTL data sheet. Discuss
electrical and switching characteristics of 74LS00.
b) Design a CMOS transistor circuit with the functional behavior
F(X) = ( [8+8]

3.a) Discuss the steps in VHDL design flow.

b) Explain in detail about the following parameters
i) Libraries and packages
ii) Types and constants [8+8]

4. Design a logic circuit and write a dataflow style VHDL program for the following
Functions.
i) F(X) = ∑A,B,C,D (3,5,6,7,13)+d(1,2,4,12,15)
ii) F(X) = ∑A,B,C,D (0,1,3,5,14)+d(8,15) [16]

5.a) Design a 16-bit comparator using 74x85 ICs.

b) Write a VHDL program for 74x245. [8+8]

6.a) Design a priority encoder for 16 inputs using two 74X148 encoders.
b) Realize the following expression using 74X151 IC
F(X) = [8+8]

7.a) Design a conversion circuit to convert a T flip-flop to JK flip-flop.

b) What is the difference between Ring counter and Johnson counter. Design a self-
correcting 4-bit, 4-state Ring counter with a single circulating 0 using 74X194.
[8+8]
8.a) Discuss in detail ROM access mechanism with the help of timing mechanism.
b) Discuss how PROM, EPROM, EEPROM technologies differ from each other.
[8+8]
*******
Code.No: 44027
R07 SET-3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
DIGITAL IC APPLICATIONS
(ELECTRONICS & INSTRUMENTATION ENGINEERING)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) Explain the effect of floating inputs on CMOS gate.

b) Explain the performance characteristics of
i) Dynamic CMOS Logic
ii) CMOS Domino logic [8+8]

2.a) Compare CMOS, TTL, and ECL with reference to logic levels, D.C noise margin,
Propagation delay and fan-out.
b) Design a 4-input CMOS AOI gate. Draw the logic diagram and function table.
[8+8]
3.a) What is a sub-program? Give a detail view of function and procedures?
b) Give a brief account of Package Declaration and Package body. [8+8]

4.a) The Keyword ‘after’ is used for what purpose? Give its syntax and also briefly
explain the same.
b) Write a process based VHDL program for the prime number detector of 4 –bit
input and explain the flow using logic circuit. [8+8]

5.a) Design a full subtractor with logic gates and write VHDL dataflow program for
the Implementation of the above program.
b) Using the above subtractor design an 8-bit subtractor and write corresponding
VHDL Program. [8+8]

6.a) Design a 24-bit group ripple adder using 74X283 ICs.

b) Write a VHDL program for the circuit that counts number of ones in a 16-bit
register using structural style of modeling. [8+8]

7.a) Design a 3-bit LFSR counter using 74X194. List out the sequence assuming that
the initial state is 101.
b) Distinguish between latch and flip-flop. Show the logic diagram for both. Explain
the operation with the help of functional table. [8+8]

8.a) Discuss the operation of IOB in XC4000 FPGA with a neat sketch.
b) Explain the internal structure of 64X1 DRAM. With the help of timing
waveforms discuss DRAM access. [8+8]

*******
Code.No: 44027
R07 SET-4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
DIGITAL IC APPLICATIONS
(ELECTRONICS & INSTRUMENTATION ENGINEERING)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) Explain how a CMOS device is destroyed.

b) What is the difference between transition time and propagation delay? Explain
these two parameters with reference to CMOS Logic. [8+8]

2.a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL
gate? Draw the interface circuit and explain the operation.
b) Draw the circuit diagram and working principal of CMOS OAI gate. [8+8]

3.a) What is the importance of time dimension in VHDL and explain its function.
b) Write a VHDL program to generate a clock with off time and on time equal to
10ns. [8+8]

4.a) Explain the behavioral design model of VHDL.

b) What is type declaration? Give the different types of type declarations. [8+8]

5. Draw the logic diagram of 74x283 IC and explain the operation. Write the
dataflow model & VHDL program for this IC. [16]

6. Design a 24-bit comparator using 74X682 ICs and discuss the functionality of the
circuit. Also implement VHDL source code in dataflow style of modeling. [16]

7.a) Design a modulo-60 counter using 74X163 ICs.

b) Design a 4-bit binary synchronous counter using 74X74. Write VHDL code for
this logic. [8+8]

8. Write Short notes on

a) FPGA
b) CPLD
c) ROM applications. [16]

*******