Quick Guide steps for using Matlab HDL

coder with Xilinx ISE.

Quick Guide steps for using Matlab HDL coder with Xilinx ISE.
Initial Checks
1. Open Matlab System Generator from your Xilinx ISE panel
2. Ensure that the Xilinx Synthesis tool works. Type !ise in the matlab command window.
Create Project
3. Create a Working Directory for your project, name it.
4. Create your Matlab algorithm and save it to the previously create project folder.
5. Run and Test your Matlab algorithm
Transform matlab code to HDL
6. Run HDL Coder, for this, go to Application > HDL coder
7. Provide some name for you HDL coder project
8. In the HDL Code Generation window, click on Add Matlab Function. Select your Matlab
function(algorithm) m file.
9. Click on Add Files and select your Matlab testbench file.
Converting Data Types
10. Click on the Workflow Advisor, then select Define Input Types and click on Run.
This process runs your matlab algorithm and automatically defines your inputs type format, for
eg. double.
11. Select Fixed Point Conversion. This tool initializes and after it has been initialized click on
the Run Simulation available on the top of the window.
This converts your input and outputs to fixed point format with min, max and proposed type
indicated by Sim Min, Sim Max and Proposed Type. Here you can also manually specify the
conversion of your algorithm input/ output types to the desired fixed point.

12. Once satisfied and finished click on the Validate Types.

Select Code Generation Target:
13. Click the Select Code Generation Target tab, choose Generic ASIC/ FPGA in the Workflow,
Xilinx ISE in the Synthesis tool and let the default be for the chip family and package.
Viewing Outputs
14. Once the types conversion is validated and the synthesis tool selected, you can compare the
original signal numeric and the fixed point numeric of the conversion.
Click on the down arrow in the Test Numeric tab on the top, select Log inputs and outputs for
comparison plots. Then click the Test Numerics button. This generates outputs graph with fixed
point implementation and the original output graph.
15. At this point, you can see the matlab code implemented in fixed point format. To see this
code, click on the down arrow of the Verification Output tab and select Type Validation Output.
Click <filename>_fixpt to see the fixed point matlab code of the original <filename> matlab
function/ algorithms.
Generating HDL Code:
16. Select the HDL Code Generation and Run to generate HDL code. This generates VHDL file
from the fixed point matlab code.
17. Run and Test the generated HDL code
Enable Generate HDL test bench, enable stimulate gnerated HDL test bench, select Simulation
Tool(ISim), disable skip this step and Click on Run.
Synthesis and Analysis
Once the HDL code has been verified. The final step is the Synthesis and Analysis.
18. Click on Synthesis and Analysis and disable the Skip this step check box, and click Run.
This creates a project for the synthesis, runs the Xilinx synthesizer and place and route tool in
background, generates files related to synthesis and place and route operation- netlists and
related files, converts the netlist to circuit description, creates timing information and generates
report.
Output Files:
19. In the Project Folder, all the files during the process of matlab code to hdl conversion plus
synthesis and place and route are created.

The folder contains the following- original matlab code in floating point(or your data type) and test bench matlab code
- the fixed point converted matlab files and test bench matlab code
- the hdl codes converted from matlab files including testbench in hdl
- the outputs from the various steps
- Xilinx ISE project, including hdl files(VHDL or verilog), testbench hdl files, synthesis, place
and route, resource utilization, timing information etc.
Examples:
An example of schematic circuit in Xilinx generated by the above process HDL code.