Term End Examination - November 2014

Course

: ECE302

Class NBR

: 1891

Time

: Three Hours

- Computer Organisation and Architecture

Slot : E2

Max.Marks:100

General instruction:
Answer to the point with correct question number & sub division.
Answer any TEN Questions
(10 X 10 = 100 Marks)
1.

a) A computer has 3 instruction classes and CPI for the instructions given below.

[7]

Instruction Class A B C
CPI

For a program, a compiler writer is considering two code sequences that require the
following instruction counts.
Instruction counts (in billions)
Compiler 1

Compiler 2

10

If the clock rate of the computer is 4 GHz, calculate the throughput and execution
time for each of the compiler code.
b) Consider a computer with 3 levels of memory. Calculate the average memory access

[3]

time, given the access time and miss rate as below.

Memory Access Time(ns) Miss Rate

2.

Cache 1

5%

Cache 2

10%

RAM

50

a) Represent the given numbers in IEEE 754 Single precision Format.

[6]

(i) -14.79
(ii) 28.82
[4]

b) Perform subtraction (79)16 (82)16 Using 2s compliment arithmetic.

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3.

Design a simple and cost effective Central processing unit to adopt the following

[10]

conditions.
a) If the Processor address is 000 it has to do the 4 bit addition @ 5ms
b) If the Processor address is 010 it has to do the 4 bit subtraction @ 10ms
c) If the Processor address is 011 it has to generate CS Control @ 15ms
d) If the Processor address is 100 it has to generate SRAM Mem Read control @ 20ms
e) If the Processor address is 101 it has to generate EPROM Mem Read control
@ 30ms
4.

a) Write a code to implement the expression A= (B+C)*D, on 3,2,1 address machines.

[7]

Do not re-arrange the expression. In accordance with programming language practice

computing the expression should not change the value of its operands. Opcode
occupies 1 byte, address occupies 2 byte and operand occupies 1 byte.

5.

6.

b) Compute the total memory traffic in bytes for instruction fetch.

[3]

a) Show the Cache Read Operation with neat flowchart.

[5]

b) Describe dynamic RAM cell operation with internal structural diagram.

[5]

Illustrate and elaborate the role of Operating system as

[10]

a) Resource Manager.
b) Scheduler.
7.

a) A program is executed on a computer with 2.0 Clocks per instruction (CPI) when all

[8]

memory accesses hit in the cache. The only data accesses for the program are loads
and store and these are 75% of the instructions. If the miss penalty is 20 clock cycles
and the miss rate is 10%, how much faster would the computer be if the miss rate is
reduced to 2%?

8.

b) What are the disadvantages of single bus system?

[2]

Analyze the singlebus, detached DMA, Single-bus integrated DMA-I/O, I/O Bus

[10]

configurations with neat diagrams.

9.

a) Show the need of TLB and give its functionality to handle page fault and Conversion

[5]

of Virtual address to generate physical address using a neat flowchart. Draw the TLB
operation and Cache operation with neat diagram.
b) Illustrate, using a flowchart, the Booths Algorithm for signed multiplication.

[5]

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10.

a) What is meant by pipeline hazards? Explain briefly about various pipeline hazards.

[3]

b) Identify and mark the data hazards in the following instruction sequence.

[4]

LW r1, 0(r2)
Sub r4, r1, r5
And r6, r1, r7
Or r8, r1, r9
c) What are the possible methods to overcome the data hazards observed above?

[3]

11.

Classify computer architectures according to the Flynn taxonomy and elaborate it.

[10]

12.

a) Differentiate RISC and CISC processor.

[4]

b) Analyze the advantages and disadvantages of VLIW architecture and explain how

[6]

pipelining is carried out in VLIW architecture.

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