White Paper: Low-End Portfolio

WP460 (v1.0) March 31, 2015

Reducing System BOM Cost with

Xilinx's Low-End Portfolio
By: Cathal Murphy, Ehab Mohsen, and Srinivasa Kolluri

Xilinx's Low-End Portfolio adds a new perspective to system

cost analysis by offering many unique strategies for overall
BOM cost reduction.
ABSTRACT
System designers face continuous pressure to reduce the total Bill of Materials
(BOM) cost of the system. The systems BOM is made up of several different
but interdependent component costs, meaning a holistic approach is required
to ensure that the lowest overall BOM cost is achieved.
While system BOM cost is a concern for nearly all FPGA-based systems, it is
typically the high-volume applications that deal with exceptional cost
pressures. Industrial motor control, portable ultrasound, driver assistance
systems, and hand-held military radio are some examples where cost is a
signif icant factor.
With a balance of the right features and cost-effectiveness, Xilinx offers an
extensive Low-End Portfolio of products that delivers the best value for a
breadth of applications. The portfolio features the Spartan-6 FPGA family,
the Artix-7 FPGA family, and the Zynq-7000 All Programmable (AP) SoC
familyeach optimized for design requirements.
The diverse capabilities inherent in these product families can offer the system
designer numerous cost-reduction strategies, making them an ideal f it for
cost-sensitive applications in the industrial, medical, automotive, consumer,
and communication infrastructure markets, among others.
While total cost of ownership also involves other factors such as length of
design cycles, f ield upgradability, and development of derivative products, this
white paper focuses exclusively on the impact of device selection on system
BOM cost.

Copyright 2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. All other trademarks are the property of their respective owners.

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Introduction
The FPGA is one of the highest-value components in an electronic system; therefore, once it has
been determined that specifications can be met, it is naturally the first place to look for reducing
overall system cost. While examining device cost is a worthy (and necessary) exercise in itself,
analyzing device densities, speed grades, and packaging against the overall system requirements,
designers are best served with a holistic view, examining the impact that device features might
have on the design of the whole system, and hence on their effect upon the overall BOM cost.
It starts with an understanding of major cost drivers within a typical system's BOM, which include:

Digital logic components (e.g., FPGAs, ASSPs)

Processors (e.g., CPUs, MPUs, DSPs)

Analog Mixed Signal (AMS) components (e.g., amplifiers, ADCs, DACs)

Sensors (e.g., temperature, pressure, humidity)

Power supplies and thermal management components

Volatile and nonvolatile memory components

Passive components (e.g., resistors, capacitors, inductors)

Safety, security, and reliability components

Protocol PHY components

Analysis must include the cost of the printed circuit board (PCB) cost itself, including PCB layers,
mechanical components, and connectors.

Low-End Portfolio Overview

The Xilinx Low-End Portfolio, consisting of the Spartan-6, Artix-7, and Zynq-7000 device families,
targets this cost-sensitive market. As shown in Figure 1, having these three product families within
the Xilinx All Programmable Low-End Portfolio ensures that Xilinx can deliver optimized value to a
diverse set of cost-sensitive end applications and markets over a broad range of densities.
Specifically, the Xilinx Spartan-6 FPGAs deliver I/O optimization; the Artix-7 FPGAs deliver
transceiver optimization; and the Zynq-7000 All Programmable SoCs (Z-7010, Z-7015, and Z-7020)
deliver system integration and optimization for SoC applications. The Xilinx Low-End Portfolio
Backgrounder, available on the Xilinx website[Ref 1], provides an excellent overview of this newly
assembled portfolio of Xilinx product families.

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 1

Value

Integration

Performance
Performance
Performance
Power
Efficiency

I/O
Optimization

Power
Efficiency

Transceiver
Optimization

Power
Efficiency

SoC
Optimization

Broadest Cost Effective Low-End Portfolio

WP460_01_033115

Figure 1: Xilinx's Low-End Portfolio Value

The Spartan-6 family is the industry's low-cost leader and an ideal fit for simple to moderately
complex bridging functions found in a range of applications; this includes such market segments as
infotainment and consumer/industrial automation. In addition to high I/O-to-logic-cell ratios and
small form-factor package offerings, this device family offers best-in-class DSP and logic fabric
performance that meet the power requirements for many cost-sensitive systems.
For FPGA applications that demand more advanced functionality, however, the 28 nm-based
Artix-7 family offers exceptional performance per watt. The Artix-7 family leads the industry in
nearly every aspect of performance in a low-end device, including logic fabric performance,
memory line rates, and signal processing bandwidth.
One of the greatest distinctions of the Artix-7 FPGA is its array of transceivers. With line rates
exceeding 6 Gb/s, the family offers the industrys smallest and fastest transceiver-based devices
available in 10 x 10 mm packaging, making it an ideal low-cost alternative for bandwidth-sensitive
applications that might otherwise require more costly mid-range solutions.
For applications that require more than just bandwidthe.g., intelligent processing and analytics
to provide the highest levels of system optimizationthe Zynq-7000 family is an ideal solution. On
a single-chip platform, these devices bring together hardware, software, analog mixed signal, and
connectivity capabilities, both within the platform and outward to external devices. Fusing Artix-7
FPGA fabric to a dual-core ARM Cortex-A9 processor, the low-end Zynq-7000 AP SoCs (Z-7010,
Z-7015, and Z-7020) provide the highest level of system integration of the three families; this, in
turn, has downstream effects, reducing system power and maximizing performance.
While designers must select a device family based on these characteristics, equally important is the
impact their device selection has on system BOM cost. In Xilinx's product definition process, the
complete system cost for a huge variety of applications was analyzed to ensure that the overall
system BOM cost was specifically addressed across many different use cases. Xilinxs focus is on
delivering the highest functionality at the right price point while reducing system cost from
WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

multiple perspectives. See Figure 2.
X-Ref Target - Figure 2

System Integration and Optimization

Increasing capabilities and performance

Z-7010

Z-7015

Z-7020

Mid-Range

Transceiver Optimization
A15T

A35T

A50T

A75T

A100T

LX75

LX100

A200T

I/O Optimization
LX4

LX9 LX16

DENSITY:

20K

LX25

LX45
40K

60K

80K

LX150

100K +
WP460_02_033115

Figure 2: Low-End Portfolio by Logic Cell Density

Bill of Materials Cost Reduction Strategies

Several elements impact and contribute to overall BOM cost in a systemi.e., the costs of the
components and the board itself. Devices in the Xilinx Low-End Portfolio mitigate these costs by:

Eliminating components through systems integration

Reducing the cost of other components on the board through diverse functionality

Minimizing PCB development cost through best-in-class device packaging

Eliminating Components through System Integration

The advantage of a programmable device is not just customizable digital logic; it is, rather, the
broad array of functionsin some cases, non-digitalavailable in today's technology. A system's
high-value digital components can comprise processors, DSPs, ASSPs, FPGAs, or a combination of
these; its non-digital components can include ADCs, sensors, and PHY interfaces, among others.
Devices from Xilinx's Low-End Portfolio can integrate much of this functionality on a single chip.
High-density system integration like this not only lowers BOM cost, but because this process
reduces board space and overall power consumption, it lowers the cost of the PCB itself, as well as
the system's power and thermal management solutions.

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Processor Integration
Many applications require a processor to simplify the interaction of the system with a wider
network, with a human-machine interface (HMI), or with an observation-and-maintenance
solution. In the past, systems needed to contain both an FPGA and a discrete processor to meet
such requirements. However, Xilinx offers a range of processor-included solutions to meet a diverse
set of application requirements. External processors are no longer needed.

MicroBlaze IP Core Processors

All devices in the Xilinx Low-End Portfolio have access to the FPGA-based MicroBlaze soft
processor IP cores:

The MicroBlaze CPU is a 32-bit RISC Harvard architecture soft-processor core. A block diagram
of this IP is shown in Figure 3. It contains over seventy user-configurable options, enabling
implementation of virtually any processor use case, from a very-small-footprint state machine
or microcontroller to a high-performance, compute-intensive microprocessor-based system
running Linux. The IP can be configured to operate in either a three-stage pipeline mode (to
optimize for size), or in a five-stage pipeline mode (to optimize for speed)thus delivering
faster DMIPs performance than any other FPGA-based soft processing solution. For detailed
information and links to documentation, visit the MicroBlaze processor page on the Xilinx
website.[Ref 2]

X-Ref Target - Figure 3

Instruction-side
Bus Interface

Data-side
Bus Interface

Optional MicroBlaze Processor Feature

WP460_03_033115

Figure 3: MicroBlaze Soft Processor IP Block Diagram

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

The Zynq-7000 Family: Full-Featured FPGAs with On-Chip Dual-Core ARM Cortex Processors
The Zynq-7000 family offers even more in the way of processing options. Each Zynq-7000 AP SoC
contains a processor system, as shown in Figure 4. The processor system contains a 1 GHz
dual-core hardened implementation of the ARM Cortex-A9 MP Core microprocessor with extensive
OS, middleware, and stack ecosystem availability.
X-Ref Target - Figure 4

Processing System
Dynamic Memory Controller
DDR3, DDR2, LPDDR2

AMBA Switches

2x SPI

AMBA Switches

Programmable
Logic:
System Gates,
DSP, RAM
S_AXI_HP0

2x I2C

ARM CoreSight Multi-core & Trace Debug

I/O MUX

2x CAN
2x UART
GPIO

NEON/ FPU Engine

S_AXI_HP2

Cortex-A9 MPCore
32/32 KB I/D Caches

Cortex-A9 MPCore
32/32 KB I/D Caches

S_AXI_HP3

512 KB L2 Cache

2x USB
with DMA

General Interrupt Controller DMA Configuration

Timer Counters

2x GigE
with DMA

S_AXI_ACP

Snoop Control Unit (SCU)

2x SDIO
with DMA

EMIO

S_AXI_HP1

NEON/ FPU Engine

256 KB On-chip Memory

AMBA Switches

XADC

S_AXI_GP0/1

M_AXI_GP0/1

Multi-standards I/Os (3.3V & High Speed 1.8V)

Multi-standards I/Os (3.3V & High Speed 1.8V)

Static Memory Controller

Quad-SPI, NANO, NOR

PCIe

Serial Transceivers

WP460_04_033115

Figure 4: 1 GHz Dual-Core Hardened Implementation of the ARM Cortex-A9 MP Core Microprocessor
This extensive array of processing options ensures that, in the vast majority of applications, no
additional processor is required in the system, resulting in a significant BOM cost reduction. This
also enables massive performance improvements due to the data transfer speeds that can be
achieved between the on-chip processor and logic, as well as the hardware acceleration of
processing and analytics functions that can be performed in the programmable logic space.

Analog Mixed Signal

Because analog mixed signal components (e.g., analog-to-digital converters, amplifiers) continue
to be major contributors to a system's BOM, the 28 nm-based Artix-7 and Zynq-7000 families
provide an integrated analog mixed signal block called the Xilinx Analog-to-Digital Converter
(XADC),[Ref 3] containing:

A dual 1 MSPS 12-bit analog-to-digital converter (ADC)

Seventeen external voltage inputs

On-chip temperature and supply sensors

JTAG and zero-latency DRP interfaces

Not only can this block replace discrete ADC componentsbut when coupled with the signal
processing resources of the FPGA or AP SoC, the XADC can simplify and reduce the costs of the
WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

entire AMS signal chain. For more information on this topic, see the Xilinx white paper Efficient
Implementation of Analog Signal Processing Functions in Xilinx All Programmable Devices.[Ref 4]
For applications like motion control, power conversion, and distributed control systems, the XADC
can be used to directly replace discrete ADCs and cost-reduce or eliminate other elements in the
main control path. This results in a highly integrated, high-performance, yet low-cost solution,
similar to the motor control example shown in Figure 5.
X-Ref Target - Figure 5

VBUS

Zynq-7000 AP SoC

PMSM

Processor

Network
Interface

GPIO
(PWM)

3-Phase
Inverter

la lb
AMS

Control
Algorithm
(DSP)

ADC 1

ADC 2

la
VBUS
lb

WP460_05_033115

Figure 5: Integrated High-Performance Motor Control Solution

For applications that demand high reliability, security, or functional safety, the XADC provides
environmental monitoring capabilities, such as junction temperature and on-chip supply sensing,
eliminating the need for external monitor solutions, while at the same time meeting industry
standards such as IEC61508 and FIPS140-2.

PHY Integration
Given the growing array of interface standards and protocols, an external device (sometimes called
a PHY) might be required to physically translate the electrical signals to a form that can be
interfaced to an existing integrated circuit.
For a diverse number of protocols, Xilinx's Low-End Portfolio families offer interface support and IP
to help remove the requirements for external components. For example, HDMI video IP (compliant
up to HDMI 2.0) is available for all Artix-7 and Zynq-7000 devices. This IP removes the requirement
and associated cost of an external HDMI transmitter/receiver and replaces it with resistors on the
receive side and simple drivers/level-shifters on the transmit side.
Other interfaces supported by the Low-End families include DisplayPort, XAUI, V-by-One, 3G-SDI,
and JESD204B. For many of these protocols, multiple components are eliminated and overall
system cost is reduced.

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Safety and Security Components

A growing number of applications are required to meet industry standards for security, functional
safety, and reliability. As the world becomes more automated and interconnected, designers of
automation equipment must ensure that their systems operate in a safe manner that cannot be
interfered with, either by accident or by intentional adversaries.
Achieving the appropriate functional safety, security, and reliability standards is not a trivial task,
and it is ultimately one that significantly impacts the BOM of the overall system. The most
significant impact to BOM cost is the requirement for physical separation of certain functional
blocks, resulting in expensive multi-chip solutions. For functional safety and high reliability,
physical separation is required both for redundancy and for separation of safe and not safe
functions. For security, physical separation is required to ensure separation of encrypted and
unencrypted data.
Xilinx offers a unique Isolation Design Flow (IDF) tool (available for all Low-End Portfolio families)
that can be used to guarantee physical separation of functions within a single device. This
substantially reduces the number of components required on the board. The BOM cost savings
made possible by IDF is illustrated by the single-chip solution for a software-defined radio
application shown in Figure 6. IDF is one of the key enablers of this design model because it allows
encrypted and non-encrypted functions to share the same device.
This tool has been approved for use by the National Security Agency of the United States in Type 1
Cryptographic Systems. (For detailed information, see the Xilinx press release announcing this
approval.)[Ref 5] IDF is also certified by TD SD as a Software Tool for Safety Related
Development for ISO26262 and IEC61508, up to ASLID and SIL3 respectively. Additional details on
IDF can be found in the Xilinx white paper The Xilinx Isolation Design Flow for Fault-Tolerant
Systems[Ref 6] and in the Xilinx application note Developing Secure and Reliable Single FPGA
Designs with Xilinx 7 Series FPGAs or Zynq-7000 AP SoCs Using the Isolation Design Flow.[Ref 7]

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 6

Zynq-7000 AP SOC

PL

PS

Modem
Receiver
Analog
Front End

Data
Framer

Digital RF
Transmitter

Processor
Cryptographic Subsystem
Key Management:
SHA-2, HMAC, TRNG

Crypto Engine 1, AES

Crypto Engine 2, AES

Single Chip
Supports Data
Crypto Enabled Separation and Isolation
WP460_06_033115

Figure 6: System Integration for Software-Defined Radio

Reducing Component Cost

Many components on the board make up the infrastructure that ensures the core system elements
can perform to specification. Examples of these include components related to power delivery,
thermal management, and both volatile and nonvolatile memory. The cost of these functions is
often overlooked, resulting in higher BOM costand in lower system performance. However,
careful FPGA or SoC selection can simplify these infrastructure requirements and provide the most
cost-effective solutions.

Power and Thermal Management Components

Every device has unique power requirements (i.e., voltage levels, load currents, and number of
rails), typically requiring a DC/DC conversion solution optimized for the device. The cost of such a
power supply solution varies widely depending on a number of factors. The two main cost drivers
that the integrated circuit device manufactures can influence are:

The number of unique power rails required by the device

The amount of current flowing through (or power being consumed by) each rail

The effect that these factors have on power supply solution costs is shown in Figure 7.

WP460 (v1.0) March 31, 2015

www.xilinx.com

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 7

Normalized Average Cost

3.5
3

Cost per Ampere

2.5
2
1.5
1

Cost per Rail

0.5
0
0

Max Current (A)

WP460_07_033115

Figure 7: DC/DC Converter Cost

Another key driver of power supply solution cost are the actual manufacturer/vendor and device
chosen. Their cost, efficiency, and PCB area requirements vary widely, so consideration needs to be
given to finding the optimum solution for each system requirement.
Furthermore, the power dissipation of the system and the efficiency of the power conversion
system directly impact thermal management requirements, which (depending on power dissipation
needs) can range from nothing at all to an actively cooled system comprising large, expensive heat
sinks and fans. In many instances (e.g., industrial motor control), expensive thermal management
solutions are not an option for reasons of cost and reliability. Therefore, if a design cannot achieve
certain power targets, it cannot proceed.

Number of Unique Power Rails

Integrated circuits typically require a number of unique power rails (e.g., 1V, 1.8V). Each of these
rails requires a unique DC/DC converter. In some instances, different integrated circuits have the
same requirements; therefore, the DC/DC converters can be shared between components. In the
case of a programmable device, primary voltage requirements include those shown in Table 1.
Table 1: Power Rail Requirements for a Typical Programmable Device
Voltage
Supply

Purpose

VCCINT

Core logic (e.g., CLBs, DSP blocks)

VCCBRAM

Block RAMs (normally shared with VCCINT)

VCCAUX

Auxiliary logic (e.g., clock managers, configuration pins)

VCCO

I/O banks

MGTAVCC

Transceivers (analog)

MGTAVTT

Transceiver termination circuits (analog)

VCCINTPS

For processor subsystem (AP SoCs)

WP460 (v1.0) March 31, 2015

www.xilinx.com

10

Reducing System BOM Cost with Xilinx's Low-End Portfolio

As illustrated in Figure 7, pricing of DC/DC converters has a fixed element, meaning that every
unique rail in the system adds cost. Therefore, reducing the number of DC/DC converters on the
board always has a reduction impact on the overall BOM cost. This is especially true when the
current consumption of that rail is less than 2A, as the cost per rail dominates.
To help reduce the number of unique rails in the system, Xilinx minimizes the number of different
rails required to power its devices. Where this is not possible, Xilinx uses rail voltages that are most
likely to be already available in the system; alternatively, it tries to ensure that current requirements
are low enough so that, in many instances, inexpensive linear regulators can be used.
This strategy was implemented in the Spartan-6 FPGA, whose power supply requirements are
shown in Figure 8.

For designers not using transceivers, only two rails are required, 1.1V and 2.5V:
o

In many instances, 2.5V is already being used in the system for other components;
therefore, it can be shared.

In many other instances, the current requirement is so low that a low-cost linear regulator
can be used to provide 2.5V power to the Spartan-6 device.

If transceivers are to be used:

o

One additional 1.2V regulator is required. Given the tight ripple requirements on MGAVCC
and MGAV TT , it is not recommended to share it with other components.

X-Ref Target - Figure 8

Spartan-6 FPGA Power Supply Connections

1
Voltage Regulator
(VCCINT) (1.2V or 1V*)

VCC

VCCINT

Voltage Regulator
(VCCAUX) (2.5V)

VCCAUX

Voltage Regulator
(VCCO) (2 5V)

VCCO

AVCC

AVTT

3
LXT Only

Voltage Regulator
(AVCC and AVTT (1.2V)

*Spartan-6 LX/LXT FPGAs assume VCCO = 2.5V or 3.3V

for minimum supply count

VREF

Reference
Voltage (VREF)
WP460_09_110514

Figure 8: Spartan-6 FPGA Power Supply Requirements

In the case of Artix-7 and Zynq-7000 deviceseven for the lowest-power -1LI speed gradethe
VCCINT and VCCBRAM voltages can be tied together and their voltage taken down to 0.95V. This
eliminates the need for a unique voltage rail for VCCBRAM.

WP460 (v1.0) March 31, 2015

www.xilinx.com

11

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Low Power Dissipation

Power is increasingly becoming a key differentiator for the small-form-factor, high-performance
space that requires tight thermal and power budgets. Through the combination of innovative
product architectures and by leveraging the best foundry processes in the industry (such as the
TSMC 28 nm High Performance Low Power (HPL) process), Xilinx is able to deliver high
performance with up to a 30% power savings, versus the nearest competitor, for all 7 series devices.
Refer to the Xilinx white paper Lowering Power at 28 nm with Xilinx 7 Series FPGAs.[Ref 8]
Architectural innovations include:

Transceivers to granularly balance power and performance trade-offs

Multi-mode I/O control to dynamically disable input and output buffers as needed during
memory interface write, read, and idle states

Intelligent clock gating of unused components

Power binning and voltage scaling of screened parts for lower operating voltage

These power-saving features are shown in Figure 9.

X-Ref Target - Figure 9

Figure 9: Xilinx Power Reduction at 28 nm v. Previous Generation

While voltage scaling and the low-power device options are available for all 7 series FPGAs (Artix-7,
Kintex-7, and Virtex-7), as well as for Zynq-7000 AP SoCs, low-end devices in particular offer
extensive voltage scaling options that reduce overall power by an additional 30% while retaining
needed performance (see Figure 10 and Table 2).
This is made possible by the headroom (i.e., flexibility permitting performance and power
trade-offs) gained with the 28 HPL process. While normal operating voltage is 1.0V, low-end
devices can offer a 0.95V option for -1 industrial speed grade (-1L I ) devices while retaining
identical performance.

WP460 (v1.0) March 31, 2015

www.xilinx.com

12

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 10

Figure 10: Total Power Reduction with Voltage Scaling for Low-End Industrial-Grade Devices

Table 2: Additional ~20-30% Total Power Reduction with Voltage Scaling (-1LI)
VCCINT(1)
-1I, -2I

Static Power Savings

Dynamic Power Savings

1.0V

0%

0%

Artix-7 -1LI

0.95V

50%

10%

Zynq-7000
Low-End -1LI

0.95V

50%

10%

45%

0%

1.0V(2)

Notes:
1.
2.

For Zynq-7000 devices, voltage change is limited to programmable logic.

At 1.0V, one voltage rail can be used for both FPGA logic and processor sub-system.

Given the dependency on DC/DC converter pricing for the amount of current being consumed by
each power rail (see Figure 7), the substantial power savings offered by Xilinx devices reduces
power supply cost.
In addition, the cost of the passive components (inductors, capacitors, etc.) required by the DC/DC
converter vary greatly with their size, which in turn often tracks closely with the amount of current
the device must be capable of handling. For example, using a power supply calculator[Ref 9]
provided by one major vendor, the total cost of a 1.0V rail decreases 33% by reducing its maximum
current rating from 3A to 2A. (In this example, the large cost differential is driven mainly by the cost
of the inductor.)

WP460 (v1.0) March 31, 2015

www.xilinx.com

13

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Optimum Power Supply Solutions

The cost effectiveness of power supply solutions varies widely depending on the vendor and the
specific device chosen. Xilinx partners with leading power supply vendors in the industry to meet
diverse requirements at the most attractive price, with the smallest board area, and at maximal
efficiency. In addition, given their broad view of complete system power requirements for various
applications, power control vendors are in a unique position to be able to offer the best solutions.
The diverse range of use cases makes it difficult to create a one-size-fits-all solution. However, a
number of highly integrated solutions offer compelling value for a vast array of end use cases. The
Analog Devices ADP5050/1/2/3 and the Texas Instruments TPS65261/2 are two such system power
control devices that provide outstanding flexibility and performance while requiring minimal board
space.
The Avnet Artix-7 50T FPGA Evaluation Kit (AES-A7EV-7A50T-G) uses one of these parts, the Analog
Devices ADP5052; given a 5V input, this one device provides a complete power solution for the
entire board. For more information on this evaluation kit, visit the Xilinx website.[Ref 10]
Solutions like these offer excellent value, as they provide a large number of rails that, in many
instances, can provide a complete power supply solution for the entire system, not merely for the
programmable device itself. In addition, they require only a small amount of board space and are
routable on two layers.

Configuration Memories
Programmable devices typically require storage for device configuration while processors require
storage for their program instructions. This means system designers must factor in components
such as configuration memory.
While some currently available programmable solutions have integrated nonvolatile memory
(NVM) within the device, they are typically designed on older processing technologies. Therefore,
they often cannot deliver the signal processing capabilities, high clock speeds, and gigabit
transceiver rates required by many of today's equipment manufacturers. In addition, storage
requirements for many applications (e.g., protocol stacks) often exceed the capacity of these
integrated NVMs.
Other programmable solutions support only their own configuration device, forcing system
designers to use their own, often very expensive, configuration solution.
Xilinx's Low-End Portfolio supports the most popular open-market flash interfaces, ensuring that a
low-cost, commonly used configuration device can be chosen. Also supported are many options
for remote configuration via an external processor, making use of a centrally located NVM that is
shared across the complete system. For more details on this type of application, see the Xilinx
application note Using a Microprocessor to Configure 7 Series FPGAs via Slave Serial or Slave
SelectMAP Mode.[Ref 11]
Table 3 gives a brief overview of flash implementation approaches.

WP460 (v1.0) March 31, 2015

www.xilinx.com

14

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Table 3: External Flash Support
Configuration
Mode

Configuration
Device

Slave Serial

Microprocessor

Master SPI

SPI

Flash(1)

Master BPI

BPI Flash

Master Serial

Xilinx PROM

Slave SelectMAP,
Slave Parallel

Microprocessor

Relative Cost
Effectiveness
Most Cost-Effective

Least Cost-Effective

Notes:
1.

Competitive advantage over leading FPGA vendors

Volatile Memory
Xilinx's low-end products contain a significant amount of integrated dynamic storage in the form
of block RAM, distributed memory, processor caches, and on-chip memory (OCM). In many cases,
the memory available within the device, either directly or via innovative methods,[Ref 12] is
sufficient for many applications, therefore eliminating the need for off-chip dynamic memory
devices like SDRAM.
However, a number of applications require additional external memory (e.g., frame buffering in
video processing applications). System designers must factor in the cost of these external
memories for the entire product life cycle. Xilinx supports SDRAM DDR3 across its complete
Low-End Portfolio, including the Spartan-6 family. DDR3 is currently the lowest cost per Mb/s
option, and is likely to continue to be for the foreseeable future.[Ref 13]

Ensuring the Smallest, Lowest-Cost Programmable Device

High Utilization
One of the primary criteria when selecting a programmable solution is device density. Designers
naturally want the smallest, lowest-cost device possible for their applications. Historically, the
challenge with programmable solutions is maximizing utilization of logic resources for any given
design without sacrificing performance. By nature of traditional architectures and implementation
tools, imperfect design packing is inevitable, leading to significantly less than 100% utilization and
potential performance degradation.
With the 28 nm families, Xilinx leveraged its next-generation design environment, the Vivado
Design Suite, to ensure maximum device utilization and performance from its silicon architecture.
With the tool's hierarchical implementation and analytical engine, Xilinx low-end 28 nm devices
can deliver the following advantages over the competition:

A full speed grade of performance improvement

20% better device utilization

WP460 (v1.0) March 31, 2015

www.xilinx.com

15

Reducing System BOM Cost with Xilinx's Low-End Portfolio

The Vivado Design Suite realizes the potential of a device's programmable logic fabric and
dedicated on-chip functional blocks through architecture and software integration to yield
maximally efficient results. The speed grade and utilization improvements directly impact the cost
of the device because small, lower-speed-grade devices can be used to perform the same task.

Partial Reconfiguration
Xilinx partial reconfiguration extends the inherent flexibility of the FPGA by allowing specific
regions of the FPGA to be reprogrammed with new functionality while applications continue to run
in the remainder of the device. In many designs, there can be a number of mutually exclusive
functions. Partial reconfiguration can be used to configure the FPGA with only the functions that
are required at that particular instance in time. An example of this is illustrated in the Xilinx
application note Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable
SoC Devices.[Ref 14]
Partial reconfiguration offers very unique benefits from a BOM cost perspective because it has the
potential to substantially reduce the device density requirement and power consumption of the
design.

Reducing Printed Circuit Board (PCB) Costs

In the absence of adequate care, attention, and planning, the cost of the PCB can become a very
significant part of the overall system cost. The key drivers for PCB cost are the number of layers
required, the size of the board, and the need for cutting-edge PCB technology like laser vias and
fine trace widths.[Ref 15]

Reducing PCB Layers with Innovative Packaging Solutions

Innovative packaging in Xilinx's Low-End Portfolio products ensures that the lowest-cost PCB
solution can be found. An excellent example of this is the Artix-7 FPGA CPG236 package. The
package itself is a 10 x 10 mm, 0.5 mm pitch BGA, with more than 100 usable I/Os. In general,
routing to a 10 x 10 mm, 0.5 mm pitch BGA requires many PCB layers and the use of fine-geometry
design rules. However, the innovative ball-grid pattern allows all of the balls to be routed on only
two layers using standard spacing and via sizes.

Board Area Reduction via System Integration

PCB costs are also substantially reduced by system integration, choice of an optimum power supply
and distribution method, component size, and so forthbecause they all affect the size of the PCB
as well as the level of interconnect required. This can directly affect the number of PCB layers
required, which in itself a huge cost factor.

BOM Cost Savings in End Applications

To further illustrate the BOM cost savings possible in end applications with Xilinx's low-end
product family, a number of typical application examples have been analyzed from a BOM cost
perspective relative to competitive products.

WP460 (v1.0) March 31, 2015

www.xilinx.com

16

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Sensor Interface with Artix-7 Devices

A range of end markets, e.g., industrial process control and in-service monitoring systems in large
mechanical equipment, use FPGAs such as the Artix-7 XC7A35T device to aggregate and process
sensor data and transmit critical information to a central host. The type of sensors used can vary
widely depending on the application, but can include temperature, pressure, strain, position, and
vibration sensors.
The block diagram shown in Figure 11 represents a typical circuit architecture and BOM for a
sensor interface board using a a non-Xilinx FPGA.
X-Ref Target - Figure 11

Competing FPGA Vendor

Sensors
Temp
Pressure

Receiver

MUX

ADC

Vibration

Data
Analysis and
Processing

to host
Transmitter

Humidity

Power Supplies

Config
WP460_11_033115

Figure 11: Sensor Interface (Competing FPGA)

In contrast, the block diagram in Figure 12 illustrates the Xilinx Artix-7 solution, using an Artix-7
XC7A15T FPGA.
X-Ref Target - Figure 12

Xilinx Artix-7 XC7A15T FPGA

XADC

Sensors
Temp
Pressure
Vibration

ADC
MUX

Receiver
Data
Analysis and
Processing

to host
Transmitter

ADC

Humidity

Power Supplies

Config
WP460_12_033115

Figure 12: Sensor Interface (Artix-7 XC7A35T)

Figure 13 illustrates that the Xilinx Artix-7 FPGA solution provides a BOM cost saving of up to 30%,
relative to the most comparable competitive FPGA. These savings are realized by leveraging the
Artix-7 FPGAs lower-power, two-layer PCB routing that is made possible by its 10 x 10mm BGA
connection technology. Additionally, the Artix-7 device works with inexpensive off-the-shelf
configuration devices, and features a fully integrated, on-chip Xilinx analog-to-digital converter
(XADC).

WP460 (v1.0) March 31, 2015

www.xilinx.com

17

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 13

100%
90%

Normalized BOM Cost

80%
70%

PCB

60%

ADC
Inductor

50%
Power
40%

Config

30%

FPGA

20%
10%
0%

Competing FPGA Vendor

Xilinx (Artix-7 FPGA)

WP460_13_033115

Figure 13: Sensor Interface BOM Cost Savings

Machine Vision with Spartan-6 Devices

Machine vision cameras are another common application niche for low-end FPGAs. Devices, such
as the Spartan-6 XC6LX45 FPGA, interface with an image sensor, perform complex image signal
processing, implement custom IP, and transmit the recovered data to a central controller by way of
various communications protocols. A typical block diagram using a Spartan-6 FPGA is shown in
Figure 14.
X-Ref Target - Figure 14

Spartan-6
XC6SLX45
Spartan-6
XC6SLX45
FPGA

Image
Sensor

Image Signal
Processing
(ISP)

Sensor
Interface

Power Supplies

Memory
(DDR)

Custom IP

Ethernet
PHY

Config
WP460_14_033115

Figure 14: Machine Vision with Spartan-6 FPGA

Some competitors FPGAs, especially those manufactured using larger process geometries like
embedded 55 nm, simply cannot perform the necessary digital signal processing required by this
application. When this is the case, the only option is to use an external DSP or ASSP (as shown in
Figure 15) to perform the intensive image signal processingor, use a more powerful FPGA, like
the Spartan-6 device.

WP460 (v1.0) March 31, 2015

www.xilinx.com

18

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 15

Another FPGA

ASSP/DSP

Image
Sensor

Sensor
Interface

Power
Supplies

Image
Signal
Processing
(ISP)

Custom IP

Memory
(DDR)

Ethernet
PHY

Config
WP460_15_033115

Figure 15: Machine Vision Using a Low-Performance FPGA and ASSP

As can be seen from Figure 16, highly significant BOM cost savings (up to 34%) can be realized by
choosing the higher-performance Spartan-6 device, when compared to low-performance
alternatives that require additional ASSP/DSP functionality to perform the complex image
processing required of this application.
X-Ref Target - Figure 16

100%
90%

Normalized BOM Cost

80%
70%

PCB
Power

60%

Memory
50%
PHY
40%

ASSP/DSP
FPGA

30%
20%
10%
0%

Competing FPGA Vendor

Xilinx (Spartan-6 FPGA)

WP460_16_033115

Figure 16: Machine Vision BOM Cost Comparison

Industrial Ethernet for Motor Control Using a Spartan-6 FPGA

FPGAs are widely used to realize industrial Ethernet interfaces for motors and similar equipment. A
block diagram for a typical Ethernet-based motor control application is illustrated in Figure 17.

WP460 (v1.0) March 31, 2015

www.xilinx.com

19

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 17

Spartan-6 FPGA

RS-485

I/O Legacy,
Field Bus

RS-232
CAN

Ethernet PHY
10/100/1000

Industrial
Networking
Communications
Processor

Motor
Control

Motor

(MicroBlaze Processor)

Ethernet Switch
MAC

System
Management
(MicroBlaze
Processor)

WP460_17_033115

Figure 17: Spartan-6 FPGA Ethernet Industrial Motor Control Solution

An alternate approach to an industrial motor controller implementation is to use an industrial
Ethernet ASIC and MCU, as shown in Figure 18. However, as shown in Figure 19, the Xilinx solution,
which uses a Spartan-6 FPGA, offers a substantial BOM cost saving of up to 27% over competitive
non-FPGA design models.
X-Ref Target - Figure 18

RS-485

HOST
Management
System

RS-232
CAN

Industrial ASIC

Ethernet PHY
10/100/1000

I/O Legacy,
Field Bus

MCU
Motor
Control

Motor

Industrial
Networking
Communications
Processor
Ethernet Switch
MAC
WP460_18_033115

Figure 18: Typical Non-FPGA ASIC/MCU Solution for Ethernet-Based Motor Control

WP460 (v1.0) March 31, 2015

www.xilinx.com

20

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 19

100%
90%

Normalized BOM Cost

80%
70%
Ethernet PHY
60%

PCB
Inductor

50%

Power
40%

Industrial Ethernet ASIC

32-Bit MCU/FPGA

30%
20%
10%
0%

32-Bit MCU+ASIC

Xilinx Spartan-6 FPGA

Implementation

WP460_19_033115

Figure 19: BOM Cost Savings, ASIC/MCU Solution vs. Xilinx Spartan-6 FPGA

Integrated Programmable Logic Controller (PLC) Using Zynq-7000 Z-7010 SoC

A very common application for the Xilinx Zynq-7000 Z-7010 AP SoC is for a PLC, e.g., in a
motion-control system. A typical block diagram is shown in Figure 20.
X-Ref Target - Figure 20

Zynq-7000 Z-7010 FPGA

PS

PL

PLC
Run-time
Application

Custom IP
MicroBlaze Industrial
Processor Ethernet

HMI
Application

Power
Supplies

Ethernet
PHY

XADC

Storage
(Flash)
WP460_20_033115

Figure 20: Block Diagram of Motor Drive Using Zynq-7000 Z-7010 SoC
Figure 21 shows that Xilinx is able to realize up to 23% BOM cost saving relative to its nearest
competition for this PLC application. This saving is realized by leveraging the Zynq-7000 AP SoCs
larger OCM capacity, as well as its XADC and PCB area savings.

WP460 (v1.0) March 31, 2015

www.xilinx.com

21

Reducing System BOM Cost with Xilinx's Low-End Portfolio

X-Ref Target - Figure 21

100%

90%

80%

PCB

Normalized BOM Cost

RAM
70%
ADC
60%

Inductor
FETs

50%

Power
40%
Power
30%

NAND
SoC

20%

10%

0%

Competing FPGA SoC Vendor

Xilinx Zynq-7000 Z-7010 AP SoC

WP460_21_033115

Figure 21: Motor Drive BOM Cost Savings: Competitive SoC vs. Xilinx Zynq-7000 Z-7010 AP SoC

Conclusion
When opting for a high-value component like an FPGA or AP SoC, designers must look beyond
component unit cost to instead consider its overall impact on total BOM cost.
Xilinx's Low-End Portfolio solutions can impact cost savings across major system design categories,
including processor elements, power supplies, analog mixed signal components, safety and
security components, memories, and PCB boards, among others. Enabled by three diverse families,
the Xilinx Low-End Portfolio adds a new perspective to system cost analysis and offers unique
solutions to overall system cost reduction.
For additional details on the Xilinx All Programmable Low-End Portfolio, visit the Xilinx
website.[Ref 16]

WP460 (v1.0) March 31, 2015

www.xilinx.com

22

Reducing System BOM Cost with Xilinx's Low-End Portfolio

References
1. Xilinx Backgrounder, Low-End Portfolio
2. Xilinx website, MicroBlaze Soft Processor Core
3. Xilinx website, Analog Mixed Signal
4. Xilinx white paper WP442, Efficient Implementation of Analog Signal Processing Functions in
Xilinx All Programmable Devices.
5. Xilinx press release, August 31, 2011: NSA Approved Defense-Grade Spartan-6Q FPGA in
Production for Highest Level Cryptographic Capabilities Strengthens Xilinx Secure Leadership
6. Xilinx white paper WP412, The Xilinx Isolation Design Flow for Fault-Tolerant Systems.
7. Xilinx application note XAPP1086, Developing Secure and Reliable Single FPGA Designs with
Xilinx 7 Series FPGAs or Zynq-7000 AP SoCs Using the Isolation Design Flow.
8. Xilinx white paper WP389, Lowering Power at 28 nm with Xilinx 7 Series FPGAs.
9. Texas Instruments website, WEBENCH Power Designer:
www.ti.com/lsds/ti/analog/webench/power.page
10. Xilinx website, Artix-7 50T FPGA Evaluation Kit
11. Xilinx application note XAPP583, Using a Microprocessor to Configure 7 Series FPGAs via Slave
Serial or Slave SelectMAP Mode.
12. Xilinx Tech Tip, Zynq-7000 AP SoC BootBooting and Running Without External Memory.
13. EETimes, DDR4 Ramps Up, Enterprise First Hilson, G., 9/9/2014:
www.eetimes.com/document.asp?doc_id=1323826
14. Xilinx application note XAPP1159, Partial Reconfiguration of a Hardware Accelerator on
Zynq-7000 All Programmable SoC Devices.
15. Staci Corporation white paper, Printed Circuit Board Cost Drivers:
www.stacicorp.com/white_papers/PCB-Cost-Drivers-White-Paper.pdf
16. Xilinx website, All Programmable Low-End Portfolio

WP460 (v1.0) March 31, 2015

www.xilinx.com

23

Reducing System BOM Cost with Xilinx's Low-End Portfolio

Revision History
The following table shows the revision history for this document:
Date

Version

03/31/2015

1.0

Description of Revisions
Initial Xilinx release.

Disclaimer
The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx
products. To the maximum extent permitted by applicable law: (1) Materials are made available AS IS and with all faults,
Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT
LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability)
for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your
use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss
of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even
if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx
assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written
consent. Certain products are subject to the terms and conditions of Xilinxs limited warranty, please refer to Xilinxs
Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and
support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe
or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products
in such critical applications, please refer to Xilinxs Terms of Sale which can be viewed at http://www.xilinx.com/
legal.htm#tos.

Automotive Applications Disclaimer

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR
(III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF
ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

WP460 (v1.0) March 31, 2015

www.xilinx.com

24