ME310

Manufacturing Processes
Rahul Panat

School of Mechanical and Materials Engineering

Washington State University
1

HW-1 REVIEW OF SELECT QUESTIONS

HW-1 REVIEW OF SELECT QUESTIONS

Manufacturing of Microelectronics
and MEMS Devices

Ack: Prof. McCloy for some material

BACKGROUND
Why study this topic?
Electronic devices have revolutionized our world!

Conceptual

Google Contact Lens

Apple Watch

Intel-Fossil
Bracelet

LENGTH SCALES IN ELECTRONIC

DEVICES

Flexible Boards with components* (100um~10mm)

Google Glass

Solder Resist

Co

(w

PTH
Filling
material

Intels 32nm Si **
(10s nm ~ 10um)

Processor**
(10s nm ~ 100um)

Cu
(Pa

Highly Complicated Layered Structure

Patterned Cu
Vias
Dielectric
Plated through holes in core
Thick Core
Solder resist and bumping

PCB (10um ~ 100um)

Length scales drive specialized manufacturing methods

*Source:

Teardown.com
**Intel public information

LENGTH SCALE DRIVEN MANUFACTURING

Needs cleanrooms!

Intel lithography now at 14um in HVM

And 11 nm and below in research

BRIEF HISTORY
Transistor discovered in Bell labs enabling modern
computing revolution
Vacuum tubes used in computers limiting the number of
circuits in the computer; highly bulky
Solution: Jack Kilby patented first IC design and showed
first prototype; Bob Noyce (Intel founder) patented Al
metallization connect the ICs
Microelectronic manufacturing as a separate area emerged
from the miniaturization started by Kilby/Noyce

Bob Noyce

Jack Kilby

Jack Kilby, Texas Instruments, Miniaturized electronic circuits, U.S. Patent US3138743 A
Robert Noyce, Intel Corporation, Semiconductor device, U.S. Patent 2,981,877

IC MINIATURIZATION
Miniaturization of circuits continues per the prediction by Intels Moore
(Moores Law) With unit cost falling as the number of components per
circuit rises, by 1975 economics may dictate squeezing as many as 65 000
components on a single silicon chip..well.a chip with
3.1 billion components* was released in 2012 by Intel..

Major area of manufacturing research in

electronics due to the massive (exponential)
pace of miniaturization!

SILICON

Why Si
Cheap
SiO2, used for isolation and passivation and can be reliably and easily formed to
form the basis for metal oxide semiconductor (MOS) devices

Doping required for to make Si a semiconductor

N-type dopant Phosphorous (group IV)
P-type dopant Boron (group III)

SILICON WAFER
Making electronic grade silicon
SiO2 + C

Heat

95-98% pure
polycrystalline Si

Trichlorisilane

High T
H2 atm

ECG

Crystal growth by Czochralski (CZ) method

Video Link

WAFER PROCESSING

CLEANING

CLEANING
Cross-contamination due to
close spacing between wafers

Wafers in a Chemical Bath

>1 hour process: long chemical

exposure causes undesired loss
of silicon and oxide

Long cycle time and high workTotal Time: >1 hour

in-process

Large footprint
30 year old technology

PHOTOLITHOGRAPHY

Masking
Projection
system
Photoresist

Considerations
Feature size
Wavelength

TYPICAL RESIST PROCESSES

HMDS: hexamethyldisilzane

OXIDATION

OXIDATION

DIFFUSION AND ION IMPLANTATION

DIFFUSION AND ION IMPLANTATION

Other types of PVD used in research

Molecular beam epitaxy (MBE)
Pulsed laser deposition (PLD)
Atomic layer deposition (ALD)

Types of CVD
Atmospheric pressure CVD (APCVD)
Low pressure CVD (LPCVD)
Plasma enhanced CVD (PECVD)
Hybrid physical-chemical VD (HPCVD)

DIFFERENCE BETWEEN PVD AND CVD METHODS: chemical decomposition of precursor

gas (CVD) versus vaporization of solid source (PVD)

CVD

PVD

PVD: Sputtering

DEPOSITION

ETCHING

ETCHING PROCESSES

ETCHING PROCESSES

WET vs PLASMA ETCHING

CHEMICAL vs PHYSICAL ETCHING

ETCHING ISSUES

BACKEND: DIELECTRICS AND

INTERCONNECTS

PACKAGE TYPES

Leadframe

Flip Chip

CSP: Chip Scale Package

Stacked Chip Scale Package

FC-CSP
www.emeraldinsight.com
computing-dictionary.thefreedictionary.com

FLIP CHIP PACKAGE: MICROPROCESSOR

Passives

First Level Interconnect

Si: ~3ppm/K
Package: ~17ppm/K

die
Die Bump

solder
substrate

Underfill (polymer)
die
Substrate (fiber reinforced polymer with metal traces connecting die to second level interconnect)
Motherboard (containing chipsets, power supply, Signal I/O connectivity and other peripherals)

substrate

Second Level
Interconnect
solder
PCB board

Schematic Ack Dr. Hill

LAYERED COMPOSITE
Solder Resist

Bump(lead free)
Vias connecting Cu layers
Dielectric Film
Core Material
(woven glass

PTH Filling
material

Highly Complicated Layered Structure

Patterned Cu
Vias
Dielectric
Plated through holes in core
Thick Core
Solder resist and bumping

composite)
Cu Layers
(Patterned)

STACKED CSP* PACKAGE: MEMORY

5 die stacked memory package
(Molding compound removed isometric view)

Gold Wires
(~20um )
Molding Compound

Stacked Dies
Substrate

Multiple dies stacked one above the other

Chip scale package (Intel makes NAND memory)
Thinning of the wafer is required
*CSP:

Chip Scale Package

FLIP CHIP ASSEMBLY

Application of solder paste

Application of flux
Substrate

LSCs

C4 bumps

Die Placement

Capacitor
Die
Substrate

Soldered
joint

Flux evaporation, reflow

and joint formation

FLI joint
formation
Die
Substrate

Capacitors
(land side)

STACKED CSP ASSEMBLY

EPOXY (or FILM)

Backgrinding/cutting wafer into individual dies

SUBSTRATE

DIE

EPOXY DISPENSE
(or FILM)

Repeat the process for multiple

dies if necessary

Overmolding

Ball attach and reflow

DIE BONDING

GOLD
WIRE

DFM: Cu-MIGRATION
Per JEDEC standards, all packages must meet certain accelerated test
requirements such as high temperature and moisture under biased condition,
temperature cycling

After several
hours at high Temp
and moisture

Dendrite

Example of dendrite formation: Cu in acidic

solution at 0.6V (Gabrielli et al, J Electrochem
Soc, 154, H393 (2007)

Copper
line

Polymeric matrix of the substrate

or dielectric of the silicon
+

H2O H+ + OHAnode: Cu Cu+ + e2Cu++ 2OH- --> Cu2O + H2O

Movement of Cu+ ion to cathode under electric field
Cathode: Cu+ + e- Cu
2H+ + 2e- H2

Cu Migration Video

Intels Microprocessor

SUMMARY

Interconnect
6 Dielectric
Deposition Steps
12 Dielectric
Etch Steps
6 Ta/Cu PVD Steps
6 Cu Plating Steps
6 Cu CMP Steps
12 Wet Clean Steps

Ion Implantation

Courtesy of Intel

Silicon Wafer

Both interconnect and transistor are important

Metal
Dielectric
Copper
Deposition
Copper
Dielectric
W-CMP
Deposition
Deposition
PVD
+ ECP
CMP
Etch
Deposition
PVD + WCVD
Transistor
Poly
Silicon
Gate
Oxide
Poly
Silicon
Shallow
Trench
Shallow
Trench
Deposition
Growth
16
Thermal
Steps
Gate
Etch
Isolation
CMP
Dielectric
Trench
Isolation
11Shallow
Implant
Steps
Deposition
Isolation
Etch
5 Etch
Steps
2 CMP Steps
38 Wet Clean Steps