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Module 11
Overview
Metastability
Constraints
Clock Skew
Core Generator
Metastability
Flip-flops may go metastable if input signals do not meet
setup and hold specifications relative to clock signal
CLK
D
Q
Rules:
Input only drives one FF
Add 2-FF synchronizer
IF clkEVENT AND clk = 1 THEN
input_d <= input;
input_dd <= input_d;
Jim Duckworth, WPI
clk = 1 THEN
input;
input_d;
input_dd;
input_dd & NOT input_ddd;
always @ (reset,
begin
input_d
<=
input_dd
<=
input_ddd
<=
input_pulse <=
clk)
input;
input_d;
input_dd;
input_dd & ~input_ddd;
Timing Constraints
======================================================
Clock Skew
The difference between the time a clock signal arrives at
the source flip-flop in a path and the time it arrives at the
destination flip-flop.
Misalignment of clock edges
Degrades (reduces) time for flip-flop to flip-flop timing
10
11
12
13
14
15
ADC
SRAM
FIFO
400 MHz
200 MHz
16
17
FIFO Generator
18
Synthesis
VHDL forand
Modeling
Timing - Module 10
11
Select Options (1 of 6)
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20
21
22
23
24
Synthesis
VHDL forand
Modeling
Timing - Module 10
11
25
26
27
FIFO Simulation
28