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Reprinted from The MathWorks News & Notes | January 2006 | www.mathworks.com
equalization, carrier recovery, and slicing),
while the rest of the receiver performs Viterbi
and RS decoding and frame alignment and
includes a controller to resolve QAM phase
ambiguity. The Frame Aligner subsystem
converts serial data at the Viterbi decoder’s
output into bytes that feed the RS decoder.
Using pattern-matching circuitry that detects
the ASM bit pattern, the Frame Aligner sub-
system aligns the serial data so that the first
bit of the received ASM becomes the MSB of
the corresponding byte output. The match
Figure 2. QAM system transmitter performing FEC and symbol mapping. signal is asserted when the last byte of the
ASM is presented on the dout port.
Figure 4 shows the Controller subsystem,
Transmitter Design symbol interference, Doppler shifting, and which performs periodic 90-degree phase
Figure 2 shows the contents of the transmitter additive white Gaussian noise. The model adjustments of the demapped symbols by
subsystem, which processes a stream of 8-bit includes a slider bar that lets you adjust the incrementing the quad_select input of
symbols generated by a sinusoidal test source Doppler shift as the simulation runs to test the QAM Demodulator subsystem until the
in the top-level model. The transmitter sub- the receiver’s robustness. Frame Aligner subsystem detects the ASM
system performs the following operations: Xilinx gateway input/output blocks repre- pattern. Once synchronization is achieved,
■R eed-Solomon (RS) encoding—Processes senting the pins to the FPGA handle the the controller asserts the start signal for the
blocks of 239 symbols through an RS en- interface between the transmitter/receiver RS decoder block. After the entire 255-byte
coder, which appends 16 parity symbols (fixed point) and the channel model (dou- code block is received, the controller en-
to each input block to form 255-symbol ble precision floating point). Within these sures that the four ASM bytes are success-
code blocks. blocks, you can specify data type, format, fully detected in the frame aligner.
■S ynchronization marker (ASM)—Prepends quantization, overflow, and sample period.
a 4-byte ASM to each code block (for non- Automatic Hardware
turbo-coded data, the ASM is 1ACFFC1D Receiver Design Generation
in hexadecimal format). The output block Figure 3 shows the QAM Receiver subsystem. You double-click the System Generator token
size is 259 bytes. The Attach ASM subsys- Because our design is destined for an FPGA, in the top level of the model to open the hard-
tem also generates a start signal for the it comprises blocks from the System Genera- ware generation GUI that lets you specify
RS encoder, indicating the beginning of a tor Blockset. The QAM Demodulator subsys- FPGA family and device, netlist type, Simu-
new code block. tem performs QAM demodulation (adaptive link clock rate, and whether a testbench
■C onvolutional encoding—Converts the
symbols into a bit stream and processes
it through a convolutional encoder. The
Convolutional Encoder block also de-
multiplexes its encoded bitstream into in-
phase and quadrature (I and Q) channels.
■ I/Q conversion—Serial to parallel blocks
convert the I/Q bitstreams into two 2-bit
word streams used to form 16-QAM sym-
bols in the top-level model (one 2-bit word
per I/Q rail).
Channel Modeling
The modulated data is passed through a
channel model that uses Simulink blocks
(see Figure 1) to simulate the effects of inter- Figure 3. QAM system receiver with demodulation, frame alignment, and error correction.
Reprinted from The MathWorks News & Notes | January 2006 | www.mathworks.com
Blockset provides RS encoding and convo-
lutional encoding blocks that could replace
the corresponding blocks shown in Figure
2. Each approach has its strengths. In a typ-
ical simulation, blocks from the Simulink
family of products tend to run faster than
their System Generator counterparts, but
they generally provide no direct path to an
FPGA implementation. System Generator
blocks, on the other hand, are designed to
provide such an implementation path and
also provide a way to accelerate simula-
tions through the HIL capability. Simulink
Figure 4. A Xilinx Picoblaze 8-bit microcontroller-based control circuit. provides a flexible design environment in
which you can easily combine blocks de-
pending on where you are in the design
is needed (Figure 5). Clicking Generate pro- process and which design sections are des-
duces a cycle- and bit-accurate HDL netlist tined for an FPGA.
that can be synthesized and placed-and- The Simulink family of products and
routed using Xilinx ISE Foundation FPGA Xilinx System Generator are widely used
implementation software. System Generator together to develop FPGA-based signal
also provides a path to automatically generate processing algorithms for digital com-
an FPGA bit stream (program the FPGA) on munications, video/imaging systems, and
the target development board. aerospace/defense systems. With these
tools, system engineers and DSP engineers
Co-Simulation and Hardware can rapidly develop algorithms within the
Verification
Simulink environment and automatically
Selecting compilation targets from the
implement their designs on FPGAs. More-
Hardware Co-Simulation menu lets you
over, System Generator’s HIL capability al-
incorporate an implemented design (run-
lows engineers to co-simulate their FPGA
ning on the FPGA) directly within a Simu- Figure 5. System Generator automatic implementations directly within Simulink.
link simulation. This co-simulation capabil- hardware generation GUI.
For the simulation of millions of samples
ity automatically creates bit streams to and
through complex designs, this capability
from the FPGA and associates them with
greatly accelerates run speeds and can thus
the corresponding System Generator blocks As an alternative hardware scheme, you can save months of development time. 7
in the Simulink model. Thus, results for the export both the testbench and golden data
compiled System Generator blocks are com- to hardware description language (HDL)
puted on the FPGA rather than being emu- simulation tools that FPGA designers Resources
lated in software. Consequently, you can test easily understand.
the design in actual hardware and accelerate 4 Model-Based Design for Signal Processing
the execution of System Generator blocks Simulation Acceleration and Communication Systems
www.mathworks.com/res/dsp_comm
by a factor of 10–100, typically, saving con- with Simulink
siderable development and debugging time. While most of the blocks in this trans 4 Webinar: Design & Implement Software—
Defined Radio Systems with Simulink
Using either the JTAG interface with Paral- mitter subsystem come from the System & Xilinx System Generator
lel Cable IV or specialized interfaces, you Generator Blockset, you can use similar www.mathworks.com/res/sdrwebinar
can also extend System Generator’s HIL blocks from the Simulink family of prod- 4 RTC Magazine “System-Level Design
ucts. For example, the Communications Using FPGAs and DSPs: An Example
capability to other FPGA platforms. Showing Software-Defined Radio”
www.mathworks.com/res/xilinx_sdr
[1] Consultative Committee for Space Data Systems, “CCSDS 101.0-B-5 Recommendation 4 Xilinx, Inc. www.xilinx.com
for Space Data System Standards – Telemetry Channel Coding,” June 2001.
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