The Pentium Pro was introduced in 1995 as the successor to the Pentium.

It introduced
several unique architectural features that had never been seen in a PC processor before.
The Pentium Pro was the first mainstream CPU to radically change how it executes
instructions, by translating them into RISC-like microinstructions and executing these on
a highly advanced internal core. (The Nexgen Nx586 processor was actually the first x86
CPU to use this design, but this chip was used in very few systems.)

The Pentium Pro achieves performance approximately 50% higher than a Pentium of the
same clock speed. In addition to its new way of processing instructions, the Pentium Pro
incorporates several other technical advances that contribute to this increased
performance:

• Superpipelining: The Pentium Pro dramatically increases the number of execution

steps, to 14, from the Pentium's 5.
• Integrated Level 2 Cache: The Pentium Pro features a dramatically higher-
performance secondary cache compared to all earlier processors. Instead of using
motherboard-based cache running at the speed of the memory bus, it uses
an integrated level 2 cache with its own bus, running at full processor speed,
typically three times the speed that the cache runs at on the Pentium. The Pentium
Pro's cache is also non-blocking, which allows the processor to continue without
waiting on a cache miss.
• 32-Bit Optimization: The Pentium Pro is optimized for running 32-bit code
(which most modern operating systems and applications use) and so gives a
greater performance improvement over the Pentium when using the latest
software.
• Wider Address Bus: The address bus on the Pentium Pro is widened to 36 bits,
giving it a maximum addressability of 64 GB of memory.
• Greater Multiprocessing: Quad processor configurations are supported with the
Pentium Pro compared to only dual with the Pentium.
• Out of Order Completion: Instructions flowing down the execution pipelines can
complete out of order.
• Superior Branch Prediction Unit: The branch target buffer is double the size of the
Pentium's and its accuracy is increased.
• Register Renaming: This feature improves parallel performance of the pipelines.
• Speculative Execution: The Pro uses speculative execution to reduce pipeline stall
time in its RISC core.

For a few reasons, the Pentium Pro is still, despite its age, an ideal choice for servers.
First, it is a fast chip in general. Second, its integrated level 2 cache makes it ideal for
multiprocessing; instead of having a single motherboard-based level 2 cache that all the
processors must share, each has its own. Third, the Pentium Pro has chipsets available for
it that are designed for high-end server use, moreso than the Pentium.

The most widely-publicized advanced feature of the Pentium Pro is of course the
integrated level 2 cache. The Pentium Pro is shipped in a special dual cavity SPGA
package that includes the chip itself and the integrated cache. It goes into a special Socket
8 interface unique to the Pentium Pro. One disadvantage of this arrangement is that the
cache is not upgradable without also replacing the processor.

The integrated-cache design has been both a blessing and a curse for Intel. The blessing is
that it greatly improves the performance of the chip. The curse is that it has been very
difficult for Intel to manufacture the Pentium Pro at the volumes and cost levels
necessary for it to become a mainstream processor. There are two main reasons for this.
First, the cache itself is highly miniaturized and therefore much more expensive to
produce than the typical SRAM chips used on a Pentium motherboard for level 2 cache.
Second, some problems with the cache are not found until after it has been mated with
the processor and installed in their shared package; when this happens the whole package
(including the processor) must be thrown away, reducing yields and increasing costs. Due
to the problems with its design, Intel has abandoned the integrated-cache concept and it is
unlikely that any future PC processors will use it in the same way that the Pentium Pro
does.

The Pentium Pro is usually found in either 180 MHz or 200 MHz versions. Older
Pentium Pros ran at 150 and 166 MHz; these are far less common and the 166 MHz chip
is in particular rarely seen. The 150 and 180 chips ship only with 256 KB level 2 cache,
while the 200 is available with 256 KB, 512 KB or 1 MB of level 2 cache. The cost of the
200 MHz chip with 512 KB or 1 MB of cache is very high due to production costs and
demand. The 166 MHz chip is unusual in that it was available with 512 KB of cache
only.

Despite being almost two years old, the Pentium Pro processor is still commonly used in
high-end systems, although the Pentium II is now starting to take some of this market.
Until Intel comes out with a proper Pentium II chipset for servers, demand for the 200
MHz version (especially with 512 KB or 1 MB of cache) will continue to be high. In
addition, multiple-Pentium-Pro servers are quite common and provide good performance
at a reasonable price. The Pentium Pro often competes against non-Intel server processors
such as DEC's Alpha.

The Pentium II builds on the design of thePentium Pro, but adds an additional 2
million transistors to bring the total up to 7.5 million. Current versions of the chip run at
speeds of 233, 266, 300, and 333MHz. In addition, the Pentium II features the following:
 ASingled Edge Contact (SEC)cartridge that fits into Slot 1
 Dual Independent Bus (DIB)architecture
 512K L2 cache
 32K L1 cache
 MMX support

Product Highlights

Available in speeds from 233 MHz up to 450 MHz.

 Utilizes Intel’s 0.25 micron manufacturing process for increased processor core frequencies
and reduced power consumption.

Includes MMX media enhancement technology.

The Pentium® II processor at 450 MHz delivers 32% more integer performance (as
measured by SPECint95), 30% more multimedia performance (as measured by Norton
Media Benchmark), and 35% more floating point performance (as measured by SPECfp95)
than the 333 MHz Pentium® II processor.

Dual Independent Bus (DIB) architecture increases bandwidth and performance over single-
bus processors.

450, 400, and 350 MHz versions improve system bandwidth and performance by increasing
the system bus speed from 66 MHz to 100 MHz. The Intel® 440BX AGP set enables the 100
MHz system bus to increase peak processor data transfers to the rest of the system by
50%.

Single Edge Contact (SEC) cartridge packaging technology delivers high-performance

processing and bus technology to mainstream systems.

32K (16K/16K) non-blocking, level-one cache provides fast access to heavily used data.

512K unified, non-blocking, level-two cache.

450, 400, and 350 MHz versions support memory cacheability for up to 4GB of addressable
memory space.

Enables scalable systems to be expanded to two processors and 64GB of physical memory.

Includes data integrity and reliability features such as Error Correction Code (ECC), Fault
Analysis, Recovery, and Functional Redundancy Checking for both system and L2 cache
buses.

P2
Other Significant Features

SEC cartridge packaging, developed by Intel, enables high-volume availability, improved

handling protection, and a common form factor for future high-performance processors.

High-performance Dual Independent Bus (DIB) architecture (system bus and cache bus) for
high bandwidth, performance and scalability with future system technologies.

The system bus supports multiple outstanding transactions to increase bandwidth

availability. It also provides “glueless” support for up to two processors. This enables low-
cost, two-way symmetric multiprocessing, providing a significant performance boost for
multitasking operating systems and multi-threaded applications.

A 512K unified, non-blocking, level-two cache that improves performance by reducing the
average memory access time and providing fast access to recently used instructions and
data. Performance is enhanced through a dedicated 64-bit cache bus. The speed of the
level-two cache scales with the processor core frequency. This processor also incorporates
separate 16K level-one caches, one for instructions and one for data.
 450, 400, and 350 MHz supports memory cacheability for up to 4GB of addressable memory
space.

Available with ECC (Error Correction Code) functionality on the level-two cache bus for
applications where data intensity and reliability are essential.

A pipelined Floating-Point Unit (FPU) for supporting the 32-bit and 64-bit formats specified
in IEEE standard 754, as well as an 80-bit format.

Parity-protected address/request and response system bus signals with a retry mechanism
for high data integrity and reliability.

Pentium III microprocessor family was an evolutionary upgrade from Pentium II. The
first Pentium III core, Katmai, featured SSE instruction set, which allowed SSE-enabled
applications to process up to four single-precision floating point numbers at once. Other
Pentium 3 cores added other features, like 256 and 512 KB on-die L2 cache memory and
smaller package size. During its lifetime, the core of Pentium III microprocessors was shrunk
twice - from 0.25 micron to 0.18 micron, and then to 0.13 micron.
Like the previous generation of x86 processors, the Pentium III family consists of a few sub-
families targeting different segments of computer market:

o Pentium III Xeon - high performance version.

o Pentium III desktop processors - desktop computers.
o Desktop Celeron - low-cost version.
o Mobile Pentium III and mobile Pentium III-M - mobile versions of the Pentium III
processor.
o Mobile Celeron - mobile version of Intel Celeron processor.

Pentium xeon
f I want to put it simply, I could say that the new architecture of Xeon is not that much of a big
deal. The CPU core is still the well known 'Deschutes' core, used in the Pentium II as well as in the
Celeron processor. The big trick is the Xeon's L2 cache. Whilst Celeron has to live completely
without L2 cache until September and whilst the Pentium II offers only 512 kB L2 cache running at
half the core clock speed, the Xeon is supplied with 512 kB, 1 MB and soon 2 MB L2 cache running
at the same clock as the Deschutes core. It sounds simple, but it took a lot of work designing L2
cache chips which would run at 400 MHz and above. Intel is producing these chips by itself,
different to the L2 cache chips found in the Pentium II. The Cache chips are called 'CSRAM' for
'custom' static RAM, where custom only means that Intel cannot buy it from a SRAM manufacturer.
The chips come in sizes of 512 kB each, so that a Xeon with 512 kB includes one, the 1 MB version
two and the 2 MB version will include 4 of those chips. These L2 cache chips are in a package that
looks identical to the Pentium II core package, which should show you how thermally sensitive
those chips are. Cooling is required for the L2 cache chips, which is why the cartridge of the
Pentium II Xeon got extremely huge.
So the faster L2 cache is the main reason why under certain conditions the Pentium II Xeon will
perform faster than the Pentium II. However, there are quite a few more special things about Xeon.
First of all it enables all the features of the good old Pentium Pro, including support for quad
CPU systems and even 8 CPUs in one system in combination with 450NX and a
special cluster controller. The cacheable memory limit lies not only by 4 GB, but it can address and
cache up to 64 GB memory by using 36-bit memory address bus and the new PSE36 mode. The
Xeon is of course running at 100 MHz front side bus, enabling a higher memory bandwidth of up to
800 MB/s peak. ECC, the error checking and correction is definitely required in servers and often in
workstations too, so the Xeon offers ECC for main memory via the chipsets 440GX and 450NX as
well as using an ECC L2 cache RAM. For manageability the Xeon has a thermal sensor, responsible
for keeping it at a save temperature, as known from the Pentium Pro already. Completely new and
very pleasing is the new PIROM in the Xeon, standing for 'Processor Information ROM', which
includes "robust addressing headers to allow for flexible programming and forward compatibility,
core and L2 cache electrical specifications, processor part and S-spec numbers, and a unique
electronic signature", so that counterfeiting of the Xeon is hopefully impossible now, but possibly
making overclocking impossible too. However, overclocking is light years from common practice in
servers or workstations anyhow. System vendors can program a special EEPROM chip within the
Xeon cartridge as well, called 'scratch EEPROM. This EEPROM is supposed to host information like
"system specifications, inventory and service tracking, installation defaults, environment
monitoring, and usage data. Its contents can be write-protected by the system, as well."