Assignment: Parasitic current in bulk driven

MOSFET.
Q1) Issues with parasitic transistors in MOSFET.
Ans:
A standard CMOS process has unintentional lateral and vertical BJTs (device) which
can be schematically shown by a cross-section of PMOS transistor (n-well
technology), in the figure below.
(B)

(C
1)

(E1) Vs>
0V

(C
2)

(Connected to
ground)
E1

T1
IC1

T2
IC2

T1,
T2
C1
IC1

IC2
C2

The vertical transistor (PNP) is formed by n-well as base (B) and source/drain as
emitter (E1) and other drain/source as collector (C1). The lateral transistor (PNP) is
formed by n-well as base (B), source/drain as emitter and p-substrate as collector
(C2).
1) The collector current through vertical bipolar transistors (T2) is a strong
function base width (n-well depth) and forward bias voltage applied at BE
junction, and doping levels. Since the collector terminal is connected to
ground hence this bipolar transistor (T2) mostly remains biased in forward
active mode. The effective emitter base junction cross-sectional area is also
large for T2 hence this device can conduct relatively large current. Since the
collector terminal of T2 is connected to ground, the composite transistor can
only be operated in common emitter configuration which is not beneficial for
high gain applications.
2) A) In the lateral bipolar transistor (T1) minority carriers are injected from base
gets divided into current through lateral channel (underneath the channel)
and other fraction through p-substrate (collector of T2). The collector of T1

(lateral PNP bipolar transistor) is free terminal, unlike the vertical PNP bipolar
transistor. The collector current density through lateral PNP bipolar transistor
can be expressed as fraction L of emitter current density and rest of ( 1- L )
conducts through vertical PNP collector [3]. Hence in-order to increase
collector current density through lateral PNP, fraction L which is proportional
to sidewall-to-area ratio of emitter diffusion can be increased, by achieving
minimum transistor size.
B) For p-MOS, gate voltage larger than threshold voltage, induces an
inversion channel which short circuits the lateral PNP bipolar transistors
collector-emitter node. Hence if p-MOS gate is biased in deep sub-threshold
then the depletion region under the Si-SiO 2 interface shields majority carriers
in base from recombination into base hence high emitter injection efficiency
can be achieved [3]. But in sub-threshold operation, for fixed gate voltage
base-emitter might reverse bias.
Hence it is required to achieve high collector current through lateral PNP
transistor with respect to collector current through vertical PNP transistor for
operating the composite transistor as an amplifier. Such techniques are cited
in few technical papers (applications related to emitter follower in SRAM,
band-gap voltage reference etc.) but ratio of collector currents through lateral
and vertical bipolar transistors are poorly controlled for relatively high gain
amplifier applications.

Q2) Analysis of ICMR for following architecture.

Figure2: Transistor-level implementation of the bulk-driven input stage [2].

This circuit (Figure2) tries to achieve high gain, rail to rail input common mode
range by adopting bulk-driven input technique. This circuit ensures that the p-MOS
differential input pair have least parasitic current due to lateral-PNP and vertical-PNP
bipolar transistors since it is difficult to control.
The basic configuration of differential p-MOS pair for analyzing input common mode
range is shown below

Itail

M1
D1

M2
D2

Idea here is not to allow the p-n junctions (Source-Bulk and Drain-Bulk) to get
forward biased. Otherwise current through collector (D1) cannot be controlled easily
and high current gain may not be possible for large channel length and V SG>|VT|.
VCM-min= VSG-VF where VSG should be such that: The above tail current source is in
saturation; Source-bulk p-n junction is reverse biased (V F is the forward bias
voltage of the source-bulk p-n junction); PMOS (M1) is in saturation. This ensures
that at low ICMR the M1 or M2 transistors have least parasitic current. R Load must be
chosen such that at any input common mode range, drain-bulk junction (collectorbase) be reverse biased so that parasitic current is negligible [2].
VCM-max=VDD-(VDS-sat|min) Here (VDS-sat|min) is the minimum source-drain voltage required
to keep the Itail current source in saturation. Also it can be noticed that source-bulk
p-n junction of PMOS can get forward biased, but not enough to conduct large
parasitic current.
References:
[1] Carrillo, J.M. Torelli, G.Perez-Aloe, R. Duque-Carrillo, J.F., "1-V Rail-to-Rail CMOS
OpAmp With Improved Bulk-Driven Input Stage," IEEE Journal of Solid-State Circuits,
, vol.42, no.3, pp.508-517, March 2007
[2] Blalock, B.J. Allen, P.E. Rincon-Mora, G., "Designing 1-V op amps using standard
digital CMOS technology," IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol.45, no.7, pp.769-780, Jul 1998
[3] Pan, T.-W. Abidi, A.A., "A 50 dB variable gain amplifier using parasitic bipolar
transistors in CMOS," IEEE Journal of Solid-State Circuits, vol.24, no.4, pp.951-961,
Aug 1989
[4]Gray, Meyer Analysis and Design of Analog Integrated Circuits, 5th Edition
chapter-2.
[5] Laker and Sansen Design of Analog integrated circuits and systems