Sunteți pe pagina 1din 4

DIGITAL ELECTRONICS (331102)

PRACTICAL: 12

TO STUDY R – S FLIP FLOP


1.0 AIM :

 To study R – S flip flop

2.0 PRIOR CONCEPTS :

 Knowledge of working of AND, OR, NOT gate.

 Knowledge of working of NAND and Ex - OR gates.

 Difference between sequential circuit and combinational circuit.

3.0 INTRODUCTION

 An SR Flip-Flop can be considered as a basic one-bit memory device that has


two inputs, one which will "SET" the device and another which will "RESET" the
device back to its original state and an output Q that will be either at a logic level
"1" or logic "0" depending upon this Set/Reset condition.

 A basic NAND Gate SR flip flop circuit provides feedback from its outputs to its
inputs and is commonly used in memory circuits to store data bits.

 The term "Flip-flop" relates to the actual operation of the device, as it can be
"Flipped" into one logic state or "Flopped" back into another.

4.0 R– S (RESET SET) LATCH :

 The simplest way to make any basic one-bit Set/Reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND Gates to form a Set-Reset
Bistable or a SR NAND Gate Latch, so that there is feedback from each output to
one of the other NAND Gate inputs.

48 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)

 This device consists of two inputs, one called the Reset, R and the other called
the Set, S with two corresponding outputs Q and its inverse or complement Q as
shown below.

 This device consists of two inputs, one called the Reset, R and the other called
the Set, S with two corresponding outputs Q and its inverse or complement Q as
shown below.

 Working of R – S flip flop with NAND gate :

o When S = 0 and R = 0 : If we assume Q = 1 and Q' = 0 as initial


condition, then output Q after input is applied would be Q = (R + Q')' = 1
and Q' = (S + Q)' = 0. Assuming Q = 0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 0 and Q' =
(S + Q)' = 1. So it is clear that when both S and R inputs are LOW, the
output is retained as before the application of inputs. (i.e. there is no state
change).

o When S = 1 and R = 0 : If we assume Q = 1 and Q' = 0 as initial


condition, then output Q after input is applied would be Q = (R + Q')' = 1
and Q' = (S + Q)' = 0. Assuming Q = 0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 1 and Q' =
(S + Q)' = 0. So in simple words when S is HIGH and R is LOW, output Q
is HIGH.

o When S = 0 and R = 1 : If we assume Q = 1 and Q' = 0 as initial


condition, then output Q after input is applied would be Q = (R + Q')' = 0
and Q' = (S + Q)' = 1. Assuming Q = 0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 0 and Q' =
(S + Q)' = 1. So in simple words when S is LOW and R is HIGH, output Q
is LOW.

o When S = 1 and R =1 : No matter what state Q and Q' are in,


application of 1 at input of NOR gate always results in 0 at output of NOR
gate, which results in both Q and Q' set to LOW (i.e. Q = Q'). LOW in both
the outputs basically is wrong, so this case is invalid.

 Same circuit can be design using NOR gate. Its logic diagram and the excitation
diagram can be as shown :

S – R Flip Flop
using NOR gate

49 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)

5.0 GATED OR CLOCKED SR FLIP-FLOP

 It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop


that only change state when certain conditions are met regardless of the
condition of either the Set or the Reset inputs.

 By connecting a 2-input NAND gate in series with each input terminal of the SR
Flip-flop a Gated SR Flip-flop can be created.

 This extra conditional input is called an "Enable" input and is given the prefix of
"EN" as shown below.

 This extra conditional input


is called an "Enable" input and is
given the prefix of "EN" as shown
below.

 When the Enable input "EN"


is at logic level "0", the outputs of the two AND gates are also at logic level "0",
(AND Gate principles) regardless of the condition of the two inputs S and R,
latching the two outputs Qand Q into their last known state.

 When the enable input "EN" changes to logic level "1" the circuit responds as a
normal SR bistable flip-flop with the two AND gates becoming transparent to the
Set and Reset signals.

 This enable input can also be connected to a clock timing signal adding clock
synchronisation to the flip-flop creating what is sometimes called a "Clocked SR
Flip-flop".

 So a Gated Bistable SR Flip-flop operates as a standard Bistable Latch but the


outputs are only activated when a logic "1" is applied to its EN input and
deactivated by a logic "0".

6.0 SETUP AND HOLD TIME :


 For synchronous flip-flops, we have special requirements for the inputs with
respect to clock signal input. They are :

o Setup Time: Minimum time period during which data must be stable
before the clock makes a valid transition. For example, for a positive edge
triggered flip-flop, with a setup time of 2 ns, Input Data (i.e. R and S in
the case of RS flip-flop) should be stable for at least 2 ns before clock
makes transition from 0 to 1.

o Hold Time: Minimum time period during which data must be stable after
the clock has made a valid transition. For example, for a positive edge
triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the
case of RS flip-flop) should be stable for at least 1 ns after clock has made
transition from 0 to 1.

50 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)

7.0 EXERCISE :

7.1 Why the flip flops are called as Bistable Devices?

Ans :

7.2 Describe the categories of Sequential circuits.

Ans :

7.3 What is Race condition?

Ans :

7.4 What is the requirement of Enable input in gated R – S flip flop.

Ans :

7.5 What are the demerits of R – S flip flop?


Ans :

8.0 ASSIGNMENT :

8.1 Discuss the working of R – S Flip Flop using NOR gate.


8.2 Discuss the working of Clocked R – S flip flop.
8.3 What is meant by SetUp time and Hold Time?

Grades for Exercise: .................................................

Grades for Assignment: .................................................

Signature of Lab Co-ordinators: .................................................

51 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

S-ar putea să vă placă și