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002
CIRCUITS AND
ELECTRONICS
Lecture 1
ADMINISTRIVIA
Homework exercises
Labs
Quizzes
Final exam
Lecture 1
Lecture 1
What is engineering?
Purposeful use of science
Lecture 1
12
0.1
0.2
0.3
0.4
6.002
+
-
Filters
Analog system
components:
Modulators,
oscillators,
RF amps,
power supplies 6.061
Digital abstraction
Combinational logic
Consider
Lecture 1
Continuity J =
t
Others
E =
0
Lecture 1
Integral form
B
E dl = t
q
J dS = t
q
E
dS
=
a?
F
You respond: a =
m
Done !! !
Lecture 1
F
a?
In doing so, you ignored
the objects shape
its temperature
its color
point of force application
Point-mass discretization
Lecture 1
discrete resistor
Lecture 1
10
A
B
Replace the bulb with a
discrete resistor
I
R
and
V
I=
R
In EE, we do things
the easy way
Lecture 1
11
A
+
V
and
I=
In EE, we do things
the easy way
I=
R
Lecture 1
12
Lecture 1
13
V
B
SB
black box
Although we will take the easy way
using lumped abstractions for the rest
of this course, we must make sure (at
least the first time) that our
abstraction is reasonable. In this case,
ensuring that
V I
are defined
for the element
6.002 Fall 2000
Lecture 1
14
I
SA
V
B
must be defined
for the element
SB
black box
Lecture 1
15
=
I out of S B
q
True only when
= 0 in the filament!
t
I into S A
J dS
SA
J dS
SB
q
J dS J dS = t
SA
SB
from ell
w
x
a
M
IA
IB
q
=0
I A = I B only if
t
So lets assume this
Lecture 1
16
see
A&L
B
=0
t
outside elements
So
VAB = AB E dl
Lecture 1
17
More in
Chapter 1
of A & L
B
= 0 outside
t
q
= 0 inside elements
t
bulb, wire, battery
Lecture 1
18
Demo
only for the
sorts of
questions we
as EEs would
like to ask!
Demo
Lecture 1
19
V
+
a
b
R1
R2
R3
R4
d
R5
Lecture 1
20
a
b
V
+
R1
R3
R4
R2
R5
c
B
under DMD
E dl = t
0
E dl + E dl + E dl = 0
ca
ab
bc
= 0
Lecture 1
21
Consider
I ca
S
a
I da
I ba
Lecture 1
22
I ca
S
a
I
da
I ba
q
S J dS = t
under LMD
0
I ca + I da + I ba = 0
Kirchhoffs Current Law (KCL):
The sum of the currents into a node is 0.
simply conservation of charge
Lecture 1
23
KVL:
j j = 0
loop
KCL:
jij = 0
node
Lecture 1
24
6.002
CIRCUITS AND
ELECTRONICS
Lecture 2
Review
Lumped Matter Discipline LMD:
B
=0
t
q
=0
t
Outside elements
Inside elements
wires resistors sources
Lecture 2
Review
Lecture 2
Review
Review
Maxwells equations simplify to
algebraic KVL and KCL under LMD!
KVL:
j j = 0
loop
KCL:
jij = 0
node
Lecture 2
Review
a
R1
R4
R3
R2
d
R5
DEMO
KVL
KCL
Lecture 2
lots of unknowns
lots of equations
lots of fun
solve
Lecture 2
Element Relationships
For R,
V = IR
R
+
V0
For current source, I = I 0
J
Io
3 lumped circuit elements
Lecture 2
1
+
0 = V0
R1
R3
+ 3
R2
R4
d
+
R5
c
The Demo Circuit
Lecture 2
Element e
Lecture 2
= i is positive
0 = V0
i0
L1
i4
i1 L 2
+
R1
4 R4
R3
b i3
d
+ 3
i2
i5
+
R2
5 R5
L3
c
The Demo Circuit
Lecture 2
L4
10
Analyze
0 5 ,0 5
1. Element relationships (v, i )
given v3 = i3 R3
v0 = V0
v4 = i4 R4
v1 = i1 R1
v5 = i5 R5
v2 = i2 R2
12 unknowns
6 equations
ugh @#!
6.002 Fall 2000
Lecture 2
11
A
B
R1
R2 R3
G1
G2
V1
V2
GN
R1 + R2 +
G1 + G2
1
Gi =
Ri
+ RN
+ GN
V1 + V2
+
I2
I1
RN
I1 + I 2
Lecture 2
12
I =?
Example
R1
V +
R3
R2
I
V +
R1
R2 R3
R2 + R3
V +
R = R1 +
R
R2 R3
R2 + R3
V
I=
R
6.002 Fall 2000
Lecture 2
13
Lecture 2
14
V0
Step 1
e2
R2
R5
+ V e1
0
R4
R1 R
3
I1
Step 2
Lecture 2
15
V0
R2
R4
e2
R5
+ V e1
0
R1 R
3
for
I1 convenience,
write
1
Gi =
Ri
KCL at e1
(e1 V0 )G1 + (e1 e2 )G3 + (e1 )G2 = 0
KCL at e2
(e2 e1 )G3 + (e2 V0 )G4 + (e2 )G5 I1 = 0
Step 3
Lecture 2
16
V0
e2
R2
R5
+ V e1
0
R4
R1 R
3
I1
Gi =
KCL at e1
(e1 V0 )G1 + (e1 e2 )G3 + (e1 )G2 = 0
1
Ri
KCL at l2
(e2 e1 )G3 + (e2 V0 )G4 + (e2 )G5 I1 = 0
move constant terms to RHS & collect unknowns
Lecture 2
Solve for es
Step 4
17
In matrix form:
G1 + G2 + G3
G3
G3
e1
G1V0
=
G V + I
G3 + G4 + G5 e2
4 0 1
conductivity
matrix
sources
unknown
node
voltages
Solve
G3
G3 + G4 + G5
G1V0
G3
G1 + G2 + G3 G4V0 + I1
e1
e =
(G1 + G2 + G3 )(G3 + G4 + G5 ) G3 2
2
)(
) ( )(
G +G +G G V + G G V + I
3
4
5 1 0
3 4 0 1
e =
1 G G +G G +G G +G G +G G +G G +G 2 +G G +G G
1 3
1 4
1 5
2 3
2 4
2 5
3
3 4
3 5
e2 =
(same denominator)
Lecture 2
18
Solve, given
G1
1
=
G5 8.2 K
G2
1
=
G4 3.9 K
1
G3 =
1.5 K
I1 = 0
)(
G G V + G +G +G G V + I
e = 3 10 1 2 3 40 1
2 G + G + G + G + G + G G 2
1 2 3
3 4 5 3
1
1
1
G +G +G =
+
+
=1
1
2
3 8.2 3.9 1.5
G3 + G4 + G5 =
)(
1
1
1
+
+
=1
1.5 3.9 8.2
1
1
1
+ 1
3.9 V
e2 = 8.2 1.5
0
1
1 2
1.5
e2 = 0.6V0
If V0 = 3V , then e2 = 1.8V0
6.002 Fall 2000
Lecture 2
19
6.002
CIRCUITS AND
ELECTRONICS
Lecture 3
Review
Circuit Analysis Methods
z KVL:
Vi = 0
loop
KCL:
Ii = 0
VI
node
Lecture 3
Linearity
R2
e
J
R1
Consider
e V e
+ I =0
R1
R2
Notice:
linear in e,V , I
No eV ,VI
terms
Lecture 3
Linearity
R1
Consider
+
R2
linear in e,V , I
V
+ I
R1
node
linear sum
voltages of sources
Lecture 3
Linearity
Write node equations -e V e
+ I =0
R1
R2
Rearrange -1
1
R + R e
1
2
conductance
matrix
G
or
e=
linear in e,V , I
V
+ I
R1
node
linear sum
voltages of sources
R2
RR
V+ 1 2 I
R1 + R2
R1 + R2
e = a1V1 + a2V2 + + b1 I1 + b2 I 2 +
Linear!
6.002 Fall 2000
Lecture 3
Linearity
Homogeneity
Superposition
Lecture 3
Linearity
Homogeneity
Superposition
Homogeneity
x1
x2 .
.
x1
x2 ..
.
Lecture 3
Linearity
Homogeneity
Superposition
Superposition
x1a
x2 a .
..
ya
x1b
x2 b .
..
yb
x1a + x1b
x2 a + x2 b .
..
y a + yb
Lecture 3
Linearity
Homogeneity
Superposition
0
V2
y1
y2
V1 + 0
0 + V2
y1 + y2
Lecture 3
Lecture 3
10
V =0 +
i
+
v
+
v
short
I =0
i
+
v
+
v
open
Lecture 3
11
R2
Lecture 3
R1
12
R1
I = 0 eV =
R2
I acting alone
V =0
sum
R1
R2
R2
V
R1 + R2
R1 R2
eI =
I
R1 + R2
superposition
R2
R1 R2
e = eV + eI =
V+
I
R1 + R2
R1 + R2
6.002 Fall 2000
Lecture 3
Voil !
13
Demo
salt
water
constant
+
output shows
superposition
sinusoid
Lecture 3
14
Consider
By superposition
v =
mVm + n I n + Ri
m
no
resistance
units
units
By setting
n I n = 0, mVm = 0,
i = 0
i = 0
+
v
-
y network
r
a
r
t
i
N
Arb
resistors
Vm
In
+
also
independent
of external
excitement &
behaves like
a resistor
All
n I n = 0,
mVm = 0
independent of external
excitation and behaves like a
voltage vTH
6.002 Fall 2000
Lecture 3
15
Or
v = vTH + RTH i
vTH
RTH
+ vTH
+
v
Lecture 3
16
Method 4:
The Thvenin Method
J
+
v
-
Thvenin equivalent
RTH
+ vTH
i
+
v
Lecture 3
17
Example:
+
V
R2
i1 R1
i1 R1
RTH
+
V
VTH
i1 =
+ I
V VTH
R1 + RTH
Lecture 3
18
VTH :
VTH = IR2
RTH :
RTH = R2
+
VTH
-
R2
+
RTH
-
R2
Lecture 3
Example:
19
Graphically,
v = vTH + RTH i
i
1
RTH
v
vTH
V
OC
I SC
Open circuit
(i 0)
v = vTH
Short circuit
(v 0)
vTH
i =
RTH
Lecture 3
VOC
I SC
20
in recitation,
see text
Method 5:
J
+
+
v
-
IN
RTH = RN
Norton
equivalent
IN =
Lecture 3
VTH
RTH
21
Summary
Discretize matter
LMD
Physics
LCA
EE
R, I, V
Linear networks
Next
Nonlinear analysis
Discretize voltage
Lecture 3
101100
22
6.002
CIRCUITS AND
ELECTRONICS
Lecture 4
Review
z Discretize matter by agreeing to
Lecture 4
Today
Discretize value
Digital abstraction
Lecture 4
R2
V1 +
V1
and V2
might represent the
outputs of two
sensors, for example.
V2
By superposition,
V0 =
R2
R1
V1 +
V2
R1 + R2
R1 + R2
If R1 = R 2 ,
V0 =
V1 + V2
2
Lecture 4
Noise Problem
t
add noise on
this wire
Receiver:
huh?
Lecture 4
Value Discretization
Restrict values to be one of two
HIGH
LOW
5V
0V
TRUE
FALSE
0 and 1
Lecture 4
Digital System
sender
noise
VN
VS
VR
VN = 0V
receiver
VS
VR
5V 0 1 0 HIGH
0 1 0
5V
2.5V
0V
LOW
0V
2.5V
With noise
VS
VN = 0.2V
0 1 0
5V
0 1 0
0.2V
2.5V
VS
2.5V
0V
6.002 Fall 2000
Lecture 4
Digital System
Lecture 4
Voltage Thresholds
and Logic Values
5V
sender
0
1
2.5V receiver
0
0V
Lecture 4
1
sender
3V
2V
VH
forbidden
region
receiver
VL
0V
0V
Lecture 4
5V
V
L
10
VH ?
V
0H
1
V
IH
sender
V
IL
receiver
0
V
0L
0V
Lecture 4
11
VH ?
V
0H
sender
Noise margins
V
IH
receiver
V
IL
V
0L
0V
1 noise margin: V
- V
0 noise margin:
Lecture 4
IH
V
IL
0H
V
0L
12
5V
V
0H
V
IH
V
IL
V
0L
0V
5V
V
0H
V
IH
V
IL
V
0L
0V
sender
receiver
Lecture 4
13
1,0
Lecture 4
14
X, Y, Z
are digital signals
0 , 1
Z = X Y
Boolean equation
X
Y
AND gate
0
1
0
1
0
0
0
1
Lecture 4
15
Combinational gate
abstraction
Adheres to static discipline
Outputs are a function of
inputs alone.
Lecture 4
16
Demo
Z
Noise
X
Y
Z = X Y
6.002 Fall 2000
Lecture 4
17
t
Y
t
Z
t
Z = X Y
6.002 Fall 2000
Lecture 4
18
In recitation
Another example of a gate
If (A is true) OR (B is true)
then C is true
else C is false
C = A + B
A
B
Boolean equation
OR
C
OR gate
More gates
B
B
Inverter
X
Y
Z
NAND
Z = X Y
Lecture 4
19
Boolean Identities
X
X
X
X
1 = X
0 = X
+ 1 = 1
+0 = X
1 = 0
0 = 1
AB + AC = A (B + C)
Digital Circuits
Implement:
B
C
output = A + B C
BC
output
Lecture 4
20
6.002
CIRCUITS AND
ELECTRONICS
Lecture 5
Review
The Digital Abstraction
z Discretize value 0, 1
z Static discipline
receiver
VIH
VIL
forbidden
region
Lecture 5
Review
Combinational gate abstraction
outputs function of input alone
satisfies static discipline
A
B
C
NAND
Lecture 5
A
0
0
1
1
B
0
1
0
1
C
1
1
1
0
For example:
a digital circuit
A
B
Demo
A B
D
C
D = (C (A B ))
3 gates here
Lecture 5
(li
taps
s)
e
h
c
t
i
ke sw
B
C
Lecture 5
OR gate
A
C
B
Lecture 5
Electrical Analogy
B
V +
Lecture 5
Electrical Analogy
equivalent ckt
in
control
C =0
in
out
in
out
C=1
3-Terminal device
if C = 0
else
out
Lecture 5
Consider
RL
VOUT
IN
+ VS
VS =
OUT
VS
RL
VOUT
C
VS
VOUT
C =0
VS
VOUT
C =1
Lecture 5
What about?
VS
VOUT
c1
c2
VS
VOUT
c1
c2
Lecture 5
c1 c2 VO
0 0 1
0 1 0
1 0 0
1 1 0
10
What about?
can also build compound gates
VS
D
A
D = (A B) + C
Lecture 5
11
drain
D
G
gate
S
source
G : control terminal
D, S : behave in a symmetric
manner (for our needs)
6.002 Fall 2000
Lecture 5
12
out k
k
c
e
Ch extboo l
the t s interna
for it ture.
iG
c
u
r
t
s
+
vGS
iDS
vDS
S
D
off
G
vGS < VT
G
vGS VT
D
iDS
on
S
VT 1V typically
Lecture 5
13
Demo
+
vDS
+
vGS
iDS
vGS VT
vGS < VT
iDS vs vDS
6.002 Fall 2000
Lecture 5
vDS
14
A MOSFET Inverter
VS = 5V
RL
vOUT
IN
Lecture 5
15
Example
vOUT
5V
vOUT
vIN
0V V
T =1V
5V
v IN
1:
0:
VOL = 0.5V
VIL = 0.9V
VOH = 4.5V
VIH = 4.1V
sender
5
4.5 V
OH
0.5
0
VOL
receiver
5
4.1
0.9
0
Our inverter satisfies this.
6.002 Fall 2000
Lecture 5
1
VIH
VIL
16
E.g.:
Does our inverter satisfy the static
discipline for these thresholds:
VOL = 0.2V
VIL = 0.5V
VOH = 4.8V
VIH = 4.5V
yes
x
VOL = 0.5V
VIL = 1.5V
VOH = 4.5V
VIH = 3.5V
Lecture 5
no
17
D
G
G
S
vGS < VT
RON
vGS VT S
e.g. RON = 5 K
Lecture 5
18
SR Model of MOSFET
D
D
G
G
S
vGS < VT
MOSFET
S model
iDS
vGS VT
RON
vGS VT S
MOSFET
SR model
vGS VT
iDS
vGS < VT
1
RON
vGS < VT
vDS
vDS
Lecture 5
19
vOUT
IN
+ VS
VS =
OUT
VS
RL
vOUT
C
VS
RL
vOUT
C VOUT
0 1
1 0
RON
C =0
VS
RL
C =1
vGS VT
vOUT
RON
Lecture 5
20
6.002
CIRCUITS AND
ELECTRONICS
Nonlinear Analysis
Lecture 6
Review
Discretize matter t LCA
m1 X KVL, KCL, i-v
m2 X Composition rules
m3 X Node method
m4 X Superposition
m5 X Thvenin, Norton
Lecture 6
any
circuit
linear
circuits
Review
Discretize value t Digital abstraction
X Subcircuits for given switch
setting are linear! So, all 5
methods (m1 m5) can be
applied
VS
VS
A =1
B =1
RL
RL
C
A
C
RON
RON
SR MOSFET Model
Lecture 6
Today
Nonlinear Analysis
X Analytical method
based on m1, m2, m3
X Graphical method
X Introduction to incremental analysis
Lecture 6
+
vD
-
Hypothetical
nonlinear
D
device
(Expo Dweeb )
iD
+ vD -
iD
iD
iD = aebvD
a
vD
0,0
Lecture 6
vD V
+ iD = 0
R
iD = aebvD
2 unknowns
1
2
2 equations
Lecture 6
iD = aebvD
a
vD
iD
V vD
1 iD =
R R
V
R
1
slope =
R
V
6.002 Fall 2000
Lecture 6
vD
V
1
R
~ 0 .4
a
called loadline
for reasons you
will see later
~ 0.5
e.g.
V =1
R =1
V
1
vD
vD = 0.5V
iD = 0.4 A
1
4
b =1
a=
Lecture 6
+
vD LED
light
intensity
I D iD
vI music signal
vI (t ) +
iR
vI (t )
iD (t )
light
AMP
iR I R
light intensity IR
in photoreceiver
LED: Light
Emitting
expoDweep
iR (t )
sound
nonlinear
linear
problem! will result in distortion
Lecture 6
Problem:
distortion
iD
iD
vD
vD = vI
t
vD
t
iD
vD
Lecture 6
10
iD
vD
vD
t
What do we do?
Zen is the answer
next lecture!
6.002 Fall 2000
Lecture 6
11
6.002
CIRCUITS AND
ELECTRONICS
Incremental Analysis
Lecture 7
Review
Nonlinear Analysis
X Analytical method
X Graphical method
Today
X Incremental analysis
Reading: Section 4.5
Lecture 7
+
vD LED
light
intensity
I D iD
vI music signal
vI (t ) +
iR
vI (t )
iD (t )
light
AMP
iR I R
light intensity IR
in photoreceiver
LED: Light
Emitting
expoDweep
iR (t )
sound
nonlinear
linear
problem! will result in distortion
Lecture 7
Problem:
distortion
iD
iD
vD
vD = vI
t
vD
t
iD
vD
Lecture 7
Insight:
iD
small region
looks linear
(about VD , ID)
ID
VD
vD
DC offset
or DC bias
Trick:
vI
vi (t ) +
VI
iD = I D + id
+
vD LED
vD = VD + vd
VI
Lecture 7
vi
5
Result
iD
id
ID
vD
VD
Lecture 7
vd
very small
Result
vD = vI
vd
vD
VD
iD
id
iD
~linear!
ID
Demo
6.002 Fall 2000
Lecture 7
iD = I D + id
total
DC
small
variable offset superimposed
signal
Lecture 7
We replaced
vD = VD + vD
large DC
vd
increment
about VD
iD = f (VD ) +
+
df (vD )
vD
dvD vD =VD
1 d 2 f (v D )
2! dvD 2 v
vD + "
D =VD
Lecture 7
iD f (VD ) +
constant
w.r.t. vD
d f (v D )
vD
d vD vD =VD
constant w.r.t. vD
slope at VD, ID
We can write
X : I D + iD f (VD ) +
d f (v D )
vD
d vD vD =VD
operating point
d f (v D )
iD =
vD
d vD vD =VD
constant w.r.t. vD
so, iD vD
6.002 Fall 2000
Lecture 7
By notation,
iD = id
v D = vd
10
In our example,
iD = a e
bv D
I D = a ebVD
operating point
aka bias pt.
aka DC offset
id = a ebVD b vd
id = I D b vd
constant
Lecture 7
small signal
behavior
linear!
11
Graphical interpretation
operating point
I D = a ebVD
id = I D b vd
A
slope at
VD, ID
iD
ID
id
VD
operating
point
vd
vD
we are
approximating
A with B
Lecture 7
12
graphically
mathematically
now, circuit
ID
+
LED VD
-
I D = a ebVD
behaves like:
id
R=
vi
+
vd
-
1
ID b
id
1
I Db
Linear!
Lecture 7
13
6.002
CIRCUITS AND
ELECTRONICS
Dependent Sources
and Amplifiers
Review
Today
Dependent sources
Amplifiers
Dependent sources
Seen previously
Resistor
Independent
Current source
+
i
+
i
R
v
I
v
i=
R
i=I
+
control
port
f ( vI )
vI
vO
output
port
2-port device
E.g., Voltage Controlled Current Source
Current at output port is a function of voltage
at the input port
6.002 Fall 2002: Lecture 8
Example 1: Find V
+
R V
independent
current
source
I = I0
V = I0R
voltage
controled
current
source
+
R V
K
I = f (V ) =
V
iI
+
f (vI ) =
K
vI
iO
+
vI
vO
+
R V
K
I = f (V ) =
V
e.g. K = 10-3 AmpVolt
R = 1k
K
V = IR = R
V
or V 2 = KR
or V = KR
= 10 3 10 3
= 1 Volt
RL
iIN
vI +
iD
vIN
vO
e.g.
VS +
iD = f (vIN )
iD = f (vIN )
K
2
= (vIN 1) for vIN 1
2
iD = 0
otherwise
Find vO as a function of vI .
vI +
iD
vIN
vO
iD = f (vIN )
e.g.
iD = f (vIN )
K
2
= (vIN 1) for vIN 1
2
iD = 0
otherwise
Find vO as a function of vI .
vO
K
2
iD = (vIN 1) for vIN 1
2
iD = 0
otherwise
Find vO as a function of vI .
vO
K
2
iD = (vIN 1) for vIN 1
2
iD = 0
otherwise
KVL
VS + iD RL + vO = 0
vO = VS iD RL
K
2
vO = VS (vI 1) RL
2
vO = VS
for vI 1
for vI < 1
10
Next, Amplifiers
11
Why amplify?
Signal amplification key to both analog
and digital processing.
Analog:
AMP
IN
Input
Port
OUT
Output
Port
12
Why amplify?
Amplification is key to noise tolerance
during communication
No amplification
useful
signal
1 mV
e
nois
10 mV
huh?
13
Try amplification
e
nois
AMP
not bad!
14
Why amplify?
Digital:
Valid region
5V
5V
VIH IN
VIL
0V
5V
OUT
Digital System
IN
5V
VOL
OUT
V OH
VIH
VIL
0V
0V
VOH
V OL
0V
15
Why amplify?
Digital:
VOH
VOL
VOH VOL
VIH VIL
16
iO
iI
+v
I
Amplifier
+ v Output
O port
POWER
IN
OUT
17
Remember?
VS
RL
vI
vI
vO
K
2
iD = (vIN 1) for vIN 1
2
iD = 0
otherwise
KVL
VS + iD RL + vO = 0
vO = VS iD RL
K
2
vO = VS (vI 1) RL
2
vO = VS
for vI 1
for vI < 1
18
vO
vO
>1
v I
6.002 Fall 2002: Lecture 8
vI
vI
amplification
19
Plot vO versus vI
vO = 10 5 (vI 1)
0.1 change
in vI
Demo
vI
vO
0.0
1.0
1.5
2.0
2.1
2.2
2.3
2.4
10.00
10.00
8.75
5.00
4.00
2.80
1.50
~ 0.00
1V change
in vO
Gain!
Measure vO .
20
One nit
vO
What
happens
here?
1
vI
Mathematically,
K
2
vO = VS RL (vI 1)
2
So
21
One nit
vO
K
2
vO = VS RL (vI 1)
2
What
happens
here?
vI
1
However, from
iD =
K
(vI 1)2
2
VS
for vI 1
RL
vO
VCCS
iD
22
vO
K
2
i.e. vO = VS RL (vI 1)
2
vI
23
K
2
iD = (vI 1)
2
will no longer be valid when vO 0 .
e.g. iD saturates (stops increasing)
and we observe:
Commonly
vO
vI
24
6.002
CIRCUITS AND
ELECTRONICS
MOSFET Amplifier
Large Signal Analysis
Lecture 9
Review
DS
b output
b port
a +
i = f (v )
Lecture 9
Amp review
VS
RL
vO
VCCS
vI
K
2
iD = (vI 1)
2
for vI 1V
= 0 otherwise
vO = VS iD RL
K
(vI 1)2
2
Lecture 9
B
i = f (v )
voltage controlled
current source
Lecture 9
D
G
vGS < VT
G
vGS VT
Lecture 9
Graphically
Demo
+
vGS
iDS
egio
n
iDS
vGS VT
vGS < VT
vGS < VT
vDS
S MODEL
vDS
SR MODEL
vDS = vGS VT
vGS 1
Saturation
region
vGS 2
vGS3
...
vGS VT
T ri o
de r
iDS
v+DS
iDS
Lecture 9
vDS
region
Graphically
+
vGS
iDS
iDS
egio
n
S MODEL
vDS
SR MODEL
vGS 2
vGS3
...
vGS < VT
Saturation
region
T ri o
de r
vGS VT
vDS
vDS = vGS VT
vGS 1
iDS
vGS VT
vGS < VT
v+DS
iDS
vGS < VT
Lecture 9
vDS
when
vDS vGS VT
Notice that
MOSFET
behaves like a
current source
7
vDS vGS VT
D
G
vGS < VT
S
G
S
vGS
G
VT
iDS = f (vGS )
K
2
= (vGS VT )
2
S
Lecture 9
when
vDS vGS VT
iDS
vGS VT
vGS < VT
vDS
S MODEL
for fun!
vGS < VT
Saturation
region
vGS 2
vGS3
...
vGS VT
T ri o
de r
egio
n
iDS
vDS = vGS VT
vGS 1
vDS
SR MODEL
for digital
designs
vGS < VT
vDS
SCS MODEL
for analog
designs
vDS vGS VT
vDS < vGS VT
Lecture 9
Back to Amplifier
VS
vI
AMP
vO
VS
RL
vI
D
S
vO
K
2
iDS = (vI VT )
2
in saturation
region
Lecture 9
10
MOSFET Amplifier
VS
RL
vI
D
S
vO
K
2
iDS = (vI VT )
2
in saturation
region
Lecture 9
at all times.
11
VS
RL
vO
G
vGS = vI
+
vI
iDS
Lecture 9
K
2
= (vI VT )
2
for vO vI VT
12
RL
vO
G
vGS = vI
+
vI
iDS =
K
(vI VT )2
2
for vO vI VT
Analytical method: vO vs vI
vO = VS iDS RL
B
K
2
or vO = VS (vI VT ) RL for vI VT
2
vO vI VT
vO = VS
vI < VT
(MOSFET turns off)
for
Lecture 9
13
Graphical method vO vs vI
K
2
From A : iDS = (vI VT ) ,
2
vO vI VT
2
for
2iDS
vO
K
K 2
iDS vO
2
B : iDS
VS v0
=
RL RL
Lecture 9
14
Graphical method vO vs vI
K 2
K
2
A : iDS = (vI VT ) , for iDS vO
2
2
VS vO
=
i
B : DS
RL RL
iDS
VS
RL
iDS
B
Lo
ad
K 2
vO
2
A
li n
e
vI
= vGS
VS
Constraints
6.002 Fall 2000
and
Lecture 9
vO
must be met
15
Graphical method vO vs vI
iDS
VS
RL
iDS
K 2
vO
2
A
vI
VI
I DS
VO
VS
vO
Lecture 9
16
vO versus vI
Lecture 9
17
vO
K
2
VS (vI VT ) RL
2
VS
VT
vO = vI VT
gets into
triode region
vI
Lecture 9
18
Our
Constraints
vI VT
iDS
vO vI VT
iDS
VS
RL
iDS
K 2
vO
2
K 2
vO
2
K
2
iDS = (vI VT )
2
vI
v
V
iDS = S O
RL RL
VS
?
6.002 Fall 2000
vO
vI = VT
vO = VS and iDS = 0
Lecture 9
19
iDS
iDS
K 2
vO
2
K
2
iDS = (vI VT )
2
vI
VS vO
iDS =
RL RL
vO
1 + 1 + 2 KRLVS
vI = VT +
KRL
1 + 1 + 2 KRLVS
vO =
KRL
VS vO
iDS =
RL RL
6.002 Fall 2000
Lecture 9
vI = VT
vO = VS and iDS = 0
20
vO versus vI
vO = VS
K
(vI VT )2 RL
2
vI : VT
to
1 + 1 + 2 KRLVS
VT +
KRL
vO : VS to
1 + 1 + 2 KRLVS
KRL
Lecture 9
21
6.002
CIRCUITS AND
ELECTRONICS
Lecture 10
Review
MOSFET amp
VS
RL
vO
vI
iDS
Lecture 10
vO vs vI
K
(vI 1)2 RL
valid for vI VT
and
vO vI VT
K 2
(same as iDS vO )
2
vO = VS
Lecture 10
V
S
v
O
5V
corresponding
interesting
region for vO
vO > vI VT
vO = vI VT
vO < vI VT
1V
vI
VT
1V
2V
interesting region
for vI . Saturation
discipline satisfied.
Lecture 10
But
VS
5V
vO
vO = vI VT
vO
1V
vI
VT
1V
Demo
vI
2V
Amplifies alright,
but distorts
vI
vO
Amp is nonlinear /
6.002 Fall 2000
Lecture 10
~ 5V VS
(VI , VO )
~ 1V
vI
VT
1V
~ 2V
2
K (vI VT )
vO = VS
RL
2
Amp all right, but nonlinear!
Hmmm So what about our linear amplifier ???
Insight:
But, observe vI vs vO about some
point (VI , VO) looks quite linear !
6.002 Fall 2000
Lecture 10
Trick
vO
vo
VO
vi
(VI ,VO )
looks
linear
VI
vI
Operate amp at VI , VO
DC bias (good choice: midpoint
of input operating range)
Lecture 10
Trick
vO
vo
VO
vi
(VI ,VO )
looks
linear
VI
vI
Operate amp at VI , VO
DC bias (good choice: midpoint
of input operating range)
Lecture 10
next
week
8
I Graphically
VS
RL
interesting
input signal
vI +
VI
+
vO
Lecture 10
Graphically
VS
RL
interesting
input signal
vO
vI +
VI
+
VS
vO
operating
point
VO
VI , VO
VT
vO = vI VT
vI
Lecture 10
VI
10
Notation
Input:
vI = VI + vi
total
DC small
variable bias signal (like vI)
bias voltage aka operating point voltage
Output: vO = VO + vo
Graphically,
vI
vO
vi
vo
VI
VO
Lecture 10
11
II Mathematically
( watch my fingers)
RL K
2
vO = VS
(vI VT ) VO = VS RL K (VI VT )2
substituting vI = VI + vi
vi << VI
RL K
vO = VS
2
( [VI + vi ] vT )2
RL K
2
( [VI VT ] + vi )2
= VS
RL K
[VI VT ]2 + 2 [VI vT ]vi + vi 2
= VS
2
RL K
VO + vo = VS
(VI VT )2 RL K (VI VT ) vi
2
From ,
vo = RL K (VI VT ) vi
gm
related to
Lecture 10
VI
12
Mathematically
vo = RL K (VI VT ) vi
gm
related to
VI
vo = g m RL vi
VI VT is constant. So,
vo = A vi
constant w.r.t. vi
Lecture 10
13
Another way
RL K
vO = VS
(vI VT )2
R K
2
L
v V
VS
I
T
2
d
vo =
dv
I
vi
v = V
I
I
slope at VI
vo = RL K (VI VT ) vi
g m = K (VI VT )
A = g m RL
amp gain
Lecture 10
14
iDS
load line
VO
vO
Lecture 10
15
6.002
CIRCUITS AND
ELECTRONICS
Lecture 11
Review:
small
signal
vOUT = f (vI )
d
f (vI )
vi
vout =
dv I
v I =VI
VS
vI = VI + vi
vi
VI
RL
vO = VO + vo
Lecture 11
Review:
I Graphical view
(using transfer function)
vO
behaves linear
for small
perturbations
vI
Lecture 11
Review:
II Mathematical view
K (vI VT )
vO = VS
RL
2
2
V K (v V )2 R
T
L
d S 2 I
vo =
dv I
vi
v I =VI
vo = K (VI VT ) RL vi
gm
related to VI
constant for fixed
DC bias
Lecture 11
i DS <
Demo
K 2
vO
2
V S vO
i
=
load line DS R R
L
L
input signal
response
VI
VO
1 + 1 + 2 KR LV S
v I = VT +
KR L
vO
v I = VT
g m RL VI
Lecture 11
vI +
VS
vOUT
K
2
iD = (vI VT )
2
Lecture 11
Lecture 11
MOSFET
large
signal
vGS
Small signal?
D
iDS =
K
(vGS VT )2
2
Lecture 11
MOSFET
large
signal
vGS
iDS =
Small signal:
K
2
iDS = (vGS VT )
2
ids =
vGS
K
(vGS VT )2
2
K (v V )2
v gs
T
2 GS
vGS =VGS
ids = K (VGS VT ) v gs
gm
small
signal
v gs
D
ids = K (VGS VT ) v gs
S
ids = g m v gs
Lecture 11
DC Supply VS
large
signal
iS
+ vS = VS
Small signal
VS
vs =
iS
is +
vs
vS = VS
is
iS = I S
vs = 0
DC source behaves
as short to small
signals.
Lecture 11
10
Similarly, R
large
signal
iR +
vR
R
v R = R iR
vr =
( RiR )
ir
iR iR = I R
vr = R ir
small
signal
ir +
vr
R
Lecture 11
11
Amplifier example:
Large signal
RL
vO
+ v
I
iDS
Small signal
+ vi
iDS
K
2
= (vI VT )
2
vO = VS
RL
vo
+ V
S
ids
ids = K (VI VT ) vi
K
(vI VT )2 RL
2
ids RL + vo = 0
vo = ids RL
vo = K (VI VT )RL vi
= g m RL vi
Lecture 11
12
" + VA
" + VOUT
+ VB
+"
"
+ va "
+ vout
+ vb + "
Lecture 11
13
6.002
CIRCUITS AND
ELECTRONICS
Capacitors
and First-Order Systems
Lecture 12
Motivation
Demo
5V
5V
5V
0V
5
A
0
5
B
0
5
Expected
Observed
C
0
Delay!
6.002 Fall 2000
Lecture 12
Reading:
Chapters 9 & 10
2
The Capacitor
D
n-channel MOSFET
symbol
G
S
drain
gate
m+
e+
t +
a+
l +
+
o
x
i
d
e
source
s
i
l n-channel
p
i MOSFET
n-channel c
o
n
n
D
G
CGS
Lecture 12
d
EA
d
obeys DMD!
total charge on
capacitor
= +q q = 0
C=
i
C
+
v
q = C v
coulombs farads volts
Lecture 12
q = C v
+
v
dq
i=
dt
d (Cv )
=
dt
dv
=C
dt
E = 1 Cv 2
Lecture 12
Analyzing an RC circuit
Thvenin Equivalent:
vI (t ) +
+
vC (t )
t t0
vC (t0 ) given
units
of time
6.002 Fall 2000
Lecture 12
Lets do an example:
+
v I (t )
vC (t )
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC
+ vC = VI
dt
Lecture 12
Example
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC
+ vC = VI
dt
vC (t ) = vCH (t ) + vCP (t )
total homogeneous
particular
Lecture 12
1 Particular solution
dvCP
+ vCP = VI
dt
RC
vCP = VI
RC
works
dVI
+ VI = VI
dt
0
In general, use trial and error.
Lecture 12
2 Homogeneous solution
dvCH
RC
+ vCH = 0
dt
assume solution
of this form. A,
s?
dA e st
RC
+ A e st = 0
dt
R CA s e st + A e st = 0
R C s +1 = 0
s=
or
1
RC
vCH = Ae
t
RC
RC
called time
constant
Lecture 12
10
3 Total solution
vC = vCP + vCH
vC = VI + A e
t
RC
Given,
vC = V0
so,
V0 = VI + A
or
A = V0 VI
thus
vC = VI + (V0 VI ) e
also
iC = C
t
RC
dvC
(V VI )
= 0
e
R
dt
Lecture 12
t
RC
11
vC = VI + (V0 VI ) e
t
RC
vC
VI
V0
0
RC
Lecture 12
12
Examples
vC
vC
5V
5V
5 + 5e
t
RC
5e
0V
VO = 0V
VI = 5V
5
0
t
RC
0V
VO = 5V
VI = 0V
5
0
= RC
Remember
B
demo
Lecture 12
13
6.002
CIRCUITS AND
ELECTRONICS
Digital Circuit
Lecture
13
Review
vI
vI +
VI
+
vC
vC (0 ) = VO
vC = VI + (VO VI ) e
t
RC
vC
VI
VO
RC
time constant RC
t
Lecture
13
A
X
VS
VS
A
vA
5V
0
1 0 at A
B
CGS
X
t
Lecture
13
VS
B
vA
5V
CGS
0
1 0 at A
vB
5V
ideal
observed
Lecture
13
A
vA
5V
VS
B
CGS
0
1 0 at A
t
5V
VOH
rising delay of X
Lecture
vB
tr
13
vI = VS
RL
vI = VS
vB (0 ) = 0
From
CGS
+
vB
for t 0
1
vB = VS + (0 VS ) e
t
RL CGS
Lecture
13
Or
vOH = VS VS e
Find tr :
VS e
t r
RL CGS
t
RL CGS
= VS VOH
VS VOH
tr
= ln
RL CGS
VS
VS VOH
t r = RL CGS ln
VS
Lecture
13
Or
vOH = VS VS e
Find tr :
VS e
t r
RL CGS
t
RL CGS
= VS VOH
VS VOH
tr
= ln
RLCGS
VS
VS VOH
t r = RL CGS ln
VS
e.g.
RL = 1K
VS = 5V
CGS = 0.1 pF
VOH = 4V
t r = 1 10 0.1 10
3
= 0.16 ns
12
54
ln
5
RC = 0.1 ns !
6.002 Fall 2000
Lecture
13
Falling Delay tf
Falling delay tf is
the t for which vB falls to VOL
RL
VS +
CGS
RON
+
vB
Lecture
13
Falling Delay tf
RL
VS +
RON
CGS
+
vB
CGS
+
vB
X
Thvenin replacement
RTH
VTH +
RTH = RL || RON
VTH
6.002 Fall 2000
RON
= VS
RON + RL
Lecture
13
10
From
1
vB = VTH + (VS VTH ) e
t
RTH CGS
Falling decay tf is
the t for which vB falls to VOL
t f
VOL VTH
t f = RTH CGS ln
VS VTH
Lecture
13
11
t f = RTH CGS ln
e.g.
RL = 1K
VS = 5V
CGS = 0.1 pF
RTH 10,
VOL VTH
VS VTH
RON = 10
VOL = 1V
VTH 0V
t f = 10 0.1 10
= 1.6 ps
12
1
ln
5
RC = 1 ps !
Lecture
13
12
Problem
chip
pin 2
pin 1
v
CL
v:
ideal
observed
slow!
RL
RON
made RL small
made RON small
Lecture
13
13
Problem
chip
pin 2
pin 1
v
CL
v:
ideal
observed
slow!
but, disaster!
v:
observed
expected
VIL
Lecture
13
14
Why? Consider
Case
Demo
R1
pin1
R0
ok
Lecture
13
15
Why? Consider
Case 2
Demo
CP
R1
pin1
pin2
R0
R2
crosstalk!
CP
R
model for crosstalk:
+
v
Lecture
13
16
Case 3
CP
R0
R2
slower transitions!
Lecture
13
17
6.002
CIRCUITS AND
ELECTRONICS
Lecture 14
Review
Recall
vI
+
v I = VI
for
vC
vC (0)
t 0
t
vC = VI + (vC (0) VI ) e RC
Lecture 14
vI
VI
t 0
vI
vC
VI
t
vC = VI + (vC (0) VI ) e RC
vC (0 )
0
Lecture 14
State
q = C V
capacitor voltage V
Lecture 14
State
Back to our simple RC circuit 1
vC = f (vC (0 ), vI (t ))
vC = VI + (vC (0 ) VI ) e
t
RC
Lecture 14
State
vI (t) = 0
Correspondingly,
zero state response or ZSR
vC = VI VI e
t
RC
t
RC
Lecture 14
DIGITAL MEMORY
Why memory?
Examples
Lecture 14
Memory Abstraction
A 1-bit memory element
d IN
store M
d OUT
The
6.004
view
The
NEC
View
d IN
store
d OUT
6.002 Fall 2000
remembers the 1
Lecture 14
A First attempt
dIN
dOUT
C
storage
node
store
Lecture 14
vC d
OUT
dIN
store = 1
C
vC d
OUT
dIN
store = 0
C
vC
vC = 5 e
t
RL C
T = RLC ln
VOH
RL
5V
VOH
from 2
Lecture 14
10
B Second attempt
dIN
buffer
dOUT
*
C
RIN
buffer
store
Input resistance RIN
VOH
T = RIN C ln
5
RIN >> RL
Better, but still not perfect.
Demo
Lecture 14
11
C Third attempt
buffer + refresh
store
dIN
dOUT
*
store
C
Does this work?
Lecture 14
12
D Fourth attempt
buffer + decoupled
refresh
store
dIN
dOUT
*
store
C
Works!
Lecture 14
13
A Memory Array
4-bit memory
Decoder
00
01
10
11
OUT
d IN
S M
d OUT
d IN
S M
d OUT
d IN
S M
d OUT
d IN
S M
d OUT
a0 a1
Address
IN
store
Address
IN store
D
Lecture 14
OUT
14
a0
0
0
1
1
a1
0
1
0
1
A
1
0
0
0
B
0
1
0
0
Lecture 14
C
0
0
1
0
D
0
0
0
1
15
Lecture 14
16
6.002
CIRCUITS AND
ELECTRONICS
Second-Order Systems
Lecture
15
Second-Order Systems
5V
5V
Demo
2K
50
2K
A
+
B
large
loop
CGS
Lecture
15
Second-Order Systems
5V
5V
Demo
50
2K
2K
C
A
+
Relevant circuit:
B
large
loop
2K
CGS
5V +
B
CGS
Lecture
15
Observed Output
2k
5
vA
0
vB
0
2k
vC
0
Lecture
15
Observed Output
~50
5
vA
0
vB
0
50
vC
0
t
Huh!
Lecture
15
vI (t )
i (t )
+
v(t )
Node method:
i (t ) = C
dv
dt
Recall
vI v = L
dv
1
(vI v) dt = C
L
dt
1
(v I v )
L
di
dt
1 t
(vI v) dt = i
d 2v
=C 2
dt
d 2v
LC 2 + v = vI
dt
time2
6.002 Fall 2000
v, i state variables
Lecture
15
Solving
Recall, the method of homogeneous and
particular solutions:
1
v = vP (t ) + vH (t )
Lecture
15
Lets solve
d 2v
LC 2 + v = vI
dt
For input
V0
vI
0
And for initial conditions
v(0) = 0 i(0) = 0 [ZSR]
Lecture
15
Particular solution
d 2 vP
LC 2 + vP = V0
dt
is a solution.
vP = V0
Lecture
15
Homogeneous solution
Solution to
d 2 vH
LC 2 + vH = 0
dt
Recall, vH :
solution to homogeneous
equation (drive set to zero)
Four-step method:
LCAs 2 e st + Ae st = 0
1
s =
LC
characteristic
equation
1
s=j
LC
C Roots
j = 1
o =
s = j o
1
LC
General solution,
Lecture
15
10
Total solution
v(t ) = vP (t ) + vH (t )
0 = CA1 jo CA2 jo
or,
A1 = A2
V0 = 2 A
V0
A1 =
2
so,
V0 jot
v( t ) = V0 (e + e jot )
2
Lecture
15
11
Total solution
e jx + e jx
= cos x
2
so,
v( t ) = V0 V0 cos ot
where
i( t ) = CV0o sin ot
1
o =
LC
Lecture
15
12
v(t )
2V0
V0
3
2
2
CV0o
o t
i (t )
3
2
o t
CV0o
6.002 Fall 2000
Lecture
15
13
Summary of Method
1
Total solution is vP + vH ,
solve for remaining constants using
initial conditions.
Lecture
15
14
Example
What if we have:
iC
+
C vC
vC (0) = V
iC (0) = 0
Lecture
15
15
Example
iC
+
C vC
vC (0) = V
iC (0) = 0
V = A1 + A2
iC (0) = 0
0 = CA1 jo CA2 jo
or A1 = A2 =
or
vC =
V
2
V j o t
(
e + e j o t )
2
vC = V cos ot
iC = CV o sin ot
6.002 Fall 2000
Lecture
15
16
Example
vC
o t
CVo iC
2
o t
CVo
Lecture
15
17
Energy
EC
C:
1
CV 2
2
1
2
CvC
2
o t
EL
1
2
L : LiC
2
1
CV 2
2
2
Notice
o t
1
1
1
2
2
CvC + LiC = CV 2
2
2
2
Lecture
15
18
RLC Circuits
R
vI (t ) +
i (t )
C
+
v(t )
v(t )
no R
add R
t
Damped sinusoids with R remember demo!
Lecture
15
19
6.002
CIRCUITS AND
ELECTRONICS
Lecture
16
Review
R
L
C
Lecture
16
Motivation
vi
VBIAS
vO
vC
Demo
CGS
Lecture
16
Example:
vI +
iC
vI (t ) = Vi cos t
=0
vC (0) = 0
+
vC
vI
t
Lecture
16
Our Approach
Example:
vI
+
iC
vC
Effort
Determine vC(t)
agony
Usual
approach
sneaky approach
very
sneaky
Th
is
lec
tu
re
11
:
0
0
11
:
2
0
1
2
N
:0
ex
0
t
le
ct
ur
e
easy
e
m
e
g
l
u
d
In
Lecture
16
Set up DE.
Find vp.
Find vH.
vC = vP + vH,
Lecture
16
Usual approach
Set up DE
RC
dvC
+ vC = vI
dt
= Vi cos t
Lecture
16
Find vp
dvP
+ vP = Vi cos t
RC
dt
First try:
nope
vP = A
Second try:
vP = A cos t
Third try:
vP = A cos(t + ) frequency
amplitude phase
nope
..
.
gasp !
Lecture
16
dvPS
+ vPS = vIS
RC
dt
= Vi e st
st
v
=
V
e
Try solution PS
p
RC
dV p e st
+ V p e st = Vi e st
dt
sRCV p e st + V p e st = Vi e st
Nice
property
of
exponentials
( sRC + 1 )V p = Vi
Vi
Vp =
1 + sRC
Vi
e st
1 + sRC
is particular solution to Vi e st
Thus, vPS =
ly
Vi
e j t
1 + jRC
j t
V
e
solution for i
where we replace s = j
complex amplitude
Vp
6.002 Fall 2000
easy!
Lecture
16
= real[Vi e j t ] = real[vIS ]
real
part
vI response vP
real
part
Lecture
16
10
complex
vP = Re[vPS ] = Re[V p e jt ]
Vi
= Re
e j t
1+ jRC
Vi (1 jRC ) j t
= Re
e
1 + 2 R 2C 2
Vi
j j t
= Re
e e , tan = RC
2 2 2
1+ R C
Vi
j( t + )
= Re
1 + 2 R 2C 2
vP =
Vi
1+ R C
2
cos( t + )
Lecture
16
11
Find vH
Recall,
vH = Ae
t
RC
Lecture
16
12
vC = vP + vH
vC =
Vi
1+ R C
2
cos( t + ) + Ae
t
RC
where = tan 1 ( RC )
Phew !
Lecture
16
13
Vi
1+ R C
2
t
RC
cos( t + ) + Ae
0
t
RC
where = tan 1 ( RC )
Vi
A=
cos( )
2 2 2
1+ R C
Vp
Vp
Described as
SSS: Sinusoidal Steady State
Lecture
16
14
Vi
Vp =
1 + jRC
Recall
Vp
1
=
Vi 1+ jRC
Vp
Vi
magnitude
Vp
phase :
Vi
Vp
Vi
1
1 + 2 R 2C 2
e j where
= tan 1 RC
1
1 + 2 R 2C 2
= tan 1 RC
Lecture
16
15
Vi cos t
drive
D.E.
+
nightmare
trig.
V p cos[t + V p ]
particular
solution
algebraic
take
equation
real
+
part
complex
algebra V p e j t
sneak
in
Vi e jt
drive
Lecture
16
16
Magnitude Plot
transfer function
Vp
H ( j ) =
Vi
Vp
Vi
Vp
Vi
1
1 + 2 R 2C 2
log
scale
log
scale
1
=
RC
Lecture
16
17
Phase Plot
= tan 1 RC
=
Vp
Vi
=
0
1
RC
log scale
Lecture
16
18
6.002
CIRCUITS AND
ELECTRONICS
Lecture 17
Review
vI = Vi cos t +
+
vO
Focus on sinusoids.
SSS
Lecture 17
Review
vP
Vi cos t
1
usual
circuit
model
sneak
in
Vi e jt
drive
set
up
DE
complex
algebra
V p cos[t + V p ]
nightmare
trig.
Vp
2
3
vH
take 4
real total
part
V p e j t
Vi
1 + jRC
Vp
V p
6.002 Fall 2000
Review
vO = V p cos(t + V p )
Vp
Vi
Vp
1
= H ( j ) transfer
function
1 + jRC
remember
demo
Vi
1
2
1
RC
1 + 2 R 2C 2
Bode plot
Vp
Vi
1
=
RC
break frequency
1
RC
RC
tan 1
1 4
Lecture 17
1
V p = Vi
j C
1
+R
j C
ZC
V p = Vi
ZC + R
Lets explore further
Lecture 17
+
vC
iR
i R = I r e j t
vR = RiR
vR = Vr e j t
Vr e j t = RI r e j t
Resistor
iC
iC = I C e
j t
vC = VC e j t
Vr = RI r
dvC
iC = C
dt
I C e j t = CVC je j t
Capacitor
+
vL
VC =
diL
vL = L
dt
j t
iL
iL = I l e
vL = Vl e j t
Vl e j t = LI l je j t
Inductor
6.002 Fall 2000
1
IC
j C
ZC
Lecture 17
Vl = jL I l
ZL
Ic
+
Vc
ZC
Vc = Z C I c
1
ZC =
j C
impedance
inductor
resistor
Il
+
Vl
+
Vr
ZL
Ir
ZR
Vl = Z l I l
Z l = j L
Vr = Z r I r
Zr = R
Lecture 17
Back to RC example
R
+
C vC
vI +
Impedance model:
ZR = R
Ic
+
Vc
Vi +
1
ZC =
jC
1
ZC
jC
Vc =
Vi =
Vi
1
ZC + Z R
+R
jC
Vc =
1
Vi
1 + jRC
Done!
Lecture 17
Ir
L
Vi e j t
Vi +
C
R
Vi cos t
Vr =
Vi Z R
Z L + ZC + Z R
+
Vr
Vr e j t
Vr cos(t + Vr )
Vi R
Vr =
1
j L +
+R
jC
Vr =
Vi jCR
2 LC + 1 + jCR
Lecture 17
Vi cos t
usual
circuit
model
set
up
DE
Lecture 17
nightmare
trig.
10
Vi cos t
usual
circuit
model
Vi e jt
drive
set
up
DE
nightmare
trig.
complex
algebra
Lecture 17
take
real
part
11
Vi cos t
usual
circuit
model
Vi e jt
drive
set
up
DE
nightmare
trig.
complex
algebra
impedance-based
circuit model
take
real
part
complex
algebra
No D.E.s, no trig!
6.002 Fall 2000
Lecture 17
12
Back to
Ir
Vr
jRC
=
Vi 1 + jRC 2 LC
Vi
L
+
C
R
+
Vr
(
jRC
1 2 LC ) jRC
=
2
(1 LC ) + jRC (1 2 LC ) jRC
Vr
=
Vi
(1
RC
LC ) + (RC )
2
Observe
Low : RC
R
High :
L
LC = 1 : 1
Lecture 17
13
Graphically
Vr
=
Vi
RC
(1
LC ) + (RC )
2
Low : RC
R
High :
L
LC = 1 : 1
Vr
Vi
Band Pass
R
L
RC
1
LC
Lecture 17
14
6.002
CIRCUITS AND
ELECTRONICS
Filters
Lecture
18
Review
R
vI
+
vC
ZR
Vi +
+
Vc
ZC
ZC
Vc =
Vi
ZC + Z R
1
Vc
1
j C
=
=
1
Vi
+ R 1 + jRC
j C
Reading: Section 14.5, 14.6, 15.3 from A & L.
6.002 Fall 2000
Lecture
18
A Filter
ZR
Vi +
+
Vc
ZC
ZC
1
Vi =
Vc =
ZC + Z R
1 + jRC
Vc
H ( ) =
Vi
Demo
with audio
6.002 Fall 2000
Lecture
18
I ab
R1
Vab
RAB
Vab
=
= R1 + R2
I ab
Z AB
Vab
=
= R1 + jL
I ab
R2
I ab
R1
Vab
j L
B
Lecture
18
Z AB = R1 + Z C || R2 + Z L
R1
R2
C
L
= R1 +
Z C R2
+ ZL
Z C + R2
= R1 +
R2
+ jL
1 + jCR2
Lecture
18
L
Z
R
C
Lecture
18
L
Z
R
C
H ( )
HPF
High Pass Filter
H ( )
LPF
Low Pass Filter
H ( )
HPF
Lecture
18
Check out:
+
R Vr
Vi +
Intuitively:
Vr
1
Vi
L
k
bloc
q
fre
w
s lo
C bloc
o =
(1
RC
freq
LC
R
Vr
=
1
Vi
j L +
+R
j C
j RC
=
1 2 LC + j RC
Vr
=
Vi
ks hig
h
LC ) + ( RC )
2
Lecture
18
At resonance,
= o
and
ZL + ZC = 0,
so Vi sees
only R!
More later
8
What about:
Vi +
Vlc
Vi
1
Vlc
C open
L open
Lecture
18
Another example:
R
+
Vi +
Vo
Vo
Vi
ort
h
s
L
BPF
Cs
ho
rt
Lecture
18
10
AM Radio Receiver
antenna
R
Vi +
demodulator
amplifier
Thvenin
antenna
model
crystal radio demo
Lecture
18
11
AM Receiver
R
Vi +
signal
strength
demodulator
amplifier
filter
10 KHz
WBZ
News
Radio
f
540 1000 1010 1020 1030 1600 KHz
Selectivity important
relates to a parameter Q for the filter. Next
6.002 Fall 2000
Lecture
18
12
Selectivity:
Look at series RLC in more detail
C
Vi +
Recall,
Vr
Vi
+
Vr
R
Vr
R
=
Vi R + j L + 1
j C
higher Q
1
2
bandwidth
o
o
Define Q =
quality factor
Lecture
18
13
Quality Factor Q
Q=
:
Vr
R
=
Vi R + j L +
1
=
1
L
1
1 + j
j C
R
CR
at =0
1
o =
LC
?
Lecture
18
14
Quality Factor Q
o
Q=
:
Note that abs magnitude is
when
Vr
=
Vi
i.e. when
1
2
1
1
=
L
1 1 j1
1 + j
R CR
L
1
= 1
R CR
R
L
1
=0
LC
R 1
2 =
+
2L 2
R2
4
+
L2 LC
R
= 1 2 =
L
Lecture
18
15
Quality Factor Q
o
Q=
Q=
o
R
L
o L
1
o =
LC
Lecture
18
16
Quality Factor Q
Another way of looking at Q :
energy stored
Q = 2
energy lost per cycle
= 2
1
L Ir
2
1 2 2
Ir R
0
2
o L
Q=
R
Lecture
18
17
6.002
CIRCUITS AND
ELECTRONICS
Lecture 19
Review
+
vO output
port
+
input
vI
port
VS
power
port
Amplifier abstraction
VS
+
vI
+
v
O
vI
Lecture 19
vO
Function of vI
Review
vI
vO
Function of vI
Today
Introduce a more powerful amplifier
abstraction and use it to build more
complex circuits.
Lecture 19
Operational Amplifier
Op Amp
VS
input
port
power
port
output
port
VS
More abstract representation:
+
vIN
Lecture 19
vOUT
+
i=0
v+
+
v
i=0
Av
A
Lecture 19
Using it
12V
VS = 12V
vO
vIN
12V
RL
VS = 12V
Demo
12V
10 V
vO active region
saturation
10V
12V
vIN
A ~ 106
but unreliable,
temp. dependent
Lecture 19
vIN +
vO
R1
R2
vIN +
op amp
v+
v
vO
+ A(v + v )
R1
i=0
R2
6.002 Fall 2000
Lecture 19
vO = A(v + v )
R2
= A vIN vO
R1 + R2
AR2
vO 1 +
= AvIN
R1 + R2
AvIN
vO =
AR2
1+
R1 + R2
What happens when A is very large?
Lecture 19
vO =
AR2
AR2
1+
R1 + R2 R1 + R2
vIN
Suppose
(R1 + R2 )
A = 10 6
R1 = 9 R
R2 = R
R2
gain
10 6 vIN
vO =
10 6 R
1+
9R + R
10 6 vIN
=
1
6
1 + 10
10
vO vIN 10
Demo
Gain:
determined by resistor ratio
insensitive to A, temperature, fab variations
6.002 Fall 2000
Lecture 19
vIN +
5V
10V
A
6V
6V
negative
feedback
i =0
12V
vO = 2vIN
R
vO
2
R
e.g. vIN = 5V
Suppose I perturb the circuit
Lecture 19
10
no
di
s
yes
release apply
Michelin
its
all about
control
yes/no
k
c
a
db
e
e
f
v. v. powerful brakes
Lecture 19
11
vIN
R1
v
v+ v = O =
0
A
A
v+ v
We also know
i+ 0
i - 0
yields an easier analysis method
(under negative feedback).
Lecture 19
12
vIN +
g vO = vIN
+
vO
b vIN
c vIN
R1 f
e i=0
vIN
d
R2
R1 + R2
R2
Lecture 19
vIN
R2
R2
13
Question:
a vIN v +
vIN +
b vIN
c vIN
vO
vO vIN
or
R1 + R2
vO = vIN
R2
with R1 = 0
R2 =
Lecture 19
14
vIN +
vO
vO vIN
Buffer
voltage gain = 1
input impedance =
output impedance = 0
current gain =
power gain =
Lecture 19
15
6.002
CIRCUITS AND
ELECTRONICS
Lecture 20
Review
input resistance
0 output resistance
Gain A very large
Lecture 20
R1
v2 +
v1 +
R2
v = v1
R1 + R2
v
+
v2 v
i=
R1
R1
R2
v
v+ +
+
vOUT
R2
vOUT = v iR2
v
= v 2
R2
R1
R
R
= v 1 + 2 v2 2
R1
R1
= v1
R2
R + R2
R
1
v2 2
R1 + R2
R1
R1
R2
= (v1 v2 )
R1
6.002 Fall 2000
subtracts!
Lecture 20
v2 0
R1
R2
R1
v2 +
v1 +
v+ +
R2
vOUT2
vOUT2
vOUT1
R1 + R2
=v
R1
+
v1 R2 R1 + R2
=
R1 + R2
R1
= v1
R2
R1
R1 || R2
R2
= v2
R1
vOUT1
Lecture 20
R2
R1
Still subtracts!
4
+
vO
dt
+
i +
vO
1
vO = i dt
C
vO is related to i dt
But we need to somehow convert
voltage vI to current.
6.002 Fall 2000
Lecture 20
vI +
R
C
vO
vI
i
R
RC
Demo
6.002 Fall 2000
Lecture 20
Notice
i
R
vI +
vI
R
vC
vI
vO = vC
+
t
vO
1 vI
vO = dt
C R
Lecture 20
d
dt
vI +
dvI
i=C
dt
dvI
i is related to
dt
But we need to somehow convert current
to voltage.
Lecture 20
Differentiator
Recall
i
i
+
R
+
vO
+
0V
C
vI +
+ vC
Demo
6.002 Fall 2000
vO = iR
current
to
voltage
vO
vI = vC
dvI
i=C
dt
dvI
vO = RC
dt
Lecture 20
6.002
CIRCUITS AND
ELECTRONICS
Lecture
21
R1
vIN +
+
R
+
vOUT = 2 vIN
R1
is
s
e
y
l
g
a a
an t p
e ex
e
s n
on
+
R2
vOUT = vIN
R1
vIN +
R1
R2
vOUT VS
Lecture
21
v IN +
R1
R2
vOUT
v + R2
R1
vOUT
A(v + v )
vOUT = A(v + v )
= Av +
v vIN
= A OUT
R1 + vIN
R1 + R2
AR1vIN
AR1
vOUT
+ AvIN
R1 + R2
R1 + R2
AR1
R1
vOUT 1
v
A
1
=
IN R + R
R1 + R2
1
2
vOUT
1 R1
R +R
R2
1
2
Av
vIN
IN
AR
R1
1
R1 + R2
Lecture
21
v+
+
+
v*
C
(v + v )
Lecture
vo
+
Av*
21
vo
R4
R3
Circuit model
R1
v+
v
R3
vo
A
R2
C
(v + v )
+
v*
+
vo
R4
Lecture
21
Dynamics of op amp
vo = Av
vo
or v =
A
*
dv* *
RC
+ v = v+ v_
dt
vo R1
+
= vo
R1 + R2
vo R3
v =
=
vo
R3 + R4
v+ =
RC dvo vo
+ = v+ v_
A dt A
+
= ( ) vo
neglect
or
dvo 1
A +
+
+
( ) vo = 0
dt RC RC
dvo
A +
+
( ) vo = 0
dt RC
time 1
or
dvo vo
RC
+ = 0 where T = +
A( )
dt T
vo ( 0 ) = 0
6.002 Fall 2000
Lecture
21
if >
T is positive
vo = K e
if
+
>
+
=
vo
stable
T is negative
vo = K e
if
t
T
t
T
unstable
T is very large
vo = K
neutral
unstable
neutral
stable
disturbance
v+
vo
VS
+ VS
vo
v+ v
VS
vo
v 0
t
Lecture
21
vo
R2
vo R1
v =
R1 + R2
+
v = 7.5
R1
vo = 15
vi
( vi = v ) > 7.5
v < v+
v < 7.5
v > 7.5
vo = 15
e.g. R1 = R2
VS = 15
Lecture
v = 7.5
21
vo
R2
vo R1
v =
R1 + R2
+
VS R1
v =
R1 + R2
+
R1
vo = +VS
15
vi
( vi = v ) > v +
e.g. R1 = R2
VS = 15
v < v+
v < 7.5
v > 7.5
vo = VS 15 v =
Lecture
21
VS R1
R1 + R2
10
vo
15
VS
hysteresis
7 .5
Demo
vi
7 .5
15
VS
e.g., analog
to digital
7.5
t
7.5
Demo
6.002 Fall 2000
Lecture
21
11
Without hysteresis
vi
7.5
analog
to digital
vo
vi
t
7.5
Lecture
21
12
vC
vo
R1
vo
2
R1
vo
VS
VS
2
v+
v
vC
VS
2
VS
Demo
6.002 Fall 2000
v+
Assume
Lecture
vo = VS
vC = 0
21
at t = 0
13
t
can use as a clock
Why do we use a clock in a digital system?
sender
receiver
clock
a
1,1,0?
Discretization of time
one bit of information associated with
an interval of time (cycle)
6.002 Fall 2000
Lecture
21
14
6.002
CIRCUITS AND
ELECTRONICS
Lecture
22
small batteries
good
Today:
How long will the battery last?
in standby mode
in active use
Will the chip overheat and self-destruct?
Lecture
22
vO
Lecture
22
Example 1:
V +
Power
+
V
V2
P = VI =
R
E = VIT
Lecture
22
Example 1:
for our gate
VS
VS
RL
RL
vO
vI high
vI low
RON
RON
VS
P=
RL + RON
Lecture
vO
P=0
22
Example 2:
Consider
R1
S1
VS +
S2
R2
T
T1
T2
S1 closed S1 open
S 2 open
S 2 closed
t
Lecture
22
T1 : S1 closed, S2 open
i
VS +
R1
+
vC
vC
VS
R1
VS
assume
vC = 0 at t = 0
Lecture
VS
e
R1
t
R1C
22
E = VS i dt
0
T1
VS
e
R1
0
t
R1C
dt
VS
R1C e
R1
t T1
R1C
0
T1
2
R
C
1
= C VS 1 e
C VS if T1 >> R1C
1
2
C VS stored on C ,
2
1
2
E1 = C VS dissipated in R1
2
6.002 Fall 2000
Lecture
22
Independent
of R!
T2 : S2 closed, S1 open
+
vC
R2
Initially, vC = VS
So, initially,
1
2
energy stored in capacitor = CVS
2
Assume T2 >> R2C
So, capacitor discharges ~fully in T2
So, energy dissipated in R2 during T2
1
2
E2 = CVS
2
E1, E2 independent of R2 !
6.002 Fall 2000
Lecture
22
E = CVS
energy dissipated in
charging & discharging C
P=
E
T
CVS
=
T
= CVS f
frequency f =
6.002 Fall 2000
Lecture
22
1
T
10
vO
vIN
RON
vIN
T
2
T
2
T
t
1
T=
f
Lecture
22
11
Equivalent Circuit
RL
VS +
C
RON
T
2
T
2
T
t
1
T=
f
Lecture
22
12
P=
VS
RL
2
+ CVS f
2( RL + RON )
(RL + RON )2
VS
2
P=
+ CVS f
2 RL
r
e
b
m
e
m
re
P STATIC
independent of f.
MOSFET ON half
the time.
e
b
m
e
rem
P DYNAMIC
related to switching
capacitor
Lecture
22
13
VS
2
P=
+ CVS f
2 RL
In standby mode,
half the gates in a
chip can be
assumed to be on.
So P STATIC per
gate is still VS2 .
In standby mode,
f0,
so dynamic power
is 0
2RL
Relates to standby
power.
Lecture
22
14
Some numbers
a chip with 106 gates clocking
C =1f F
at 100 MHZ
RL = 10 k
f = 100 10 6
VS = 5 V
25
15
6
P = 10 6
10
25
100
10
+
2 10
= 10 6 [1.25 milliwatts + 2.5 microwatts ]
problem !
1.25KW!
VS 2
f
reduce VS
next
lecture
6.002 Fall 2000
2.5W
not bad
5 V 1V
2.5 W 150 mW
Lecture
22
15
6.002
CIRCUITS AND
ELECTRONICS
Energy, CMOS
Lecture
23
Review
VS
RL
VS
P=
RL + RON
vO
vI
RON
T1: closed
T2: open R
open
closed
VS +
S1
S2
R2
1
T = T1 + T2 =
f
2
P = CVS f
Lecture
23
Review
VS
RL
Inverter
vO
vI
RON
1
Square wave input
T=
f
2
VS
2
P=
+ CVS f
2 RL
Demo
P STATIC
independent of f.
MOSFET ON half
the time.
P DYNAMIC
RL >> RON
T
>>" RC"
2
time constant
related to switching
capacitor.
In standby mode,
f0,
so dynamic power is 0
Lecture
23
Review
P=
VS
2
+ CVS f
2 RL
C = 1 f F, RL = 10 K , f = 100 10 6 , VS = 5 V
2
5
6
15
2
6
P = 10
+ 10 5 100 10
3
gates 2 10 10
1.25KWatts
problem !
independent of f
also standby power
(assume MOSFETs
ON if f 0)
must get rid of this!
Lecture
2.5Watts
not bad
f
VS2
reduce VS
5V1V
2.5V150mW
23
VS
RL
RL
vO low
vI high
vI low
RON
vO high
MOSFET
off
idea !
VS
vI high
vO low
Lecture
23
D
G
S
5V
ON when
less than 4V
Lecture
23
vI
S
D
D
S
PU = pull up
vO
PD = pull down
IN
OUT
Lecture
23
OUT
IN
vI = 5V (input high)
vI = 0V (input low)
VS = 5V
VS = 5V
RON p
+
vI = 5V
vO
RON n
= 0V
+
vI = 0V
vO
= 5V
Complementary
MOS
(our previous logic was called NMOS)
Lecture
23
vI
T
vI
vO
closed for
vI high
closed for
vI low
RON p
VS +
From
1
f =
T
RON n
P = CVS f
Lecture
23
P = CV S f
= 10
15
5 2 100 10 6
106
100 ~2.5
MHz watts
Pentium?
2x106
300
~15
MHz watts
PII?
2x106
600
~30
MHz watts
PII?
8x106
~240
1.2 GHz watts
25x106
~1875
3 GHz watts
Lecture
PIII?
keep
all
else
same
!
p
s
ga
PIV?
23
10
Lecture
23
11
CMOS Logic
NAND:
VS
A
A B
0 0
0 1
1 0
1 1
Z
1
1
1
0
Z
A
B
5V
0V
G
S
on
D
Lecture
5V
5V
G
23
S
off
D
12
VS
short when
A = 0 or B = 0,
open otherwise
short
when F
is true,
else open
A
B
Z
short
when F
is true,
else open
short when
A B is true,
else open
r
e
b
m
reme gans law
r
o
M
e
D
Lecture
23
13
6.002
CIRCUITS AND
ELECTRONICS
Lecture 24
+
5V DC
PCC
+
5V DC
110V
60Hz
solar cells,
battery
3V
DC
DC-to-DC UP converter
Power efficiency of converter important,
so use lots of devices:
MOSFET switches, clock circuits,
inductors, capacitors, op amps, diodes
Lecture 24
VvD
iD = I S e 1
I S = 10 12 A
iD
+
vD
VT = 0.025V
Boltzmanns constant
temperature in Kelvins
charge of an electron
kT
VT =
q
iD
iD
vD
IS
vD
V
mV
analytical
graphical
incremental
Lecture 24
short
or
on
vD < 0 iD = 0
vD
open
or
off
Lecture 24
0.6V
iD
Short segment
Open segment
iD = 0
vD = 0
0.6V
Lecture 24
vD
Lecture 24
Example
(We will build up towards an AC-to-DC converter)
0.6V
+
Consider
+
vI +
vO
vI
is a sine wave
Lecture 24
Example
0 .6 V
+
Equivalent
circuit
vI +
vO
Short segment:
iD = (vI 0.6 ) / R
vI 0.6
0.6V
+ vI
vO = vI 0.6
Open segment:
iD = 0
vI < 0.6
+ vI
+
0.6V
vO = 0
Lecture 24
Example
vI
vO
0.6
t
Lecture 24
+
vI +
+
R
vO
Lecture 24
10
A half-wave rectifier
vI
diode on
diode off
vO
Demo
C
current
pulses
charging
capacitor
Lecture 24
11
se
Do not u
resistive
s!
el em en t
DC-to-DC UP Converter
i
+
VI +
DC
vS
C vO
switch
load
vS
S
closed
open
t
Tp
Lecture 24
12
VI +
VI T
i (T ) =
L
vO
C
di
VI = L
dt
VI
slope =
L
i is a ramp
1
E = energy stored at t = T : Li( T )2
2
2
VI T 2
E =
2L
6.002 Fall 2000
Lecture 24
13
vO
VI +
VI T
L
0
T T
TP
1
O =
LC
Lecture 24
14
VI T
L
0
T T
1
O =
LC
Capacitor voltage
ignore
diode
drop
O =
TP
vO
III.
vO (T )
1
LC
vO
0
T T
TP
Lecture 24
15
VI T
L
0
T T
1
O =
LC
Capacitor voltage
ignore
diode
drop
O =
TP
vO
III.
vO (T )
1
LC
vO
0
T T
TP
Lecture 24
16
+
VI +
C vO
C holds vO after T
i is zero
Capacitor voltage
vO
Lecture 24
TP
17
+
VI +
C vO
C holds vO after T
i is zero
until S turns ON at TP, and cycle repeats
I II III I II III
Thus, vO increases each cycle, if there is no load.
vO
vO (n)
TP 2TP 3TP
6.002 Fall 2000
Lecture 24
t
18
E
=
L
i
(
t
=
T
)
2
2
1 VI T 2
E =
2
1 VI T
2 L
= L
2 L
After n cycles, energy on capacitor
2
nVI T 2
nE =
2L
1
This energy must equal CvO ( n )2
2
so,
or
2
1
nV
T
2
CvO ( n ) = I
2
2L
2
nVI T 2
vO ( n ) =
LC
1
O =
LC
vO ( n ) = VI T O n
6.002 Fall 2000
Lecture 24
19
vO
load
vO
pwm
control
change T
Tp
recall
compare
+ vref
VI T 2
E =
2L
(v
(v
O
O
vref )
vref )
then T
then T
Lecture 24
20
6.002
CIRCUITS AND
ELECTRONICS
Lecture 25
Problem
VO
0 1 Vi
expected
observed
VO 1
VO 1
huh?
t
0
in forbidden region!
Lecture 25
(a) DC case
R
VO
V1
Vi
Vi = 5V DC
VO = 5V DC V1 = 5V DC
Lecture 25
very high
impedance,
like open
circuit
OK
(b)
Step
R
VO
V1
Vi
very high
impedance,
like open
circuit
5V Vi
b.1
0V
b.3
5V
t=0
VO
not ok!
VO = 2.5V
t=0
b.2
2T
5V V1
looks ok!
t=0 T
6.002 Fall 2000
Lecture 25
t
4
2.5
....
Vi
characteristic
impedance
instantaneous R divider
finite propagation speed
of signals
5V
5V
5V
2T
Lecture 25
0 T
5V V1
rce
u
o
S
tion
a
n
i
Term
1. Look only at V1
O
DEM
3. Termination
O
DEM at the
R
add
end
5V VO
0
le l
Paral ation
in
term
5V VO
2.5V
More in 6.014
6.002 Fall 2000
Lecture 25
OK
driving a 50
resistor!
0
V
driving a 50
resistor!
input
Why?
Lecture 25
VS
V
Inverter current
v inductor
VS
solution
1. short wires
2. low inductance wires
3. avoid big current swings
Lecture 25
a given chip
worked,
but was slow.
ideal
actual
actual
Disaster!
6.002 Fall 2000
Lecture 25
Why?
DEMO
Consider
ok
R1
R0
DEMO
R2
dV
dt
dV
C
dt
crosstalk!
6.002 Fall 2000
Lecture 25
10
Solution
DEMO
small
Load output!
dV
dt
11
Vo
Vi
expect
Vo
Vi
but, observe
Vo
Vi
6.002 Fall 2000
Lecture 25
12
5V
Vi
5V + 3V
5V
0V
3V
Lecture 25
13