TNANO Author PROOF PDF

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO.
00, 00 2014
Novel 4F2 Buried-Source-Line STT MRAM Cell

With Vertical GAA Transistor as Select Device
Shivam Verma, Student Member, IEEE, Shalu Kaundal, Student Member, IEEE,
and Brajesh Kumar Kaushik, Senior Member, IEEE
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AbstractSpin transfer torque (STT) magnetic random access

memories (MRAMs) have recently emerged as one of the strongest
contenders for universal memory technology. They have entire
range of features, i.e., high speed, nonvolatility, high density, and
low power, which make them cynosure to every memory designers
notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a
larger amount of embedded memory, the cell size must be reduced.
Therefore, the designs target to attain an optimistic figure of 4F2
(F being the feature size) array density, which is the maximum
achievable two-dimensional (2-D) density. With this objective in
mind, a novel 4F2 buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source
NMOS transistor is proposed. The magnetic tunnel junction (MTJ)
multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ
and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical
GAA device structure. Furthermore, these TCAD results are used
to calibrate the BSIM CG model for cylindrical GAA transistors.
The proposed STT MRAM cell is then analyzed using calibrated
Verilog-A models for perpendicular anisotropy MTJ and vertical
GAA NMOS transistor (BSIM CG). The performance analysis in
terms of read stability, write margins, and power dissipation for
the proposed cell is also presented.
Index TermsMagnetic tunnel junction (MTJ), perpendicular
magnetic anisotropy (PMA), spin transfer torque (STT), vertical
gate all around (GAA).
33
I. INTRODUCTION
34
NALOGOUS to a typical memory system, spin transfer

torque (STT) magnetic random access memory (MRAM)
consists of memory cells connected to form an array. Conventionally, each cell is composed of a storage element as magnetic
tunnel junction (MTJ) and a planar NMOS transistor as select
device. An MTJ consists of two ferromagnetic (FM) layers separated by a nonmagnetic insulator layer. The resistance of MTJ
depends on the magnetization orientations of the two FM layers. Each cell stores data as the resistance state of an MTJ. The
resistance state of MTJ is high (binary 1), if the two FM layers
have antiparallel (AP) alignment of magnetization. Conversely,
35
36
37
38
39
40
41
42
43
44
it is low (binary 0) if the magnetization orientations of the two

FM layers have a parallel (P) alignment.
Embedded memory can be accessed faster as compared to the
external memory; hence, there is a continuously increasing quest
for an on-chip embedded memory. Moreover, in almost every
memory technology, the select devices have been the bottleneck
toward increasing the integration density [1]. Keeping this in
mind, several novel architectures for select devices have been
proposed by researchers working in the area [2][5]. They have
been primarily focusing on vertical select devices to reduce the
cell area. Kawahara et al. [6] analyzed memory cell scalability
for STT MRAMs for various transistor gate widths and informed
the possibility of cell area reduction up to 4F2 with a vertical
select device. However, till date no thorough analysis has been
presented for vertical select device driving STT MRAM cells.
In the conventional in-plane MTJ technology, the switching
current is quite high (2001200 A) [7], [8]. Such high current
drive could not be achieved with minimum-sized transistors,
and hence, scaling toward 4F2 array density per cell is not feasible for STT MRAMs with in-plane MTJs. However, with the
evolution of perpendicular magnetic anisotropy (PMA) MTJs
(with switching current as low as 20100 A or even less), one
can see decent prospects for higher integration density in STT
MRAMs.
The planar MOSFETs have a saturation drive current per
unit width of 900 A/m for high-performance logic [9]. On
the other hand, gate all around (GAA) MOSFETs have been
reported to have a much higher saturation drive current of 2.6
2.9 mA/m per unit diameter [10]. Hence, GAA transistor with
the same diameter should provide a larger drive current. A vertical GAA transistor can act as an ideal select device that can
provide sufficient drive current for efficient switching of an
MTJ. In addition, it will provide a cell size of minimum 2-D
area. Considering these facts, this paper proposes a novel STT
MRAM cell with vertical GAA transistor as select device with
a buried source line (SL) and word line (WWL). The objective
is to improve or retain the other performance specifications (access time read and write margins) with the proposed 4F2 STT
MRAM cell. A detailed analysis is done taking into account
the design considerations and the constraints for an efficient
STT MRAM cell. The proposed cell is also compared with the
minimum-sized cell that can be realized with a planar select
device.
The paper is divided into seven sections, including the introductory section. The architecture and functionality of the
proposed STT MRAM cell are presented in Section II. Section
III analyzes the recent advances in the field of PMA MTJs for
IE
E
Pr E
oo
f
Manuscript received January 29, 2014; accepted July 31, 2014. Date of publication; date of current version. The review of this paper was arranged by
Associate Editor A. Martinez.
The authors are with the Microelectronics and VLSI Group, Department
of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India (e-mail: shivamvermaid@gmail.com;
shalupec@iitr.ac.in; bkk23fec@iitr.ac.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2014.2346790
1536-125X 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Q1
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014
III. ANALYSIS OF PRACTICALLY FABRICATED PMA MTJS
127
PMA MTJs offer low critical currents and higher thermal stability and scalability for STT switching. Lee et al. [11] demonstrated a PMA in Fe-rich CoFeB free layers due to the reduction
of demagnetizing field. The demagnetizing field decreases with
increase in perpendicular anisotropy and eventually leads to a
layer with perpendicular easy axis. The effective demagnetizing
(4Me ) field is expressed as
128
4Me = 4MS Hkp
Fig. 1. (a) Typical STT MRAM cell. (b) Front view of the proposed STT
MRAM cell.
93
94
95
96
97
98
99
100
101
creating Verilog-A models based on experimental results. Section IV focuses on the design considerations (read, write margins and switching probability) of an STT MRAM cell from the
perspective of select devices. Section V describes the TCAD
analysis of the proposed buried source GAA device followed
by the load line analysis. Section VI analyzes and compares
the HSPICE simulation results of the proposed STT MRAM
cell with conventional STT MRAM cell. Finally, in Section
VII, conclusions are drawn based on the analysis done in the
previous sections.
102
II. PROPOSED STT MRAM ARCHITECTURE
103
STT MRAMs have three-dimensional (3-D) integration of

MTJs with conventional CMOS technology. The memory cell
of STT MRAMs has one MTJ and one NMOS select device,
abbreviated as a 1T-1MTJ cell. The structure and properties of
a typical 1T-1MTJ STT MRAM cell can be understood through
Fig. 1(a). The bottom layer (pinned or fixed layer) of an MTJ
has fixed magnetization due to its comparatively high magnetic
coercivity. The top layer of the MTJ is known as free/recording
layer whose magnetization can be switched by the spin torque
acting on it. This spin torque is generated by the electric current, which is spin polarized by the pinned bottom layer. The
directions of current for writing 1 and 0 are shown in Fig. 1(a).
A current from BL to SL would make the magnetization orientation as P (to write a 0). Conversely, a current from SL to
BL would make the magnetization states of two layers as AP (to
write a 1). Besides this, for both the directions, the write currents
need to be above a minimum threshold value for proper switching of the MTJ. The front view of the proposed architecture
is shown in Fig. 1(b) that consists of a PMA MTJ multilayer
structure stacked above the vertical GAA cylindrical NMOS
transistor. The bit line (BL) and buried SL are perpendicular to
the plane of paper, while the WWL is in the plane of the paper.
The proposed GAA structure allows the maximum possible 2-D
array density for STT MRAMs.
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
131
132
133
134
(1)
where Hkp is the perpendicular uniaxial anisotropy, Ms is the

magnetization of the layer and 4Ms is the demagnetizing field.
When Hkp exceeds 4Ms , the magnetic moment of CoFeB
has an easy axis perpendicular to the plane of MTJ. The low
switching current density is attributed to Hkp , which cancels
the effect of the out of plane demagnetizing field 4Ms .
Ikeda et al. [7], [12] demonstrated that the performance of
CoFeB/MgO/CoFeB based PMA MTJ with 40 nm diameter
shows excellent properties that includes a high stability factor
(E/KB T = 39) and low switching current (IC0 = 49 A). The
only limitation is large write voltage due to high resistance area
(RA) product, which leaves a scope of improvement. Moreover,
Gajek et al. experimentally analyzed spin torque switching of
PMA MTJ with a diameter of 20 nm. However, the results are
not as promising because of a low TMR (57%) [13]. Hence,
experimental results (shown in Table I) for 40 nm PMA MTJ
are used to develop a Verilog-A model that precisely replicates
the behavior and properties [14].
IE
E
Pr E
oo
f
92
129 Q2
130
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149 Q3
150
151
152
IV. DESIGN CONSIDERATIONS
153
The select device in a typical memory system allows a memory cell to be accessible for read and write. This section describes
the design considerations of STT MRAMs from the perspective
of select devices. Fig. 2(a) and (b) represents the two states of
the STT MRAM cell before the write operation is performed.
Fig. 2(a) shows the equivalent circuit with polarity of BL and
SL trying to write a 0 into the cell (P write). Likewise, Fig. 2(b)
shows the equivalent circuit with the polarities of BL and SL
trying to write a 1 into the cell (AP write). Hence, an STT
MRAM cell can be viewed as an NMOS transistor with RP or
RAP connected to it as load.
The switching of MTJ depends on the direction of current and
also a minimum threshold current (IC0 ) required for switching
to occur. Hence, the primary consideration is that whether the
select device can provide sufficient drive current for MTJ switching in either direction. The driving current must be sufficiently
high to surmount the switching threshold with high switching
probability for proper operation of the STT MRAM cell.
A write error occurs when the strength of the write current is
not enough, and there is a probability that the desired data may
not be written into the cell [15]. Furthermore, a read disturb
is the unintentional write due to the read current flowing in a
direction; this lowers the switching energy barrier [15], [16].
The write error rate (WER) and read disturb rate (RDR) for
STT-MRAM cell are determined from the switching probability.
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
VERMA et al.: NOVEL 4F2 BURIED-SOURCE-LINE STT MRAM CELL WITH VERTICAL GAA TRANSISTOR AS SELECT DEVICE
TABLE I
PRACTICALLY FABRICATED MTJ PARAMETERS FOR CURRENT PULSEWIDTH OF 1 ns
Barrier/recording layer structure (nm)
MgO(0.85)/CoFeB(1.7)/Ta
Diameter
(nm)
40
TMR
(%)
113
RA
(m2 )
16
= E /k B T
R P (k)
R A P (k)
I L H 0 (A)
I H L 0 (A)
V W (V)
Reference
39
12.73
27.1
72
28
0.608
[7]
V W = J C 0 (RA) is the mean write voltage, where J C 0 is the switching current density and RA is the resistance area product. R A P = 27.1 k and TM R = 113% are the
zero-bias values for the PMA MTJ from [7].
are expressed as
200
WMAP = (IWAP0 ILH0 )

(4)
where IHL0 and ILH0 are AP to P and P to AP critical switching
currents, respectively.
Read margin is defined in terms of sensing current (read current) as the normalized difference between the critical switching
current and read current (sensing current) [16]. Analogous to
write margins, different read margins would be defined for P
(RMP ) and AP (RMAP ) reading mechanisms. The read current
during P reading has a direction from free layer (BL) to the
pinned layer (SL) of an MTJ. Likewise, the read current during
AP reading has a direction from pinned layer (SL) to free layer
(BL) of an MTJ. The RMAP and RMP are expressed as
IE
E
Pr E
oo
f
WMP = (IW P0 IHL0 ),
RMP =
Fig. 2. (a) Equivalent circuit of STT MRAM cell before MTJ switching with
AP resistance as load. (b) Equivalent circuit of STT MRAM cell before MTJ
switching with P resistance as load. (c) Top view of the vertical GAA NMOS
device. (d) Front view of the vertical GAA NMOS device.
179
WER and RDR are expressed as

RDR = PSW ,
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
WER = 1 PSW
(2)
where PSW is the probability of occurrence of switching below

critical switching current (IC0 ) that is expressed as [15]

tPW
E
I
PSW = 1 exp
exp
(3)
1
0
kB T
IC0
where tPW is the current pulsewidth, 0 is the attempt time, IC0

is the critical current required for switching, and E/kB T is the
Boltzmanns factor.
The drain current (ID ) should be very small, when the cell
has not been selected (WWL = 0) for reading or writing. The
current through the cell with WWL = 0 should be small enough
so that the switching probability is negligible, preferably below
109 [15]. This means that the select device should offer very
small off the current even though BL or SL is equal to VDD .
Write margin is defined as the difference between the writing
current and critical switching current of an MTJ [16]. The write
current must be sufficiently high to obtain a cell with large
write margins and small switching time. Different write margins
are defined for P (WMP ) or AP (WMAP ) write into the cell. The
write current for P writing IW P0 should have a direction from
free layer (BL) to the pinned layer (SL) of an MTJ. Conversely,
the write current for AP writing IWAP0 should have a direction
from pinned layer (SL) to free layer (BL). WMP and WMAP
IHL0 IP0
,
IHL0
RMAP =
ILH0 IAP0
ILH0
201
202
203
204
205
206
207
208
209
210
211
(5)
where IP0 and IAP0 are the read currents during P and AP
reading, respectively.
Write access time (tP and tAP ) is defined as the time required
for switching the state of MTJ at the particular write current
and write current pulsewidth. The switching time also depends
on the switching threshold at that write current pulse duration
(tPW ) [14].
218
V. VERTICAL GAA TRANSISTOR AS SELECT DEVICE
219
Conventionally, the overall area of the STT MRAM cell has

been dominated by the select device [1]. The proposed structure
allows us to accommodate the MTJ and select device within the
same area through 3-D stacking. In this section, the proposed
select device structure is thoroughly analyzed. The analysis has
been carried out for feature size F = 40 nm, which is same as
the diameter of the MTJ to keep the overall cell area 4F 2 . The
proposed structure with a buried source of diameter 2F is shown
in Fig. 2(c) and (d). The source is extended upward to a height
of 40 nm (F) so that the gate and source are not shorted together.
The diameter of the extension region is also F (40 nm). Drain
is at the top having a diameter and length of F (40 nm). Device
simulations are carried out for the proposed GAA structure on
Silvaco Atlas [17] (TCAD device simulator) for gate/channel
lengths (Lch ) of 40 (F), 80 (2F), and 120 nm (3F). The buried
oxide layer has not been shown for simplicity.
Source, drain, and source extension regions are heavily doped
with a uniform n-type doping concentration of 1 1020 cm3 .
The channel is uniformly doped with p-type impurity concentration of 1 1016 cm3 . The work function and gate oxide thickness of the cylindrical gate are 4.61 eV and 2 nm, respectively.
The heavily doped extension region ensures a high current drive.
220
212
213
214
215
216
217
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
TABLE II
TCAD RESULTS OF GAA DEVICE FOR DIFFERENT GATE LENGTHS
Lch
40
80
120
Vt
l i n (V)
DIBL (mV/V)
Io n (A)
Io n /Io f f
SS (mV/decade)
115
22.1
13.6
214.6
194
175.5
3.8103
3.3106
1.5107
103.0
63.4
60.3
0.279
0.300
0.307
TABLE III
TCAD RESULTS OF PLANAR NMOS DEVICE
W (nm) L c h (nm) V t
40
40
80
243
244
245
246
247
248
249
250
251
252
253
254
DIBL (mV/V) Io n (A) Io n /Io f f
0.250
0.275
0.275
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
85.8
72.8
145.6
18.29
142.8
142.7
768.3
294.2
294.2
Fig. 3. Comparison of the ID V G S characteristics of GAA (40 nm nanowire

diameter and L ch = 120 nm) and planar (W = 80 nm and L ch = 120 nm)
NMOS.
A. TCAD Analysis of the Proposed Structure

The ID VDS and ID VGS characteristics are analyzed using 3-D TCAD device simulation of the proposed structure.
Threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope (SS), and Ion /Io are calculated for Lch of 40,
80, and 120 nm. The method used for threshold voltage extraction is the linear extrapolation method in the linear region,
which is also commonly known as maximum transconductance method [18], [19]. The magnitude of on current (Ion )
and off current (Io ) are calculated at VGS = VDS = 1.6 V and
VGS = 0, VDS = 1.6 V, respectively. DIBL is defined as the normalized difference in threshold voltages when VDS is changed
from VDS lin and VDS sat
DIBL =
255
354
280
310
SS (mV/decade)
IE
E
Pr E
oo
f
242
80
120
120
l i n (V)
Vt
VDS
Vt sat
sat VDS lin
lin
(6)
where Vt lin and Vt sat are the threshold voltage in the linear
(very low VDS ) and saturation regions, respectively. The values
of VDS sat and VDS lin are 1.6 and 0.05 V, respectively. Vt sat
is the value of VGS on ID VGS curve at VDS = VDS sat required to get the same value of current, which is obtained when
VGS = Vt lin and VDS = VDS lin . The subthreshold slope (SS)
is the change in VGS required to alter the subthreshold drain
current by one decade (ten times). The corresponding results
are shown in Table II. Although the device with 40 nm gate
length has the largest current drive, but it severely suffers from
short channel effects. The DIBL, off-current, and subthreshold
slope parameters are comparatively large for the device with
40 nm gate length. It is because of lower electrostatic gate control at smaller gate length. Evidently, the device with 120 nm
gate length demonstrates the best performance. In order to compare with the conventional STT MRAM cell, TCAD simulations are carried out for planar NMOS transistor also. The gate
work function and oxide thickness of the planar NMOS are
4.61 eV and 1.5 nm, respectively. However, the source, drain,
and channel doping is same as that for GAA NMOS. The performance parameters calculated for planar transistor for different
device dimensions are placed in Table III. The performance of
the planar transistor is poor, especially for small gate length,
Fig. 4. Comparison of |ID | |V D S | characteristics with top as drain and

bottom as drain operation for the GAA NMOS of L ch = 120 nm.
due to large short channel effects that are measured at a high

VDD of 1.6 V. Although, the short channel effects of the planar
NMOS can be reduced by decreasing the source and drain doping concentration, but that will reduce Ion also. A comparison
of ID VGS characteristics is shown in Fig. 3, which confirms
that GAA NMOS has much lower off current than the planar
NMOS devices.
For SL = VDD and BL = 0, the vertical GAA transistor
would be operating with drain as bottom and top as source.
Therefore, the ID VDS characteristics of the proposed structure
should also be analyzed with bottom [buried source in Fig. 2(d)]
as drain. However, Fig. 4 clearly shows a minute difference
between |ID | |VDS | characteristics under the two modes of
operation. This difference can be safely neglected in the subsequent analysis and the device can be considered to be having
symmetric IV characteristics.
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
B. DC Load Line Analysis
294
In this section, dc load line analysis is carried out to ascertain

that the vertical GAA transistor provides sufficient drive current for proper operation of the proposed STT-MRAM cell [20].
The ID VDS characteristics obtained from TCAD simulation
for the proposed structure [see Fig. 2(d)] are used for the load
line analysis. Moreover, ID VDS characteristics obtained from
TCAD simulations of planar NMOS with 120 nm gate/channel
295
296
297
298
299
300
301
302
303
304
305
306
307
308
length are also included in the load line analysis. The minimum width (W = F = 40 nm) planar NMOS has a low Ion as
compared to GAA (Tables II and III). Hence, the comparison
would be more appropriate with a planar NMOS of width 80 nm
(W = 2F = 80 nm), that has Ion comparable to the GAA device. The value of VDS , as deduced from Fig. 2(a) and (b) is
expressed as
VDS = VDD ID RM TJ
309
Q4 310
311
312
(7)
where RM TJ is the resistance of MTJ. The RM TJ and TMR

parameters vary considerably with bias voltage across the MTJ,
when in AP state [14], [15]. The AP resistance (RAP ) and TMR
of an MTJ are expressed as
RAP (Vbias ) = RP {1 + TMR(Vbias )}
TMR(0)
TMR(Vbias ) =
2 /V 2 )
1 + (Vbias
h
(8)
348
C. BSIM CG Model Calibration
349
BSIM CG is a part of the combined multigate (MG) model

BSIM CMG coded in Verilog-A, which captures the behavior of
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
350
all MG and GAA transistors [21], [22]. Appendix I depicts the

steps along with parameters to calibrate BSIM CG according to
TCAD results for the proposed GAA structure (40 nm diameter
and 120 nm gate length). The results of HSPICE simulation of
calibrated model are shown and compared with TCAD results
in Fig. 6(b) and (c). The ID VDS and ID VGS characteristics show that the model closely replicates the TCAD results.
Henceforth, it can be used for further analysis of the proposed
STT MRAM cell.
351
352
353
354
355
356
357
358
359
VI. ANALYSIS OF PROPOSED STT MRAM CELL
360
The proposed STT MRAM cell and conventional cell with

planar transistor are analyzed using transient and dc simulations on HSPICE using calibrated Verilog-A models. The layout of the 10F2 (F = 40 nm) conventional cell is shown in
Fig. 6(c). For the circuit analysis of this 10F 2 planar cell,
BSIMSOI [23] Verilog-A model for planar SOI NMOS is calibrated from TCAD results using the same methodology given in
Appendix I for BSIM CG. The behavior of the two cells during
read is analyzed by performing dc analysis for P read scheme.
The bit stored in the STT MRAM cell (MTJ state) is read out
by applying WWL = VDD and a read voltage (VR ) between
BL and SL. The P read scheme employs BL = VR and SL = 0
during read operation. An optimum read voltage at BL is found
by simultaneous consideration of TMR degradation effect with
MTJ bias voltage and read current difference between P and AP
states of MTJ [24]. Since this read current has to be compared
with a reference current to read the data, the difference in cell
current between 0 and 1 stored cells should be high enough
to be discernible. In addition, TMR should be high during the
read operation, which decreases with an increase in read current (or with an increase in MTJ bias voltage) expressed in (8).
The optimum read voltage is found to be 0.4 V [see Fig. 7(a)]
with a read current difference of 10 A and TMR = 0.75 for
the GAA cell. Fig. 7 (a) also shows that, the read performance
of the two cells is similar. The read margins (RMP ) plotted in
Fig. 7 (b) further confirm the analogous read behavior, which
is expected because both the NMOS devices are in deep linear
region with very little difference currents during read operation.
The dynamic behavior of the proposed cells [see Fig. 8 and Table IV] is verified by a series of write, hold, and read operation
cycle in terms of time at VDD of 1.6 V. The pulsewidth (tPW )
of every cycle is 1 ns with rise and fall times of 0.1 ns. The
initial state of MTJ is considered as AP. The P read operation
is performed keeping WWL = 1.6 V with SL = 0 and BL =
0.4 V [24]. All entries in Table IV are measured at the midpoint
of each cycle or after the write operation is complete, in case of
write cycle.
The dynamic and leakage power of the two cells is obtained
from a transient analysis by keeping WWL equal to 1.6 and 0 V,
respectively. In addition, SL and BL are applied with a square
wave pulse of period 2 ns (50% duty cycle) with amplitude
of 1.6 V (VDD ) in both cases. During the analysis, SL is kept
as logical complement of BL such that when SL = 0, BL =
1.6 V, and vice versa. Again, the initial state of MTJ is considered as AP. Furthermore, write margins are also calculated for
361
IE
E
Pr E
oo
f
347
where Vbias is voltage across MTJ and Vh (= 0.5 V) is the fitting

parameter [14]. Hence, both RAP and TMR reduce with an increase in Vbias as compared to their zero-bias values according
to (8) for Vbias > 0. RAP is considered as 20 k (value of RAP
at Vbias = 0.5) based on the safe assumption that Vbias 0.5 V
at VGS > Vt and VDD 1 V. This assumption is perfectly safe,
because the on resistance (for VGS greater than Vt ) of NMOS
is comparatively lower than the resistance of the MTJ. Thus,
two load lines are drawn corresponding to the loads of RP =
12.73 k and RAP = 20 k as shown in Fig. 5. The point of intersection between the load line and ID VDS curves represents
the operating point of the NMOS. The corresponding value of
ID should be high enough for providing a drive current larger
than the critical switching current of MTJ in either direction. The
dotted lines show the critical MTJ switching currents ILH0 =
72 A and IHL0 = 28 A in Fig. 5. As expected, the primary
cause of concern is the comparatively high critical switching
current required for P to AP switching (ILH0 ) [15]. The current
ILH0 is higher, since the electrons reflected from the pinned
layer switch the state of MTJ. The points of intersection (operating points) of ID VDS curve with the P and AP load lines
are worth noting. The drain current ID at the operating point
corresponding to load RP (RAP ) should be higher than the
critical switching current ILH0 (IHL0 ). At VGS = 1.2, ID (for
GAA) barely overcomes ILH0 (P load line), while at VGS equal
to 1.4 and 1.6 V, ID (for GAA) exceeds ILH0 by 19 and 36 A,
respectively. Hence, the load line analysis shows that vertical
GAA transistor can provide a sufficient drive current for switching MTJ in either direction when VDD 1.4 V. Besides, it is
evident from Fig. 5 that, to achieve a drive current close to
GAA, the planar transistor of width 80 nm (2F) is required and
the minimum width transistor (W = F = 40 nm) does not provide sufficient current driving capability. The cell area for such
a cell is exorbitantly higher, i.e., 10F 2 , the layout of which is
shown in Fig. 6(a).
313
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
IE
E
Pr E
oo
f
Fig. 5. Load-line analysis of vertical GAA (40 nm nanowire diameter and L ch = 120 nm) and planar NMOS (gate length of 120 nm) at different V G S (= V D D )
corresponding to P and AP resistance as load. (a) For V G S = 1.6 V, (b) for V G S = 1.4 V, and (c) for V G S = 1.2. Red and black lines represent P and AP load
lines, respectively, in each of (a), (b), and (c). IL H 0 and IH L 0 are 72 and 28 A, respectively.
Fig. 6. (a) Cell layout of conventional 10F 2 STT MRAM cell with planar select device. (b) Comparison of ID V G S characteristics of calibrated BSIM CG
with TCAD results at V D S = 1.6 V. (c) Comparison of ID V D S characteristics of calibrated BSIM-CG with TCAD results.
Fig. 7. (a) Variation of TMR and read current difference with read voltage (WWL = V D D = 1.6 V and SL = 0 V). (b) Variation of read margin (RM P )
and write margins WM P with WWL = V D D . The analysis is done keeping BL = 0.4 V and SL = 0 V with the initial state of MTJ considered as AP.
(c) Comparison of dynamic power dissipation (with WWL = 1.6 V) of the two cells in terms of V D D .
TABLE IV
TIMING ANALYSIS OF THE PROPOSED 4F2 GAA CELL AND 10F2 PLANAR CELL
Bias voltages
Planar
Hold (initial state AP)
Write 0
Hold
Read 0 (P read)
Hold
Write 1
Hold
Read 1 (P read)
Hold
SL
BL
WWL
I c e l l (A)
R M T J (k)
TMR
MTJ State
I c e l l (A)
R M T J (k)
TMR
MTJ state
0
0
0
0
27.1
1.13
AP (1)
0
27.1
1.13
AP (1)
0
1.6 V
1.6 V
55.1
12.73
P (0)
61.3
12.73
P (0)
0
0
0
0
12.73
P (0)
0
12.73
P (0)
0
0.4 V
1.6 V
25.2
12.73
P(0)
26.5
12.73
P(0)
0
0
0
0
27.1
P(0)
0
12.73
P(0)
1.6V
0
1.6V
92
14.46
0.14
AP (1)
95.8
14.41
0.13
AP (1)
0
0
0
0
27.1
1.13
AP (1)
0
27.1
1.13
AP (1)
0
0.4 V
1.6 V
15.7
22.4
0.76
AP (1)
16.3
22.20
0.74
AP (1)
0
0
0
0
27.1
1.13
AP (1)
0
27.1
1.13
AP (1)
Fig. 8. Timing diagram showing successful operation of the proposed 4F 2

STT MRAM cell at V D D = 1.6 V.
423
the proposed 4F 2 and conventional 10F 2 cell. The corresponding results are tabulated in Table V. Undoubtedly, the proposed
cell demonstrates a better performance in terms of power dissipation and write margins. The leakage power dissipation for
the proposed cell is four to five orders of magnitude lower than
conventional cell (when the cell is not selected for writing). The
dynamic power dissipation at WWL = 1.6 V (VDD ) is higher;
although, here the point of consideration is that the dynamic
power always has a tradeoff with the P and AP write margins
(write currents). There is a larger tradeoff window between the
write margin and dynamic power dissipation in the case of proposed cell with GAA device, as it can operate with VDD as low
as 1.3 V (at tPW = 1 ns) by sacrificing the write margins. It is
clearly observed in Fig. 7(b) that the planar cell cannot operate
correctly at VDD = 1.3 V for tPW = 1 ns. Moreover, a comparison of the dynamic power dissipation between the cells in
terms of VDD in Fig. 7(c) shows that the proposed cell can be
optimized for low-power operation also.
424
VII. CONCLUSION
425
The proposed STT MRAM cell offers better performance

over the conventional STT MRAM cell from all perspectives.
The biggest improvements are in terms of area and leakage
power dissipation. The proposed cell occupies a much smaller
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
426
427
428
area of 4F 2 with a 60% reduction in area from its conventional

counterpart, and still offers a much better performance. Hence,
to achieve high density STT MRAMs, the 4F 2 cell with vertical
GAA transistor is potentially better solution than 610 F2 cell
with planar transistor. The leakage power dissipation of the proposed cell is comparatively much smaller, when the cell is not
selected for writing (WWL = 0 V ). In addition, the proposed
cell shows excellent write margins and can be optimized for
low power operation. Despite the high write currents, the read
behavior is not compromised, as the proposed cell offers good
read stability and high read margins. Moreover, the read disturb
rate is lower than 107 up to read voltage VR = 0.4 V with
a read current difference of 10 A between 0 (P) and 1 (AP)
stored cells. These advantages have been possible by the virtue
of vertical GAA NMOS. The proposed select device offers excellent gate control (Io = 12 pA) and high current drive along
with the attainment of maximum 2-D array density. These improvements should proliferate even more with subsequent down
scaling of the STT MRAM cell.
IE
E
Pr E
oo
f
GAA
Parameter
APPENDIX I
BSIM CG MODEL CALIBRATION
The important parameters and model calibration methodology for configuring BSIM CG for cylindrical GAA operation
are classified and discussed as follows:
A. Geometry and Material Parameters: The geometry
and material parameters of BSIM CMG are set for a vertical
GAA device operation, according to the parameters used for
TCAD simulation (see Table VI).
B. Threshold Voltage Calibration: The threshold voltage
of BSIM CG is expressed as
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
Vth = Vth0 + Vth,SCE + Vth,DIBL + DVTSHIFT (A1)
where Vth0 is the threshold voltage of the model based on surface potential calculations. Vth,SCE is the threshold voltage
degradation due to short channel effects, Vth,DIBL is used
to model the effect of drain voltage on threshold voltage, and
DVTSHIFT is to handle any additional shift in Vth [21].
The model equation for Vth,SCE in BSIM CG [21] is
Vth,SCE =
0.5DVT0
(Vbi st )
cosh {DVT1 (Le /)} 1
(A2)
458
459
460
461
462
463
TABLE V
COMPARISON BETWEEN PROPOSED CELL AND 10F2 PLANAR NMOS
Select Device
GAA
Planar
W M P (A)
W M A P (A)
t p (ns)
t A P (ns)
Power (pW) W W L = 0 V
Power (W) W W L = 1.6 V
23.3
17.6
34.0
29.0
0.43
0.52
0.25
0.32
16.2
1140
112.4
107.0
TABLE VII
THRESHOLD VOLTAGE PARAMETERS
TABLE VI
GEOMETRY AND MATERIAL PARAMETERS
GEOMOD
BULKMOD
ASYMMMOD
COREMOD
L
D
EOT
NGATE
NSD
PHIG
NBODY
Value
Description[21]
3
0
1
0
120 nm
40 nm
2 nm
0
1 1020 cm3
4.61 eV
1 1016 cm3
Cylindrical GAA
SOI substrate
Asymmetric device
Surface potential model
Gate length
Gate diameter
Gate oxide thickness
Metal gate
S/D doping concentration
Gate work function
Channel doping
BSIM Model Parameter
VALUE
Description [21]
DVT0
DVT1
ETA0
DSUB
DVTP0
DVTP1
DVTSHIFT
2.2
0.177
1
0.80
0
0
0
SCE coefficient
SCE exponent coefficient
DIBL coefficient
DIBL exponent coefficient
Coefficient for drain-induced V t h shift
Exponent coefficient for drain-induced V t h shift
Additional V t h shift handle
TABLE VIII
MOBILITY AND DRAIN CURRENT PARAMETERS
IE
E
Pr E
oo
f
464
465
466
467
468

where
Vbi = (kB T /q) ln NSD (nb o dy /n2i ) ,
and
=
st = 0.4 + (kB T /q) ln(nb o dy /ni ),

(si R EOT/2ox ) {1 + (R ox /2si EOT)}.
Le is the effective channel length. The model equation for
Vth,DIBL in BSIM CG is expressed as [22]
Vth,DIBL =
0.5ETA0
VDS
cosh (DSUB (Le /)) 1
+ DVTP0 VDS DVTP1

469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
U0
IDS0MULT
U0MULT
TCAD simulation is carried to calculate Vth,SCE and

Vth,DIBL and then (A1)(A3) are used to set threshold voltage
parameters accordingly (see Table VII).
C. Mobility and Drain Current Parameters: Average low
field mobility is calculated using TCAD simulations for the
on state (VGS > Vth and VDS = 0.05) of the device. The low
field mobility is found to be 650 cm2 /(Vs). Further, U0MULT
(multiplier to mobility) and IDS0MULT (multiplier to source
drain channel current) are set, which are dedicated to variability
modeling and can be set by the user appropriately [21]. Mobility
and drain current parameters are shown in Table VIII.
D. Parasitic Capacitance, Subthreshold, and Leakage
Current Parameters: AC analysis is done at a frequency of
1 MHz with a low VDS (load line analysis in Section V shows
that the NMOS will be invariably in the linear region of operation). Hence, at |VDS | = 0.2 V, the average values of capacitances are calculated. The average gate to source capacitance
CGS and gate-to-drain capacitances CGD are found to be 0.087
and 0.1 fF/m, respectively. The parameters concerned with
parasitic capacitance and subthreshold conduction are placed in
Table IX.
Description [21]
650 cm2 /Vs

5
0.62
Low field mobility

Multiplier to sourcedrain channel current
Multiplier to mobility
TABLE IX
PARASITIC CAPACITANCE, SUBTHRESHOLD, AND LEAKAGE CURRENT
PARAMETERS
(A3)
Value
CGEOMOD
CGEO1SW
COVS
COVD
DVT1SS
GIDLMOD
AGISL
AGIDL
Value
Description [21]
1
1
0.1 fF
0.087 fF
1.0234
1
1.05 1015
1.05 1015
Parasitic capacitance model selector

Capacitance unit selector
Constant ate to source overlap capacitance
Constant gate to drain overlap capacitance
Subthreshold swing exponent coefficient
GIDL/GISL model selector
Preexponential coefficient for GISL
Preexponential coefficient for GIDL
REFERENCES
[1] ERD. (2011). International technology road map for semiconductors [Online]. Available: http://www.itrs.net
[2] T. Schloesser et al., 6F2 buried wordline DRAM cell for 40 nm and
beyond, in Proc. IEEE IEDM08, San Francisco, CA, USA, pp. 14,
Dec. 2008.
[3] H. Chung et al., Novel 4F2 DRAM cell with vertical pillar transistor(VPT), in Proc. IEEE ESSDRC, Helsinki, Finland, pp. 211214, Sep.
2011.
[4] Z. Fang et al., Fully CMOS-compatible 1T1R integration of vertical
nanopillar GAA transistor and oxide-based RRAM cell for high-density
nonvolatile memory application, IEEE Trans. Electron Devices, vol. 60,
no. 3, pp. 11081113, Mar. 2013.
[5] D.-L. Kwong et al., Vertical silicon nanowire platform for low power
electronics and clean energy applications, J. Nanotechnol., vol. 2012,
pp. 121, 2012.
[6] T. Kawahara, K. Ito, R. Takemura, and H. Ohno, Spin-transfer torque
RAM technology: Review and prospect, Microelectron. Reliab., vol. 52,
no. 4, pp. 613627, Apr. 2012.
490
491
492
493
494
495 Q5
496
497
498
499
500
501
502
503
504
505
506
507
508
[7] S. Ikeda et al., Recent progress of perpendicular anisotropy magnetic

tunnel junction for non-volatile VLSI, Spin (World Sci.), vol. 2, no. 3,
pp. 1240003-11240003-12, Dec. 2012.
[8] S. Ikeda et al., Magnetic tunnel junctions for spintronic memories and
beyond, IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 9911002,
2007.
[9] PIDS. (2001). International technology roadmap for semiconductors [Online]. Available: http://www.itrs.net
[10] Y. Song et al., Performance breakthrough in gate-all-around nanowire nand p-type MOSFETs fabricated on bulk silicon substrate, IEEE Trans.
Electron Devices, vol. 59, no. 7, pp. 18851890, Jul. 2012.
[11] K. Lee, J. J. Sapan, S. H. Kang, and E. E. Fullerton, Perpendicular
magnetization of CoFeB on single-crystal MgO, J. Appl. Phys., vol. 109,
no. 12, pp. 123910-1123910-3, Jun. 2011.
[12] S. Ikeda et al., A perpendicular-anisotropy CoFeB-MgO magnetic tunnel
junction, Nat. Mater., vol. 9, no. 9, pp. 721724, Sep. 2010.
[13] M. Gajek et al., Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy, Appl. Phys. Lett., vol. 100, no. 13,
pp. 1324081-132408-3, Mar. 2012.
[14] Y. Zhang et al., Compact modeling of perpendicular-anisotropy
CoFeB/MgO magnetic tunnel junctions, IEEE Trans. Electron Devices,
vol. 59, no. 3, pp. 819826, Mar. 2012.
[15] D. D. Tang and Y. J. Lee, Magnetic memory fundamentals and technology,
1st ed. Cambridge U.K.: Cambridge Univ. Press, 2010, ch. 36.
[16] J. Li et al., Design paradigm for robust spin-torque transfer magnetic
RAM (STT MRAM) from circuit/architecture perspective, IEEE Trans.
VLSI, vol. 18, no. 12, pp. 17101723, Dec. 2010.
[17] Silvaco Inc. (2012, Mar.). ATLAS users manual [Online]. Available:
www.silvaco.com
[18] L. Dobrescu et al., Threshold voltage extraction methods for MOS transistors, in Proc. CAS 2000 Int. Semicond. Conf., 23rd ed., 2000, vol. 1,
no. 2, pp. 371374.
[19] A. Bazigos et al., An adjusted constant-current method to determine
saturated and linear mode threshold voltage of MOSFETs, IEEE Trans.
Electron Devices, vol. 58, no. 11, pp. 37513758, Nov. 2011.
[20] X. Fong, S. H. Choday, and K. Roy, Bit-cell level optimization for
non-volatile memories using magnetic tunnel junctions and spin-transfer
torque switching, IEEE Trans. Nanotechnol., vol. 11, no. 1, pp. 172181,
Jan. 2012.
[21] V. Sriramkumar et al., BSIM-CMG 107.0.0 Multi-gate MOSFET Compact
Model: Technical Manual, Dept. Elect. Eng. Comp. Sci., Univ. California,
Berkeley, USA, 2013.
[22] D. Lu, C. H Lin, A. Niknejad, and C. Hu, Multi-gate MOSFET compact model BSIM-MG, in Compact Modeling, G. Gidenblat, Ed. The
Netherlands: Springer, pp. 395429, 2010.
[23] N. Paydavosi, A. Niknejad, C. Hu, BSIMSOIv4.5.0 MOSFET MODEL
Users Manual, Dept. Elect. Eng. Comp. Sci., Univ. California, Berkeley,
USA, 2013.
[24] T. Kawahara et al., 2 Mb SPRAM (spin-transfer torque RAM) with
bit-by-bit bi-directional current write, IEEE Trans. Solid State Circuits,
vol. 43, no. 1, pp. 109120, 2008.
Shivam Verma (S13) received the M.Tech. degree

in microelectronics from IIT BHU, Varanasi, India,
in 2012. He is currently working toward the Ph.D.
degree from the Indian Institute of Technology Roorkee, Roorkee, India.
His current research interests include STT
MRAMs and all spin logic.
560
561
562
563
564
565
566
567
Shalu Kaundal (S14) received the M.Tech. degree

in microelectronics and VLSI from the Indian Institute of Technology Roorkee, Roorkee, India.
Her current research interests include designing
and modeling of STT MRAMs.
568
569
570
571
572
573
IE
E
Pr E
oo
f
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
Q6 541
542
543
544
545
546
547
548
549
550
551
552
553
Q7 554
555
556
557
558
Q8 559
Brajesh Kumar Kaushik (SM13) received the B.E.

degree in electronics and communication engineering from D.C.R. University of Science and Technology (formerly C. R. State College of Engineering),
Murthal, India, in 1994, and the M.Tech. degree in
engineering systems from Dayalbagh Educational Institute, Agra, India, in 1997, and the Ph.D. degree
under AICTE-QIP scheme from the Indian Institute
of Technology Roorkee, Roorkee, India, in 2007.
He was with Vinytics Peripherals Pvt. Ltd., Delhi,
India, as a Research and Development Engineer in
microprocessor, microcontroller, and DSP processor-based systems. He joined
the Department of Electronics and Communication Engineering, G. B. Pant
Engineering College, Pauri Garhwal, India, as a Lecturer in July 1998, where
he was an Assistant Professor from May 2005 to May 2006 and an Associate
Professor from May 2006 to December 2009. He is currently an Associate
Professor in the Department of Electronics and Communication Engineering,
Indian Institute of Technology Roorkee, Roorkee, India. His current research
interests include in the area of high-speed interconnects, low-power VLSI design, carbon-nanotube-based designs, organic thin film transistor design and
modeling, and spintronics-based devices and circuits.
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
QUERIES
597
598
599
600
601
602
603
604
Q1.
Q2.
Q3.
Q4.
Q5.
Q6.
Q7.
Q8.
Author: Please check the acronym of word line. Is this OK as is or should be WL.
Author: Please check the edited sentence PMA MTJs offer . . . switching. for intended meaning.
Author: Please provide the full form of the acronyms BSIM CG and TMR.
Author: The variable j has been set as R MTJ. Please check.
Author: Please provide all the names of authors in Refs. [2][5], [7], [8], [10], [12][14], [16], [21], and [24].
Author: Please verify Ref. [18] as set.
Author: Please provide the city of the publisher in Ref. [22].
Author: Please provide the month information in Ref. [24].
IE
E
Pr E
oo
f
596
Novel 4F2 Buried-Source-Line STT MRAM Cell

With Vertical GAA Transistor as Select Device
Shivam Verma, Student Member, IEEE, Shalu Kaundal, Student Member, IEEE,
and Brajesh Kumar Kaushik, Senior Member, IEEE
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AbstractSpin transfer torque (STT) magnetic random access

memories (MRAMs) have recently emerged as one of the strongest
contenders for universal memory technology. They have entire
range of features, i.e., high speed, nonvolatility, high density, and
low power, which make them cynosure to every memory designers
notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a
larger amount of embedded memory, the cell size must be reduced.
Therefore, the designs target to attain an optimistic figure of 4F2
(F being the feature size) array density, which is the maximum
achievable two-dimensional (2-D) density. With this objective in
mind, a novel 4F2 buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source
NMOS transistor is proposed. The magnetic tunnel junction (MTJ)
multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ
and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical
GAA device structure. Furthermore, these TCAD results are used
to calibrate the BSIM CG model for cylindrical GAA transistors.
The proposed STT MRAM cell is then analyzed using calibrated
Verilog-A models for perpendicular anisotropy MTJ and vertical
GAA NMOS transistor (BSIM CG). The performance analysis in
terms of read stability, write margins, and power dissipation for
the proposed cell is also presented.
Index TermsMagnetic tunnel junction (MTJ), perpendicular
magnetic anisotropy (PMA), spin transfer torque (STT), vertical
gate all around (GAA).
33
I. INTRODUCTION
34
NALOGOUS to a typical memory system, spin transfer

torque (STT) magnetic random access memory (MRAM)
consists of memory cells connected to form an array. Conventionally, each cell is composed of a storage element as magnetic
tunnel junction (MTJ) and a planar NMOS transistor as select
device. An MTJ consists of two ferromagnetic (FM) layers separated by a nonmagnetic insulator layer. The resistance of MTJ
depends on the magnetization orientations of the two FM layers. Each cell stores data as the resistance state of an MTJ. The
resistance state of MTJ is high (binary 1), if the two FM layers
have antiparallel (AP) alignment of magnetization. Conversely,
35
36
37
38
39
40
41
42
43
44
it is low (binary 0) if the magnetization orientations of the two

FM layers have a parallel (P) alignment.
Embedded memory can be accessed faster as compared to the
external memory; hence, there is a continuously increasing quest
for an on-chip embedded memory. Moreover, in almost every
memory technology, the select devices have been the bottleneck
toward increasing the integration density [1]. Keeping this in
mind, several novel architectures for select devices have been
proposed by researchers working in the area [2][5]. They have
been primarily focusing on vertical select devices to reduce the
cell area. Kawahara et al. [6] analyzed memory cell scalability
for STT MRAMs for various transistor gate widths and informed
the possibility of cell area reduction up to 4F2 with a vertical
select device. However, till date no thorough analysis has been
presented for vertical select device driving STT MRAM cells.
In the conventional in-plane MTJ technology, the switching
current is quite high (2001200 A) [7], [8]. Such high current
drive could not be achieved with minimum-sized transistors,
and hence, scaling toward 4F2 array density per cell is not feasible for STT MRAMs with in-plane MTJs. However, with the
evolution of perpendicular magnetic anisotropy (PMA) MTJs
(with switching current as low as 20100 A or even less), one
can see decent prospects for higher integration density in STT
MRAMs.
The planar MOSFETs have a saturation drive current per
unit width of 900 A/m for high-performance logic [9]. On
the other hand, gate all around (GAA) MOSFETs have been
reported to have a much higher saturation drive current of 2.6
2.9 mA/m per unit diameter [10]. Hence, GAA transistor with
the same diameter should provide a larger drive current. A vertical GAA transistor can act as an ideal select device that can
provide sufficient drive current for efficient switching of an
MTJ. In addition, it will provide a cell size of minimum 2-D
area. Considering these facts, this paper proposes a novel STT
MRAM cell with vertical GAA transistor as select device with
a buried source line (SL) and word line (WWL). The objective
is to improve or retain the other performance specifications (access time read and write margins) with the proposed 4F2 STT
MRAM cell. A detailed analysis is done taking into account
the design considerations and the constraints for an efficient
STT MRAM cell. The proposed cell is also compared with the
minimum-sized cell that can be realized with a planar select
device.
The paper is divided into seven sections, including the introductory section. The architecture and functionality of the
proposed STT MRAM cell are presented in Section II. Section
III analyzes the recent advances in the field of PMA MTJs for
IE
E
Pr E
oo
f
Manuscript received January 29, 2014; accepted July 31, 2014. Date of publication; date of current version. The review of this paper was arranged by
Associate Editor A. Martinez.
The authors are with the Microelectronics and VLSI Group, Department
of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India (e-mail: shivamvermaid@gmail.com;
shalupec@iitr.ac.in; bkk23fec@iitr.ac.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2014.2346790
1536-125X 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Q1
III. ANALYSIS OF PRACTICALLY FABRICATED PMA MTJS
127
PMA MTJs offer low critical currents and higher thermal stability and scalability for STT switching. Lee et al. [11] demonstrated a PMA in Fe-rich CoFeB free layers due to the reduction
of demagnetizing field. The demagnetizing field decreases with
increase in perpendicular anisotropy and eventually leads to a
layer with perpendicular easy axis. The effective demagnetizing
(4Me ) field is expressed as
128
4Me = 4MS Hkp
Fig. 1. (a) Typical STT MRAM cell. (b) Front view of the proposed STT
MRAM cell.
93
94
95
96
97
98
99
100
101
creating Verilog-A models based on experimental results. Section IV focuses on the design considerations (read, write margins and switching probability) of an STT MRAM cell from the
perspective of select devices. Section V describes the TCAD
analysis of the proposed buried source GAA device followed
by the load line analysis. Section VI analyzes and compares
the HSPICE simulation results of the proposed STT MRAM
cell with conventional STT MRAM cell. Finally, in Section
VII, conclusions are drawn based on the analysis done in the
previous sections.
102
II. PROPOSED STT MRAM ARCHITECTURE
103
STT MRAMs have three-dimensional (3-D) integration of

MTJs with conventional CMOS technology. The memory cell
of STT MRAMs has one MTJ and one NMOS select device,
abbreviated as a 1T-1MTJ cell. The structure and properties of
a typical 1T-1MTJ STT MRAM cell can be understood through
Fig. 1(a). The bottom layer (pinned or fixed layer) of an MTJ
has fixed magnetization due to its comparatively high magnetic
coercivity. The top layer of the MTJ is known as free/recording
layer whose magnetization can be switched by the spin torque
acting on it. This spin torque is generated by the electric current, which is spin polarized by the pinned bottom layer. The
directions of current for writing 1 and 0 are shown in Fig. 1(a).
A current from BL to SL would make the magnetization orientation as P (to write a 0). Conversely, a current from SL to
BL would make the magnetization states of two layers as AP (to
write a 1). Besides this, for both the directions, the write currents
need to be above a minimum threshold value for proper switching of the MTJ. The front view of the proposed architecture
is shown in Fig. 1(b) that consists of a PMA MTJ multilayer
structure stacked above the vertical GAA cylindrical NMOS
transistor. The bit line (BL) and buried SL are perpendicular to
the plane of paper, while the WWL is in the plane of the paper.
The proposed GAA structure allows the maximum possible 2-D
array density for STT MRAMs.
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
130
131
132
133
134
(1)
where Hkp is the perpendicular uniaxial anisotropy, Ms is the

magnetization of the layer and 4Ms is the demagnetizing field.
When Hkp exceeds 4Ms , the magnetic moment of CoFeB
has an easy axis perpendicular to the plane of MTJ. The low
switching current density is attributed to Hkp , which cancels
the effect of the out of plane demagnetizing field 4Ms .
Ikeda et al. [7], [12] demonstrated that the performance of
CoFeB/MgO/CoFeB based PMA MTJ with 40 nm diameter
shows excellent properties that includes a high stability factor
(E/KB T = 39) and low switching current (IC0 = 49 A). The
only limitation is large write voltage due to high resistance area
(RA) product, which leaves a scope of improvement. Moreover,
Gajek et al. experimentally analyzed spin torque switching of
PMA MTJ with a diameter of 20 nm. However, the results are
not as promising because of a low TMR (57%) [13]. Hence,
experimental results (shown in Table I) for 40 nm PMA MTJ
are used to develop a Verilog-A model that precisely replicates
the behavior and properties [14].
IE
E
Pr E
oo
f
92
129 Q2
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149 Q3
150
151
152
IV. DESIGN CONSIDERATIONS
153
The select device in a typical memory system allows a memory cell to be accessible for read and write. This section describes
the design considerations of STT MRAMs from the perspective
of select devices. Fig. 2(a) and (b) represents the two states of
the STT MRAM cell before the write operation is performed.
Fig. 2(a) shows the equivalent circuit with polarity of BL and
SL trying to write a 0 into the cell (P write). Likewise, Fig. 2(b)
shows the equivalent circuit with the polarities of BL and SL
trying to write a 1 into the cell (AP write). Hence, an STT
MRAM cell can be viewed as an NMOS transistor with RP or
RAP connected to it as load.
The switching of MTJ depends on the direction of current and
also a minimum threshold current (IC0 ) required for switching
to occur. Hence, the primary consideration is that whether the
select device can provide sufficient drive current for MTJ switching in either direction. The driving current must be sufficiently
high to surmount the switching threshold with high switching
probability for proper operation of the STT MRAM cell.
A write error occurs when the strength of the write current is
not enough, and there is a probability that the desired data may
not be written into the cell [15]. Furthermore, a read disturb
is the unintentional write due to the read current flowing in a
direction; this lowers the switching energy barrier [15], [16].
The write error rate (WER) and read disturb rate (RDR) for
STT-MRAM cell are determined from the switching probability.
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
TABLE I
PRACTICALLY FABRICATED MTJ PARAMETERS FOR CURRENT PULSEWIDTH OF 1 ns
Barrier/recording layer structure (nm)
MgO(0.85)/CoFeB(1.7)/Ta
Diameter
(nm)
40
TMR
(%)
113
RA
(m2 )
16
= E /k B T
R P (k)
R A P (k)
I L H 0 (A)
I H L 0 (A)
V W (V)
Reference
39
12.73
27.1
72
28
0.608
[7]
V W = J C 0 (RA) is the mean write voltage, where J C 0 is the switching current density and RA is the resistance area product. R A P = 27.1 k and TM R = 113% are the
zero-bias values for the PMA MTJ from [7].
are expressed as
200
WMAP = (IWAP0 ILH0 )

(4)
where IHL0 and ILH0 are AP to P and P to AP critical switching
currents, respectively.
Read margin is defined in terms of sensing current (read current) as the normalized difference between the critical switching
current and read current (sensing current) [16]. Analogous to
write margins, different read margins would be defined for P
(RMP ) and AP (RMAP ) reading mechanisms. The read current
during P reading has a direction from free layer (BL) to the
pinned layer (SL) of an MTJ. Likewise, the read current during
AP reading has a direction from pinned layer (SL) to free layer
(BL) of an MTJ. The RMAP and RMP are expressed as
IE
E
Pr E
oo
f
WMP = (IW P0 IHL0 ),
RMP =
Fig. 2. (a) Equivalent circuit of STT MRAM cell before MTJ switching with
AP resistance as load. (b) Equivalent circuit of STT MRAM cell before MTJ
switching with P resistance as load. (c) Top view of the vertical GAA NMOS
device. (d) Front view of the vertical GAA NMOS device.
179
WER and RDR are expressed as

RDR = PSW ,
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
WER = 1 PSW
(2)
where PSW is the probability of occurrence of switching below

critical switching current (IC0 ) that is expressed as [15]

E
tPW
I
PSW = 1 exp
exp
(3)
1
0
kB T
IC0
where tPW is the current pulsewidth, 0 is the attempt time, IC0

is the critical current required for switching, and E/kB T is the
Boltzmanns factor.
The drain current (ID ) should be very small, when the cell
has not been selected (WWL = 0) for reading or writing. The
current through the cell with WWL = 0 should be small enough
so that the switching probability is negligible, preferably below
109 [15]. This means that the select device should offer very
small off the current even though BL or SL is equal to VDD .
Write margin is defined as the difference between the writing
current and critical switching current of an MTJ [16]. The write
current must be sufficiently high to obtain a cell with large
write margins and small switching time. Different write margins
are defined for P (WMP ) or AP (WMAP ) write into the cell. The
write current for P writing IW P0 should have a direction from
free layer (BL) to the pinned layer (SL) of an MTJ. Conversely,
the write current for AP writing IWAP0 should have a direction
from pinned layer (SL) to free layer (BL). WMP and WMAP
IHL0 IP0
,
IHL0
RMAP =
ILH0 IAP0
ILH0
201
202
203
204
205
206
207
208
209
210
211
(5)
where IP0 and IAP0 are the read currents during P and AP
reading, respectively.
Write access time (tP and tAP ) is defined as the time required
for switching the state of MTJ at the particular write current
and write current pulsewidth. The switching time also depends
on the switching threshold at that write current pulse duration
(tPW ) [14].
218
V. VERTICAL GAA TRANSISTOR AS SELECT DEVICE
219
Conventionally, the overall area of the STT MRAM cell has

been dominated by the select device [1]. The proposed structure
allows us to accommodate the MTJ and select device within the
same area through 3-D stacking. In this section, the proposed
select device structure is thoroughly analyzed. The analysis has
been carried out for feature size F = 40 nm, which is same as
the diameter of the MTJ to keep the overall cell area 4F 2 . The
proposed structure with a buried source of diameter 2F is shown
in Fig. 2(c) and (d). The source is extended upward to a height
of 40 nm (F) so that the gate and source are not shorted together.
The diameter of the extension region is also F (40 nm). Drain
is at the top having a diameter and length of F (40 nm). Device
simulations are carried out for the proposed GAA structure on
Silvaco Atlas [17] (TCAD device simulator) for gate/channel
lengths (Lch ) of 40 (F), 80 (2F), and 120 nm (3F). The buried
oxide layer has not been shown for simplicity.
Source, drain, and source extension regions are heavily doped
with a uniform n-type doping concentration of 1 1020 cm3 .
The channel is uniformly doped with p-type impurity concentration of 1 1016 cm3 . The work function and gate oxide thickness of the cylindrical gate are 4.61 eV and 2 nm, respectively.
The heavily doped extension region ensures a high current drive.
220
212
213
214
215
216
217
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
TABLE II
TCAD RESULTS OF GAA DEVICE FOR DIFFERENT GATE LENGTHS
Lch
40
80
120
Vt
l i n (V)
DIBL (mV/V)
Io n (A)
Io n /Io f f
SS (mV/decade)
115
22.1
13.6
214.6
194
175.5
3.8103
3.3106
1.5107
103.0
63.4
60.3
0.279
0.300
0.307
TABLE III
TCAD RESULTS OF PLANAR NMOS DEVICE
W (nm) L c h (nm) V t
40
40
80
243
244
245
246
247
248
249
250
251
252
253
254
DIBL (mV/V) Io n (A) Io n /Io f f
0.250
0.275
0.275
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
85.8
72.8
145.6
18.29
142.8
142.7
768.3
294.2
294.2
Fig. 3. Comparison of the ID V G S characteristics of GAA (40 nm nanowire

diameter and L ch = 120 nm) and planar (W = 80 nm and L ch = 120 nm)
NMOS.
A. TCAD Analysis of the Proposed Structure

The ID VDS and ID VGS characteristics are analyzed using 3-D TCAD device simulation of the proposed structure.
Threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope (SS), and Ion /Io are calculated for Lch of 40,
80, and 120 nm. The method used for threshold voltage extraction is the linear extrapolation method in the linear region,
which is also commonly known as maximum transconductance method [18], [19]. The magnitude of on current (Ion )
and off current (Io ) are calculated at VGS = VDS = 1.6 V and
VGS = 0, VDS = 1.6 V, respectively. DIBL is defined as the normalized difference in threshold voltages when VDS is changed
from VDS lin and VDS sat
DIBL =
255
354
280
310
SS (mV/decade)
IE
E
Pr E
oo
f
242
80
120
120
l i n (V)
Vt
VDS
Vt sat
sat VDS lin
lin
(6)
where Vt lin and Vt sat are the threshold voltage in the linear
(very low VDS ) and saturation regions, respectively. The values
of VDS sat and VDS lin are 1.6 and 0.05 V, respectively. Vt sat
is the value of VGS on ID VGS curve at VDS = VDS sat required to get the same value of current, which is obtained when
VGS = Vt lin and VDS = VDS lin . The subthreshold slope (SS)
is the change in VGS required to alter the subthreshold drain
current by one decade (ten times). The corresponding results
are shown in Table II. Although the device with 40 nm gate
length has the largest current drive, but it severely suffers from
short channel effects. The DIBL, off-current, and subthreshold
slope parameters are comparatively large for the device with
40 nm gate length. It is because of lower electrostatic gate control at smaller gate length. Evidently, the device with 120 nm
gate length demonstrates the best performance. In order to compare with the conventional STT MRAM cell, TCAD simulations are carried out for planar NMOS transistor also. The gate
work function and oxide thickness of the planar NMOS are
4.61 eV and 1.5 nm, respectively. However, the source, drain,
and channel doping is same as that for GAA NMOS. The performance parameters calculated for planar transistor for different
device dimensions are placed in Table III. The performance of
the planar transistor is poor, especially for small gate length,
Fig. 4. Comparison of |ID | |V D S | characteristics with top as drain and

bottom as drain operation for the GAA NMOS of L ch = 120 nm.
due to large short channel effects that are measured at a high

VDD of 1.6 V. Although, the short channel effects of the planar
NMOS can be reduced by decreasing the source and drain doping concentration, but that will reduce Ion also. A comparison
of ID VGS characteristics is shown in Fig. 3, which confirms
that GAA NMOS has much lower off current than the planar
NMOS devices.
For SL = VDD and BL = 0, the vertical GAA transistor
would be operating with drain as bottom and top as source.
Therefore, the ID VDS characteristics of the proposed structure
should also be analyzed with bottom [buried source in Fig. 2(d)]
as drain. However, Fig. 4 clearly shows a minute difference
between |ID | |VDS | characteristics under the two modes of
operation. This difference can be safely neglected in the subsequent analysis and the device can be considered to be having
symmetric IV characteristics.
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
B. DC Load Line Analysis
294
In this section, dc load line analysis is carried out to ascertain

that the vertical GAA transistor provides sufficient drive current for proper operation of the proposed STT-MRAM cell [20].
The ID VDS characteristics obtained from TCAD simulation
for the proposed structure [see Fig. 2(d)] are used for the load
line analysis. Moreover, ID VDS characteristics obtained from
TCAD simulations of planar NMOS with 120 nm gate/channel
295
296
297
298
299
300
301
302
303
304
305
306
307
308
length are also included in the load line analysis. The minimum width (W = F = 40 nm) planar NMOS has a low Ion as
compared to GAA (Tables II and III). Hence, the comparison
would be more appropriate with a planar NMOS of width 80 nm
(W = 2F = 80 nm), that has Ion comparable to the GAA device. The value of VDS , as deduced from Fig. 2(a) and (b) is
expressed as
VDS = VDD ID RM TJ
309
Q4 310
311
312
(7)
where RM TJ is the resistance of MTJ. The RM TJ and TMR

parameters vary considerably with bias voltage across the MTJ,
when in AP state [14], [15]. The AP resistance (RAP ) and TMR
of an MTJ are expressed as
RAP (Vbias ) = RP {1 + TMR(Vbias )}
TMR(0)
TMR(Vbias ) =
2 /V 2 )
1 + (Vbias
h
(8)
348
C. BSIM CG Model Calibration
349
BSIM CG is a part of the combined multigate (MG) model

BSIM CMG coded in Verilog-A, which captures the behavior of
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
350
all MG and GAA transistors [21], [22]. Appendix I depicts the

steps along with parameters to calibrate BSIM CG according to
TCAD results for the proposed GAA structure (40 nm diameter
and 120 nm gate length). The results of HSPICE simulation of
calibrated model are shown and compared with TCAD results
in Fig. 6(b) and (c). The ID VDS and ID VGS characteristics show that the model closely replicates the TCAD results.
Henceforth, it can be used for further analysis of the proposed
STT MRAM cell.
351
352
353
354
355
356
357
358
359
VI. ANALYSIS OF PROPOSED STT MRAM CELL
360
The proposed STT MRAM cell and conventional cell with

planar transistor are analyzed using transient and dc simulations on HSPICE using calibrated Verilog-A models. The layout of the 10F2 (F = 40 nm) conventional cell is shown in
Fig. 6(c). For the circuit analysis of this 10F 2 planar cell,
BSIMSOI [23] Verilog-A model for planar SOI NMOS is calibrated from TCAD results using the same methodology given in
Appendix I for BSIM CG. The behavior of the two cells during
read is analyzed by performing dc analysis for P read scheme.
The bit stored in the STT MRAM cell (MTJ state) is read out
by applying WWL = VDD and a read voltage (VR ) between
BL and SL. The P read scheme employs BL = VR and SL = 0
during read operation. An optimum read voltage at BL is found
by simultaneous consideration of TMR degradation effect with
MTJ bias voltage and read current difference between P and AP
states of MTJ [24]. Since this read current has to be compared
with a reference current to read the data, the difference in cell
current between 0 and 1 stored cells should be high enough
to be discernible. In addition, TMR should be high during the
read operation, which decreases with an increase in read current (or with an increase in MTJ bias voltage) expressed in (8).
The optimum read voltage is found to be 0.4 V [see Fig. 7(a)]
with a read current difference of 10 A and TMR = 0.75 for
the GAA cell. Fig. 7 (a) also shows that, the read performance
of the two cells is similar. The read margins (RMP ) plotted in
Fig. 7 (b) further confirm the analogous read behavior, which
is expected because both the NMOS devices are in deep linear
region with very little difference currents during read operation.
The dynamic behavior of the proposed cells [see Fig. 8 and Table IV] is verified by a series of write, hold, and read operation
cycle in terms of time at VDD of 1.6 V. The pulsewidth (tPW )
of every cycle is 1 ns with rise and fall times of 0.1 ns. The
initial state of MTJ is considered as AP. The P read operation
is performed keeping WWL = 1.6 V with SL = 0 and BL =
0.4 V [24]. All entries in Table IV are measured at the midpoint
of each cycle or after the write operation is complete, in case of
write cycle.
The dynamic and leakage power of the two cells is obtained
from a transient analysis by keeping WWL equal to 1.6 and 0 V,
respectively. In addition, SL and BL are applied with a square
wave pulse of period 2 ns (50% duty cycle) with amplitude
of 1.6 V (VDD ) in both cases. During the analysis, SL is kept
as logical complement of BL such that when SL = 0, BL =
1.6 V, and vice versa. Again, the initial state of MTJ is considered as AP. Furthermore, write margins are also calculated for
361
IE
E
Pr E
oo
f
347
where Vbias is voltage across MTJ and Vh (= 0.5 V) is the fitting

parameter [14]. Hence, both RAP and TMR reduce with an increase in Vbias as compared to their zero-bias values according
to (8) for Vbias > 0. RAP is considered as 20 k (value of RAP
at Vbias = 0.5) based on the safe assumption that Vbias 0.5 V
at VGS > Vt and VDD 1 V. This assumption is perfectly safe,
because the on resistance (for VGS greater than Vt ) of NMOS
is comparatively lower than the resistance of the MTJ. Thus,
two load lines are drawn corresponding to the loads of RP =
12.73 k and RAP = 20 k as shown in Fig. 5. The point of intersection between the load line and ID VDS curves represents
the operating point of the NMOS. The corresponding value of
ID should be high enough for providing a drive current larger
than the critical switching current of MTJ in either direction. The
dotted lines show the critical MTJ switching currents ILH0 =
72 A and IHL0 = 28 A in Fig. 5. As expected, the primary
cause of concern is the comparatively high critical switching
current required for P to AP switching (ILH0 ) [15]. The current
ILH0 is higher, since the electrons reflected from the pinned
layer switch the state of MTJ. The points of intersection (operating points) of ID VDS curve with the P and AP load lines
are worth noting. The drain current ID at the operating point
corresponding to load RP (RAP ) should be higher than the
critical switching current ILH0 (IHL0 ). At VGS = 1.2, ID (for
GAA) barely overcomes ILH0 (P load line), while at VGS equal
to 1.4 and 1.6 V, ID (for GAA) exceeds ILH0 by 19 and 36 A,
respectively. Hence, the load line analysis shows that vertical
GAA transistor can provide a sufficient drive current for switching MTJ in either direction when VDD 1.4 V. Besides, it is
evident from Fig. 5 that, to achieve a drive current close to
GAA, the planar transistor of width 80 nm (2F) is required and
the minimum width transistor (W = F = 40 nm) does not provide sufficient current driving capability. The cell area for such
a cell is exorbitantly higher, i.e., 10F 2 , the layout of which is
shown in Fig. 6(a).
313
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
IE
E
Pr E
oo
f
Fig. 5. Load-line analysis of vertical GAA (40 nm nanowire diameter and L ch = 120 nm) and planar NMOS (gate length of 120 nm) at different V G S (= V D D )
corresponding to P and AP resistance as load. (a) For V G S = 1.6 V, (b) for V G S = 1.4 V, and (c) for V G S = 1.2. Red and black lines represent P and AP load
lines, respectively, in each of (a), (b), and (c). IL H 0 and IH L 0 are 72 and 28 A, respectively.
Fig. 6. (a) Cell layout of conventional 10F 2 STT MRAM cell with planar select device. (b) Comparison of ID V G S characteristics of calibrated BSIM CG
with TCAD results at V D S = 1.6 V. (c) Comparison of ID V D S characteristics of calibrated BSIM-CG with TCAD results.
Fig. 7. (a) Variation of TMR and read current difference with read voltage (WWL = V D D = 1.6 V and SL = 0 V). (b) Variation of read margin (RM P )
and write margins WM P with WWL = V D D . The analysis is done keeping BL = 0.4 V and SL = 0 V with the initial state of MTJ considered as AP.
(c) Comparison of dynamic power dissipation (with WWL = 1.6 V) of the two cells in terms of V D D .
TABLE IV
TIMING ANALYSIS OF THE PROPOSED 4F2 GAA CELL AND 10F2 PLANAR CELL
Bias voltages
Planar
Hold (initial state AP)
Write 0
Hold
Read 0 (P read)
Hold
Write 1
Hold
Read 1 (P read)
Hold
SL
BL
WWL
I c e l l (A)
R M T J (k)
TMR
MTJ State
I c e l l (A)
R M T J (k)
TMR
MTJ state
0
0
0
0
27.1
1.13
AP (1)
0
27.1
1.13
AP (1)
0
1.6 V
1.6 V
55.1
12.73
P (0)
61.3
12.73
P (0)
0
0
0
0
12.73
P (0)
0
12.73
P (0)
0
0.4 V
1.6 V
25.2
12.73
P(0)
26.5
12.73
P(0)
0
0
0
0
27.1
P(0)
0
12.73
P(0)
1.6V
0
1.6V
92
14.46
0.14
AP (1)
95.8
14.41
0.13
AP (1)
0
0
0
0
27.1
1.13
AP (1)
0
27.1
1.13
AP (1)
0
0.4 V
1.6 V
15.7
22.4
0.76
AP (1)
16.3
22.20
0.74
AP (1)
0
0
0
0
27.1
1.13
AP (1)
0
27.1
1.13
AP (1)
Fig. 8. Timing diagram showing successful operation of the proposed 4F 2

STT MRAM cell at V D D = 1.6 V.
423
the proposed 4F 2 and conventional 10F 2 cell. The corresponding results are tabulated in Table V. Undoubtedly, the proposed
cell demonstrates a better performance in terms of power dissipation and write margins. The leakage power dissipation for
the proposed cell is four to five orders of magnitude lower than
conventional cell (when the cell is not selected for writing). The
dynamic power dissipation at WWL = 1.6 V (VDD ) is higher;
although, here the point of consideration is that the dynamic
power always has a tradeoff with the P and AP write margins
(write currents). There is a larger tradeoff window between the
write margin and dynamic power dissipation in the case of proposed cell with GAA device, as it can operate with VDD as low
as 1.3 V (at tPW = 1 ns) by sacrificing the write margins. It is
clearly observed in Fig. 7(b) that the planar cell cannot operate
correctly at VDD = 1.3 V for tPW = 1 ns. Moreover, a comparison of the dynamic power dissipation between the cells in
terms of VDD in Fig. 7(c) shows that the proposed cell can be
optimized for low-power operation also.
424
VII. CONCLUSION
425
The proposed STT MRAM cell offers better performance

over the conventional STT MRAM cell from all perspectives.
The biggest improvements are in terms of area and leakage
power dissipation. The proposed cell occupies a much smaller
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
426
427
428
area of 4F 2 with a 60% reduction in area from its conventional

counterpart, and still offers a much better performance. Hence,
to achieve high density STT MRAMs, the 4F 2 cell with vertical
GAA transistor is potentially better solution than 610 F2 cell
with planar transistor. The leakage power dissipation of the proposed cell is comparatively much smaller, when the cell is not
selected for writing (WWL = 0 V ). In addition, the proposed
cell shows excellent write margins and can be optimized for
low power operation. Despite the high write currents, the read
behavior is not compromised, as the proposed cell offers good
read stability and high read margins. Moreover, the read disturb
rate is lower than 107 up to read voltage VR = 0.4 V with
a read current difference of 10 A between 0 (P) and 1 (AP)
stored cells. These advantages have been possible by the virtue
of vertical GAA NMOS. The proposed select device offers excellent gate control (Io = 12 pA) and high current drive along
with the attainment of maximum 2-D array density. These improvements should proliferate even more with subsequent down
scaling of the STT MRAM cell.
IE
E
Pr E
oo
f
GAA
Parameter
APPENDIX I
BSIM CG MODEL CALIBRATION
The important parameters and model calibration methodology for configuring BSIM CG for cylindrical GAA operation
are classified and discussed as follows:
A. Geometry and Material Parameters: The geometry
and material parameters of BSIM CMG are set for a vertical
GAA device operation, according to the parameters used for
TCAD simulation (see Table VI).
B. Threshold Voltage Calibration: The threshold voltage
of BSIM CG is expressed as
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
Vth = Vth0 + Vth,SCE + Vth,DIBL + DVTSHIFT (A1)
where Vth0 is the threshold voltage of the model based on surface potential calculations. Vth,SCE is the threshold voltage
degradation due to short channel effects, Vth,DIBL is used
to model the effect of drain voltage on threshold voltage, and
DVTSHIFT is to handle any additional shift in Vth [21].
The model equation for Vth,SCE in BSIM CG [21] is
Vth,SCE =
0.5DVT0
(Vbi st )
cosh {DVT1 (Le /)} 1
(A2)
458
459
460
461
462
463
TABLE V
COMPARISON BETWEEN PROPOSED CELL AND 10F2 PLANAR NMOS
Select Device
GAA
Planar
W M P (A)
W M A P (A)
t p (ns)
t A P (ns)
Power (pW) W W L = 0 V
Power (W) W W L = 1.6 V
23.3
17.6
34.0
29.0
0.43
0.52
0.25
0.32
16.2
1140
112.4
107.0
TABLE VII
THRESHOLD VOLTAGE PARAMETERS
TABLE VI
GEOMETRY AND MATERIAL PARAMETERS
GEOMOD
BULKMOD
ASYMMMOD
COREMOD
L
D
EOT
NGATE
NSD
PHIG
NBODY
Value
Description[21]
3
0
1
0
120 nm
40 nm
2 nm
0
1 1020 cm3
4.61 eV
1 1016 cm3
Cylindrical GAA
SOI substrate
Asymmetric device
Surface potential model
Gate length
Gate diameter
Gate oxide thickness
Metal gate
S/D doping concentration
Gate work function
Channel doping
VALUE
Description [21]
DVT0
DVT1
ETA0
DSUB
DVTP0
DVTP1
DVTSHIFT
2.2
0.177
1
0.80
0
0
0
SCE coefficient
SCE exponent coefficient
DIBL coefficient
DIBL exponent coefficient
Coefficient for drain-induced V t h shift
Exponent coefficient for drain-induced V t h shift
Additional V t h shift handle
TABLE VIII
MOBILITY AND DRAIN CURRENT PARAMETERS
IE
E
Pr E
oo
f
464
465
466
467
468

where
Vbi = (kB T /q) ln NSD (nb o dy /n2i ) ,
and
=
st = 0.4 + (kB T /q) ln(nb o dy /ni ),

(si R EOT/2ox ) {1 + (R ox /2si EOT)}.
Le is the effective channel length. The model equation for
Vth,DIBL in BSIM CG is expressed as [22]
Vth,DIBL =
0.5ETA0
VDS
cosh (DSUB (Le /)) 1
+ DVTP0 VDS DVTP1

469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
U0
IDS0MULT
U0MULT
TCAD simulation is carried to calculate Vth,SCE and

Vth,DIBL and then (A1)(A3) are used to set threshold voltage
parameters accordingly (see Table VII).
C. Mobility and Drain Current Parameters: Average low
field mobility is calculated using TCAD simulations for the
on state (VGS > Vth and VDS = 0.05) of the device. The low
field mobility is found to be 650 cm2 /(Vs). Further, U0MULT
(multiplier to mobility) and IDS0MULT (multiplier to source
drain channel current) are set, which are dedicated to variability
modeling and can be set by the user appropriately [21]. Mobility
and drain current parameters are shown in Table VIII.
D. Parasitic Capacitance, Subthreshold, and Leakage
Current Parameters: AC analysis is done at a frequency of
1 MHz with a low VDS (load line analysis in Section V shows
that the NMOS will be invariably in the linear region of operation). Hence, at |VDS | = 0.2 V, the average values of capacitances are calculated. The average gate to source capacitance
CGS and gate-to-drain capacitances CGD are found to be 0.087
and 0.1 fF/m, respectively. The parameters concerned with
parasitic capacitance and subthreshold conduction are placed in
Table IX.
Description [21]
650 cm2 /Vs

5
0.62
Low field mobility

Multiplier to sourcedrain channel current
Multiplier to mobility
TABLE IX
PARASITIC CAPACITANCE, SUBTHRESHOLD, AND LEAKAGE CURRENT
PARAMETERS
(A3)
Value
CGEOMOD
CGEO1SW
COVS
COVD
DVT1SS
GIDLMOD
AGISL
AGIDL
Value
Description [21]
1
1
0.1 fF
0.087 fF
1.0234
1
1.05 1015
1.05 1015
Parasitic capacitance model selector

Capacitance unit selector
Constant ate to source overlap capacitance
Constant gate to drain overlap capacitance
Subthreshold swing exponent coefficient
GIDL/GISL model selector
Preexponential coefficient for GISL
Preexponential coefficient for GIDL
REFERENCES
[1] ERD. (2011). International technology road map for semiconductors [Online]. Available: http://www.itrs.net
[2] T. Schloesser et al., 6F2 buried wordline DRAM cell for 40 nm and
beyond, in Proc. IEEE IEDM08, San Francisco, CA, USA, pp. 14,
Dec. 2008.
[3] H. Chung et al., Novel 4F2 DRAM cell with vertical pillar transistor(VPT), in Proc. IEEE ESSDRC, Helsinki, Finland, pp. 211214, Sep.
2011.
[4] Z. Fang et al., Fully CMOS-compatible 1T1R integration of vertical
nanopillar GAA transistor and oxide-based RRAM cell for high-density
nonvolatile memory application, IEEE Trans. Electron Devices, vol. 60,
no. 3, pp. 11081113, Mar. 2013.
[5] D.-L. Kwong et al., Vertical silicon nanowire platform for low power
electronics and clean energy applications, J. Nanotechnol., vol. 2012,
pp. 121, 2012.
[6] T. Kawahara, K. Ito, R. Takemura, and H. Ohno, Spin-transfer torque
RAM technology: Review and prospect, Microelectron. Reliab., vol. 52,
no. 4, pp. 613627, Apr. 2012.
490
491
492
493
494
495 Q5
496
497
498
499
500
501
502
503
504
505
506
507
508
[7] S. Ikeda et al., Recent progress of perpendicular anisotropy magnetic

tunnel junction for non-volatile VLSI, Spin (World Sci.), vol. 2, no. 3,
pp. 1240003-11240003-12, Dec. 2012.
[8] S. Ikeda et al., Magnetic tunnel junctions for spintronic memories and
beyond, IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 9911002,
2007.
[9] PIDS. (2001). International technology roadmap for semiconductors [Online]. Available: http://www.itrs.net
[10] Y. Song et al., Performance breakthrough in gate-all-around nanowire nand p-type MOSFETs fabricated on bulk silicon substrate, IEEE Trans.
Electron Devices, vol. 59, no. 7, pp. 18851890, Jul. 2012.
[11] K. Lee, J. J. Sapan, S. H. Kang, and E. E. Fullerton, Perpendicular
magnetization of CoFeB on single-crystal MgO, J. Appl. Phys., vol. 109,
no. 12, pp. 123910-1123910-3, Jun. 2011.
[12] S. Ikeda et al., A perpendicular-anisotropy CoFeB-MgO magnetic tunnel
junction, Nat. Mater., vol. 9, no. 9, pp. 721724, Sep. 2010.
[13] M. Gajek et al., Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy, Appl. Phys. Lett., vol. 100, no. 13,
pp. 1324081-132408-3, Mar. 2012.
[14] Y. Zhang et al., Compact modeling of perpendicular-anisotropy
CoFeB/MgO magnetic tunnel junctions, IEEE Trans. Electron Devices,
vol. 59, no. 3, pp. 819826, Mar. 2012.
[15] D. D. Tang and Y. J. Lee, Magnetic memory fundamentals and technology,
1st ed. Cambridge U.K.: Cambridge Univ. Press, 2010, ch. 36.
[16] J. Li et al., Design paradigm for robust spin-torque transfer magnetic
RAM (STT MRAM) from circuit/architecture perspective, IEEE Trans.
VLSI, vol. 18, no. 12, pp. 17101723, Dec. 2010.
[17] Silvaco Inc. (2012, Mar.). ATLAS users manual [Online]. Available:
www.silvaco.com
[18] L. Dobrescu et al., Threshold voltage extraction methods for MOS transistors, in Proc. CAS 2000 Int. Semicond. Conf., 23rd ed., 2000, vol. 1,
no. 2, pp. 371374.
[19] A. Bazigos et al., An adjusted constant-current method to determine
saturated and linear mode threshold voltage of MOSFETs, IEEE Trans.
Electron Devices, vol. 58, no. 11, pp. 37513758, Nov. 2011.
[20] X. Fong, S. H. Choday, and K. Roy, Bit-cell level optimization for
non-volatile memories using magnetic tunnel junctions and spin-transfer
torque switching, IEEE Trans. Nanotechnol., vol. 11, no. 1, pp. 172181,
Jan. 2012.
[21] V. Sriramkumar et al., BSIM-CMG 107.0.0 Multi-gate MOSFET Compact
Model: Technical Manual, Dept. Elect. Eng. Comp. Sci., Univ. California,
Berkeley, USA, 2013.
[22] D. Lu, C. H Lin, A. Niknejad, and C. Hu, Multi-gate MOSFET compact model BSIM-MG, in Compact Modeling, G. Gidenblat, Ed. The
Netherlands: Springer, pp. 395429, 2010.
[23] N. Paydavosi, A. Niknejad, C. Hu, BSIMSOIv4.5.0 MOSFET MODEL
Users Manual, Dept. Elect. Eng. Comp. Sci., Univ. California, Berkeley,
USA, 2013.
[24] T. Kawahara et al., 2 Mb SPRAM (spin-transfer torque RAM) with
bit-by-bit bi-directional current write, IEEE Trans. Solid State Circuits,
vol. 43, no. 1, pp. 109120, 2008.
Shivam Verma (S13) received the M.Tech. degree

in microelectronics from IIT BHU, Varanasi, India,
in 2012. He is currently working toward the Ph.D.
degree from the Indian Institute of Technology Roorkee, Roorkee, India.
His current research interests include STT
MRAMs and all spin logic.
560
561
562
563
564
565
566
567
Shalu Kaundal (S14) received the M.Tech. degree

in microelectronics and VLSI from the Indian Institute of Technology Roorkee, Roorkee, India.
Her current research interests include designing
and modeling of STT MRAMs.
568
569
570
571
572
573
IE
E
Pr E
oo
f
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
Q6 541
542
543
544
545
546
547
548
549
550
551
552
553
Q7 554
555
556
557
558
Q8 559
Brajesh Kumar Kaushik (SM13) received the B.E.

degree in electronics and communication engineering from D.C.R. University of Science and Technology (formerly C. R. State College of Engineering),
Murthal, India, in 1994, and the M.Tech. degree in
engineering systems from Dayalbagh Educational Institute, Agra, India, in 1997, and the Ph.D. degree
under AICTE-QIP scheme from the Indian Institute
of Technology Roorkee, Roorkee, India, in 2007.
He was with Vinytics Peripherals Pvt. Ltd., Delhi,
India, as a Research and Development Engineer in
microprocessor, microcontroller, and DSP processor-based systems. He joined
the Department of Electronics and Communication Engineering, G. B. Pant
Engineering College, Pauri Garhwal, India, as a Lecturer in July 1998, where
he was an Assistant Professor from May 2005 to May 2006 and an Associate
Professor from May 2006 to December 2009. He is currently an Associate
Professor in the Department of Electronics and Communication Engineering,
Indian Institute of Technology Roorkee, Roorkee, India. His current research
interests include in the area of high-speed interconnects, low-power VLSI design, carbon-nanotube-based designs, organic thin film transistor design and
modeling, and spintronics-based devices and circuits.
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
QUERIES
597
598
599
600
601
602
603
604
Q1.
Q2.
Q3.
Q4.
Q5.
Q6.
Q7.
Q8.
Author: Please check the acronym of word line. Is this OK as is or should be WL.
Author: Please check the edited sentence PMA MTJs offer . . . switching. for intended meaning.
Author: Please provide the full form of the acronyms BSIM CG and TMR.
Author: The variable j has been set as R MTJ. Please check.
Author: Please provide all the names of authors in Refs. [2][5], [7], [8], [10], [12][14], [16], [21], and [24].
Author: Please verify Ref. [18] as set.
Author: Please provide the city of the publisher in Ref. [22].
Author: Please provide the month information in Ref. [24].
IE
E
Pr E
oo
f
596

TNANO Author PROOF PDF

Încărcat de

Informații document

Descriere originală:

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

TNANO Author PROOF PDF

Încărcat de

Drepturi de autor:

Formate disponibile

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO.

Novel 4F2 Buried-Source-Line STT MRAM Cell

AbstractSpin transfer torque (STT) magnetic random access

NALOGOUS to a typical memory system, spin transfer

it is low (binary 0) if the magnetization orientations of the two

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014

III. ANALYSIS OF PRACTICALLY FABRICATED PMA MTJS

4Me = 4MS Hkp

II. PROPOSED STT MRAM ARCHITECTURE

STT MRAMs have three-dimensional (3-D) integration of

where Hkp is the perpendicular uniaxial anisotropy, Ms is the

IV. DESIGN CONSIDERATIONS

WMAP = (IWAP0 ILH0 )

WMP = (IW P0 IHL0 ),

WER and RDR are expressed as

where PSW is the probability of occurrence of switching below

where tPW is the current pulsewidth, 0 is the attempt time, IC0

V. VERTICAL GAA TRANSISTOR AS SELECT DEVICE

Conventionally, the overall area of the STT MRAM cell has

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014

DIBL (mV/V) Io n (A) Io n /Io f f

Fig. 3. Comparison of the ID V G S characteristics of GAA (40 nm nanowire

A. TCAD Analysis of the Proposed Structure

Fig. 4. Comparison of |ID | |V D S | characteristics with top as drain and

due to large short channel effects that are measured at a high

B. DC Load Line Analysis

In this section, dc load line analysis is carried out to ascertain

where RM TJ is the resistance of MTJ. The RM TJ and TMR

C. BSIM CG Model Calibration

BSIM CG is a part of the combined multigate (MG) model

all MG and GAA transistors [21], [22]. Appendix I depicts the

VI. ANALYSIS OF PROPOSED STT MRAM CELL

The proposed STT MRAM cell and conventional cell with

where Vbias is voltage across MTJ and Vh (= 0.5 V) is the fitting

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014

Hold (initial state AP)

Fig. 8. Timing diagram showing successful operation of the proposed 4F 2

The proposed STT MRAM cell offers better performance

area of 4F 2 with a 60% reduction in area from its conventional

Vth = Vth0 + Vth,SCE + Vth,DIBL + DVTSHIFT (A1)

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014

Power (W) W W L = 1.6 V

BSIM Model Parameter

BSIM Model Parameter

BSIM Model Parameter

st = 0.4 + (kB T /q) ln(nb o dy /ni ),

+ DVTP0 VDS DVTP1

TCAD simulation is carried to calculate Vth,SCE and

650 cm2 /Vs

Low field mobility

BSIM Model Parameter

Parasitic capacitance model selector

[7] S. Ikeda et al., Recent progress of perpendicular anisotropy magnetic

Shivam Verma (S13) received the M.Tech. degree

Shalu Kaundal (S14) received the M.Tech. degree

Brajesh Kumar Kaushik (SM13) received the B.E.

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014

Novel 4F2 Buried-Source-Line STT MRAM Cell

AbstractSpin transfer torque (STT) magnetic random access

NALOGOUS to a typical memory system, spin transfer

it is low (binary 0) if the magnetization orientations of the two

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 00, NO. 00, 00 2014