EE2255

DIGITAL LOGIC CIRCUITS

3 1 0 4

AIM
To introduce the fundamentals of Digital Circuits, combinational and sequential circuit.
OBJECTIVES
i.
To study various number systems and to simplify the mathematical
expressions
using Boolean functions simple problems.
ii.
To study implementation of combinational circuits
iii.
To study the design of various synchronous and asynchronous circuits.
iv.
To expose the students to various memory devices.
v.
To introduce digital simulation techniques for development of application
oriented logic circuit.
1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS
9
Boolean algebra: De-Morgans theorem, switching functions and simplification using
K-maps & Quine McCluskey method, Design of adder, subtractor, comparators, code
converters, encoders, decoders, multiplexers and demultiplexers.
2. SYNCHRONOUS SEQUENTIAL CIRCUITS
9
Flip flops - SR, D, JK and T. Analysis of synchronous sequential circuits; design of
synchronous sequential circuits Counters, state diagram; state reduction; state
assignment.
3. ASYNCHRONOUS SEQUENCTIAL CIRCUIT
9
Analysis of asynchronous sequential machines, state assignment, asynchronous
design problem.
4. PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES 9
Memories: ROM, PROM, EPROM, PLA, PLD, FPGA, digital logic families: TTL,
ECL, CMOS.
5. VHDL
9
RTL Design combinational logic Types Operators Packages Sequential
circuit Sub programs Test benches. (Examples: adders, counters, flipflops, FSM,
Multiplexers / Demltiplexers).
L = 45 T = 15 Total = 60
TEXT BOOKS
1. Raj Kamal, Digital systems-Principles and Design, Pearson education 2 nd edition,
2007
2. M. Morris Mano, Digital Design, Pearson Education, 2006.
3. John M.Yarbrough, Digital Logic, Application & Design, Thomson, 2002.
REFERENCES
1. Charles H.Roth, Fundamentals Logic Design, Jaico Publishing, IV edition, 2002.
2. Floyd and Jain, Digital Fundamentals, 8th edition, Pearson Education, 2003.
3.John F.Wakerly, Digital Design Principles and Practice, 3rd edition, Pearson
Education, 2002.
4. Tocci, Digital Systems : Principles and aopplications, 8th Edition Pearson Education.
UNIT I

BOOLEAN ALGEBRA & COMBINATIONAL CIRCUITS

1. Convert the hexadecimal number 68BE to binary and octal (NOV 2007)
(68BE)H =( )2 = ( )8
6
8 B
E

0110 1000 1011 1110 = (110100010111110)2

110 100 010 111 110

6 4 2 7 6 = (64276)8
2. Find the 1s and 2s complement of 00000000 (NOV 2007)
1s complement of 00000000=11111111
2s complement =1s+1=11111111+1=100000000
3. Express the following switching circuit in binary logic notation.(NOV 2007)
INPUT
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

OUTPUT
Y=(A+B).C
0
1
0
1
0
1
0
1

4. Simplify X + XY. (NOV 2007)

Y X XY

X+XY

X + XY = X+Y

5. What is the difference between half adder and full adder? (Nov 2007)
Half Adder

Full Adder

The logic circuit which performs The logic circuit which performs
the arithmetic sum of two bits is the arithmetic sum of three bits is
called a half adder.
called a full adder.

6. Implement half adder using gates (Nov 2007)

INPUT

OUTPUT

Sum

Carry

7. What is a prime Implicant? (Nov 2008).

After grouping the cells, the sum terms which appear in the K-map are called
Prime Implicant.
8. Given that 1610 = 100b find the value of b. (NOV 2008)
4 16
4 4 - 0
1 - 0
The value of b = 4.
9. Implement the following using NAND gates only. (Nov 2008)
AB + BA=Y

10. Give an application each for a multiplexer and a De multiplexer. (NOV 2008)
Multiplexer circuit are used for data selection and data routing.
De multiplexers are used in Binary to Decimal decoder and it is used in
DATA transmission system with error detection.
11. State Demorgans theorem. (June 2009)
1. AB = A + B. The complement of a product is equal to the sum of the
complement.
2. A + B = A . B. The complement of a sum is equal to the product of the
complement.
1. Proof: A+B = A + B
A

A.B

A+B

2. Proof : A+B = A . B
A

A+B

A.B

12. Briefly explain the streamlined method of converting binary to decimal number
with an example. (June 2009)
Example : (11011)2 = ( )10
1 X 24 + 1 X 23 + 0 X 2 2 + 1 X 2 1 + 1 X 2 0
16 + 8 + 0
+ 2 + 1

= (27) 10

13. Give the Gray code for the binary number (1111)2 (June 2009)
(1111)2 = (1010)Gray

14. Subtract 01011011 - 00000101 (June 2009)

01011011
00000101
---------------01010110
---------------15. What is priority encoder. (June 2009).
A priority encoder is an encoder circuit that includes the priority function. In
priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.
16. Show the common cathode type seven segment indicator (display). (Nov 2009).

Digit

17. Convert 1110011 into hexadecimal. (June 2010)

0111 0011

7
3
Ans. = (73)H

18. Add (1A8)16 and (67B)16. June 2010.

1 A8

Decimal Hexa
16
10
67B
17
11
---------------18
12
823
19
13
---------------Ans. : (823)H
20
14
19. Express the Boolean function F = XY + XY as a product of max term. (June
2010)
X.Y X

XY XY XY+XY

0 0

0 Max term

0 1

1 0

0 Max term

1
1

F = M(0,2)
20. Differentiate combinational and sequential circuits (June 2010)
Combinational circuit

Sequential Circuit

Memory unit is not required

Memory unit is required

Parallel adder is a combinational Serial adder is a sequential

circuit
circuit.
21. Add (A3)16 to (7C)H.
A3
7C
-------------11 F
--------------

Ans.: (11F)H

22. What do you mean by literal?

Decimal
15
16
17
18
19
20
21
22

Hexa
F
10
11
12
13
14
15
16

In Boolean function, the total number of variables in complemented or

uncomplemented form are called literals.
Example: F (A,B,C,D) = A + BC + ACD contains 6 literals.
23. Name two basic forms (or) types of Boolean expression.
1. Sum of product Form (SOP) or Min term.
2. Product of sum form (POS) or Max term.
24. Which gates are called as universal gates and why they are so called?
NAND and NOR gates are called as universal gates. Since NAND and NOR
gates can be used alone to generate remaining gates such as NOT, AND and OR. Hence
they are called as universal gates.
25. Represent binary number 1101.101 in power of 2 and find its decimal
equivalent.
N = 1 x 23 + 1 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 0 x 2-2 + 1 x 2-3
= (13.625)10
26. Convert (634)8 to binary.
6
3
4
110 011 100
Ans = (110 011 100)2
27. Convert (9 B 2.1A)H to its decimal equivalent.
N = 9 x 162 + B(11) x 161 + 2 x 160 + 1 x 16-1 + A(10) x 16-2
= 2304 + 176 + 2 + 0.0625 + 0.039
= (2482.1015)10
28. What are the different classifications of binary codes?
Weighted codes
Non - weighted codes
Reflective codes
Sequential codes
Alphanumeric codes
Error Detecting and correcting codes.
29. Convert gray code 101011 into its binary equivalent.

30. Add (1 0 1 0)2 and (0 0 1 1)2

31. Find 2s complement of (1 0 1 0 0 0 1 1)2

32. What are the advantages of 1s complement subtraction?

The 1s complement subtraction can be accomplished with an binary adder.
Therefore, this method is useful in arithmetic logic circuits.
The 1s complement of a number is easily obtained by inverting each bit in the
number.
33. What is meant by parity bit?
Parity bit is an extra bit included with a binary message to make the number of
1s either odd or even. The message, including the parity bit is transmitted and then
checked at the receiving and for errors.
34. Define Decoder.
A decoder is a multiple - input multiple output logic circuit which converts coded
inputs into coded outputs where the input and output codes are different.
In a binary decoder n input produces 2n outputs.
35. Define Encoder.
An encoder has 2n input lines and n output lines. In encoder the output lines
generate the binary code corresponding to the input value.
36. Define multiplexer & Demultiplexer.
Multiplexer is a digital switch. If allows digital information from several sources
to be routed onto a single output line.
A Demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2n possible output lines.

37. Design 1:8 demultiplexer using to 1:4 DEMUX.

38. What is a logic gate?

The logic gate is an electronic circuit that has one or more input binary variables
but only one output. It is called logic gate because of its ability to operate on a number
of binary inputs to perform a logical function, i.e. its output is a logical function of
inputs

UNIT- II
SYNCHRONOUS SEQUENTIAL CIRCUITS
1. What is meant by triggering and what is edge triggering? (Nov 2007)
Triggering of a flip flop means changing the state of the output of flip flop
(from 0 to 1 for +ve logic and from 1 to 0 for ve logic ) by giving a clock pulse and an
input.
Another type of flip flop that synchronizes the state changes during a clock pulse
transition is edge triggered flip flop. In this type of flip flop output transitioNoccur at a
specific level of the clock pulse.
2. What is race condition? (Nov 2008)
In the JK latch, the output is feedback to the input, and therefore change in the
output results change in the input. Due to this in the positive half of the clock pulse if J
and K are both high then output toggles continuously. This condition is known as race
around condition.
3. Draw the truth table for a NOR gate RS Flip flop. (June 2007)
S
0
0
0
0
1
1
1
1

R
0
0
1
1
0
0
1
1

Qn
0
1
0
1
0
1
0
1

Qn+1
0
1
0
0
1
1
X
X

State
No change (NC)
Reset
Set
Intermediate

4. Obtain D Flip Flop from JK Flip Flop. (June 2009)

or
5. Convert JK Flip flop to D Flip flop. (June 2010)
Input
D
0
0
1
1

Present state
Qn
0
1
0
1

Next state
Q n+1
0
0
1
1

Flip-flop inputs
J
0
X
1
X

K
X
1
X
0

6. Differentiate Synchronous Counter and Asynchronous Counter (June 2009)

7.

Draw a modulo 6 counter (June 2009)

2n >=6
N=6
n=3
therefore three flip flops are required to draw the modulo 6 counter

8. A counter has 14 stable states 0000 through 1101. If the input frequency is 50
Hz. What will be the output frequency? (June 2010)
50 KHz
-------------14

3.57 KHz

9. Define sequential circuit and what are the types of sequential circuits?
In sequential circuits the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables.
Synchronous sequential circuits
Asynchronous sequential circuits
10. Define flip-flop
Flip - flop is a sequential device that normally samples its inputs and changes its
outputs only at times determined by clocking signal.
11. List various types of flip-flop
S.R. latch
D latch
Clocked J.K. flip-flop
T flip-flop

12. Draw the logic diagram for SR latch using two NOR gates.

13. The following wave forms are applied to the inputs of SR latch.
Determine the Q waveform Assume initially Q = 1

14. What is meant by a clocked Flip flop?

A FF whose state changes (according to the data i/p s ) only when a clock pulse is
present.
15. Explain the functions of preset and clear i/p s in flip flops.
Preset input is used to set (make Q = 1 ) the FF,whereas the clear i/p is
used to clear or reset (make Q = 0) the FF.
16.Explain the operation of a JK flip flop.
i) When J = K = 0, the outputs are not affected by the clock pulse.
ii) When J = K = 1,the outputs get complemented when a clock is
applied.
i)
J = 1, K = 0 sets the FF when the clock is applied.
ii)
J = 0, K= 1 clears the FF when the clock is applied.
17. What is Master Slave flip flop?
It is a cascade of two flip flops in which the first one responds to the data inputs when
the clock is high, whereas the second one responds to the outputs of the first one when
the clock is low. Thus the final o/p change only when the clock is low when the data
inputs are not effective. Thus the race around condition gets eliminated in this. The first
FF is known as the MASTER and the second as the SLAVE.

18. What is a Latch and what is meant by a Transparent Latch?

A Latch stores one bit of data. It is a D type of flip flop.
It is the output of the latch follows the input as long as the clock is present and
whatever is the o/p at the falling edge of the clock gets latched, it is known as the
transparent latch. The word transparent signifies that the output is same as the i/p as long
as the clock is present.
19. What are the various methods used for triggering flip flop?
i) Level Triggering.
ii) Master-Slave or Pulse triggering.
iii) Positive-edge triggering.
iv) Negative-edge triggering.
20. Differentiate between Negative-edge triggered and Master slave flip flop.
In Negative-edge triggered FF, only a negative ( or falling ) edge is required for
triggering whereas in the case of master slave FF, both a positive and a negative edge are
required for triggering.
21. Differentiate between S-R and J-K flip flop.
When both the i/ps are at logic 1,the o/p of a J-K FF gets complemented, whereas
this i/p condition is prohibited in S-R FF. For all other i/p conditions the behavior of
both is same.
22. Why Master Slave configuration is used in a JK flip flop?
Master Slave configuration is used in a JK FF to eliminate Race around
condition.
23. Define shift Registers
The binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of bit
movement or shifting is essential for certain arithmetic and logic operations used in
microprocessors. This gives rise to a group of registers called shift registers.
24. What are the types of shift register?
Serial in serial out shift register
Serial in parallel out shift register
Parallel in serial out shift register
Parallel in parallel out shift register
Bidirectional shift register
25. What are the types of counter?

 Synchronous counter
Asynchronous Counter
26. Define propagation Delay
A propagation delay is the time required to change the output after application of
the input.

27. What is meant by serial data?

In the serial form the data is arranged bit by bit. Only one wire is required for serial
data.
28. What is meant by parallel data?
In the parallel form each data bit requires a separate wire. For example, 8 wires are
required for processing or transmitting an 8-bit data.
29. Compare serial data and parallel data transmission.
1. Serial data requires only one connecting wire between the source device and the
destination device, whereas the parallel data requires a number of lines equal to the
number of bits in the data. Therefore, parallel transmission is expensive.
2. Serial data transmission requires more time than the parallel data transmission.
30. What is meant by modulus of a counter?
It represents the number of possible states of the counter.
31. How will you use a shift register to multiply or divide a binary number by 2?
The binary number is to be stored in the shift register and then shifted towards
right or left respectively by one bit position for multiplication or division by 2.
32. Are the ring and twisted ring counters synchronous or asynchronous counters?
Justify
The ring and twisted ring counters are synchronous because all the FLIP-Flops
are clocked simultaneously in three counters.
33. What is meant by the following terms?
(a) Synchronous preset
(b) Asynchronous preset
(c) Synchronous clear
(d) Asynchronous clear
(a) Preset operation is performed in synchronism with the clock
(b) Preset operation is independent of the clock
(c) Clear operation is performed in synchronism with the clock.
(d) Clear
operation
is
independent
of

the

clock

34. Can you use a 7492 counter IC as a natural binary mod-12 counter? Justify
your answer.

It is not possible. The divide by 6 circuit of this counter does not follow natural
binary sequence.
35. How will you use the 7490 IC to design a symmetrical divide by 10 frequency
divider?
The divide by 5 circuit followed by divide by 2 circuit will give symmetrical
output.
36. What is the drawback of SR Flip flop and how it is minimized?
Drawbacks
of SR Flip flop is that it has intermediate state when SR = 11 and problem can be
minimized by providing complemented inputs for S & R.
37. How does a JK Flip flop differ from the SR Flip Flop in its basic operation?
In JK Flip flop when both the inputs are logic 1 the output is complement of
previous output. However, in case of SR flip flop when both the inputs are 1, the output
is intermediate.
38. Mention the application of counter.
Digital counter is useful and versatile device and it is found in many applications
such as digital clock and frequency counter.
39. How many Flip flops are required to build a binary counter that counts from 0
to 1023?
Number of flip flops required:
2n > 1023 + 1
2n > 1024
N = 10
Therefore 10 flip flops are required to build a binary counter that counts from 0 to
1023.

UNIT- III
ASYNCHRONOUS SEQUENTIAL CIRCUIT
1. What is the difference between serial and parallel transfer? What type of
register is used in each case? (Nov 2007)
Shift register are used for storage and transfer of data in a digital system.
Serial transfer
Serial shift right then out
Serial shift left then out

Parallel Transfer
Parallel shift in
Parallel shift out

The register used for serial transfer is serial in serial out shift register.
The register used for parallel transfer is parallel in parallel out shift register.
2. Define Hazard. (Nov 2008)
The unwanted switching transients that appear at the output of a circuit are called
Hazards. The hazard cause the circuit to malfunction. The main cause of hazards is
the different propagation delays at different paths.
3. What is a Mealey machine? Give an example. (Nov 2008)
When the output of the sequential network depends on both the present state of flip
flop and on the inputs the sequential circuit is called as Mealey machine. Its input
changes may affect the output of the circuit.
4. What is Saturation delay time? Explain. (June 2009)
TTL logic family are based on the saturation mode. In the saturation mode, the
transistor takes some time to come out of the saturation to switch to the cut off
mode. Since the transistors do not go into saturation, these families do not have
saturation delay time for switching operation.
5. What is a race condition? How it can be eliminated? (June 2009)
In a JK latch when J& K are both high, then the output toggles continuously and
this condition is called race condition.
This can be eliminated when an edge triggered or pulse triggered JK flip flop is
used. In this flip flop the output changes only at the positive edge or a negative
edge of the clock.
6. What is essential hazard? Give an example. (June 2009)

Essential hazards occurs in asynchronous sequential circuits. It is caused by

unequal delays along two or more paths that originate from the same input. These
hazards can be eliminated by adjusting the amount of delays in the affected path.
7. What is the difference between hazard and race? (June 2010)
The unwanted switching transients that appear at the output of a circuit are called
Hazards. The hazard cause the circuit to malfunction. The main cause of hazards is
the different propagation delays at different paths.
In a JK latch when J& K are both high, then the output toggles continuously and
this condition is called race condition.
8. The input frequency of a 4 bit ripple counter is 256 Hz. What is the output
frequency? (June 2010)
0 15 that is 16 stable states are there for a 4 bit ripple counter. Given input
frequency = 256 Hz.
256 Hz
----------- = 16 Hz
16
Output frequency =
16 Hz
9. Define compatibility.
States Si and Sj said to be compatible states, if and only if for every input
sequence that affects the two states, the same output sequence, occurs whenever both
outputs are specified and regardless of whether Si on Sj is the initial state.
10. Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices
as the state table contains states. Each compatible state pair is indicated by a line drawn
between the two state vertices. If two states are incompatible no connecting line is
drawn.
11. Define incompatibility.
The states are said to be incompatible if no line is drawn in between them. If
implied states are incompatible, they are crossed & the corresponding line is ignored.
12. Explain the procedure for state minimization.
Partition the states into subsets such that all states in the same subsets are 1
- equivalent.
Partition the states into subsets such that all states in the same subsets are 2
- equivalent.

 Partition the states into subsets such that all states in the same subsets are 3
- equivalent.
13. Define state table and total state.
For the design of sequential counters we have to relate present states and next
states. The table which represents the relationship between present states and next states
is called state table.
The combination of level signals that appear at the inputs and the outputs of the
delays is called the total state of the circuit.
14. What are the steps for the design of asynchronous sequential circuit?
Construction of a primitive flow table from the problem statement.
Primitive flow table is reduced by eliminating redundant states by using
state reduction.
State assignment is made
The primitive flow table is realized using appropriate logic elements.
15. Define primitive flow table.
It is defined as a flow table which has exactly one stable state for each row in the
table. The design process begins with the construction of primitive flow table.
16. Give the comparison between state Assignment Synchronous circuits and state
assignment asynchronous circuit.
In synchronous circuit, the state assignments are made with the objective of
circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid
critical races.
17. Define critical race and non critical race?
If the final stable state depends on the order in which the state variable changes,
the race condition is harmful and it is called a critical race.
If the final stable state that the circuit reaches does not depend on the order in
which the state variable changes, the race condition is not harmful and it is called a non
critical race.
18. What is a cycle?
A cycle occurs when an asynchronous circuit makes a transition through a series
of unstable states. If a cycle does not contain a stable state, the circuit will go from one
unstable to stable to another, until the inputs are changed.
19. List the different techniques used for state assignment
Shared row state assignment
One hot state assignment.

20. Write a short note on fundamental mode asynchronous circuit.

Fundamental mode circuit assumes that. The input variables change only when
the circuit is stable. Only one input variable can change at a given time and inputs are
levels and not pulses.
21. Write a short note on pulse mode circuit.
Pulse mode circuit assumes that the input variables are pulses instead of level.
The width of the pulses is long enough for the circuit to respond to the input and the
pulse width must not be so long that it is still present after the new state is reached.
22. Define secondary variables.
The delay elements provide a short term memory for the sequential circuit. The
present state and next state variables in asynchronous sequential circuits are called
secondary variables.
23. What is the purpose of synthesis in asynchronous sequential circuit?
The purpose of synthesis is to develop systematic techniques for the design of
fundamental mode asynchronous sequential circuits. The approach to be followed is to
construct a flow table which describes the circuit performance, to simplify the table,
whenever possible, and finally to realize it by electronic or electromechanical devices.
24. Write short note on shared row state assignment.
Races can be avoided by making a proper binary assignment to the state
variables. Here, the state variables are assigned with binary numbers in such a way that
only one state variable can change at any one state variable can change at any one time
when a state transition occurs. To accomplish this, it is necessary that states between
which transitions occur be given adjacent assignments. Two binary are said to be
adjacent if they differ in only one variable.
25. Write short note on one hot state assignment.
The one hot state assignment is another method for finding a race free state
assignment. In this method, only one variable is active or hot for each row in the original
flow table, ie, it requires one state variable for each row of the flow table. Additional
row are introduced to provide single variable changes between internal state transitions.

UNIT IV
PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES
1. What is a Volatile memory? Give example. (Nov 2007)
Volatile memory losses the content when the computer or hardware device losses
power.
Example : SRAM & DRAM
2. Which is faster TTL or ECL? Which requires more power to operate? (Nov
2007)
TTL logic is faster than ECL, since it uses multi emitter transistors and every
emitter is a diode this logic eliminates the use of diodes. ECL requires more power
to operate.
3. Define fan in & fan out. (Nov 2008)
Fan-in
It is said to be the number of inputs in a digital logic gate.
Example: 2 input NOR had fan-in of 2.
Fan-out
It is said to be the number of inputs in a digital logic gate.
Example: 2 input NOR has Fan-in of 2.

4. Define Noise margin. (Nov 2008)

The voltage difference between the lowest possible HIGH output, VOH (min) and the
minimum input voltage, VIH (min) required for a HIGH input is called high-state
noise margin.
The voltage between the largest possible low output, VOL (max) and the maximum,
VIL (max) required for a LOW input is called low-state noise margin.
The noise margin allows the digital circuit to function properly if noise voltages are
within the noise margin.

5. What is saturation delay time? Explain (June 2009)

TTL logic families are based on the saturation mode. In the saturation mode, the
transistor takes some time to come out of the saturation to switch to the cut off
mode. Since the transistors do not go into saturation, these families do not have
saturation delay time for switching operation.
6. Compare Bipolar Transistors with MOS Transistors (June 2009)
Bipolar Transistors
1. Bipolar can work at higher
frequencies.
2. It has good input and output
impedance matching at high frequency.
3. High power dissipation
4. High cost

MOS Transistors
1. It work at low frequency.
2. Input and output impedance
matching is not possible at high
frequency.
3. Low state power dissipation.
4. Low cost.

7. Compare volatile data storage with non volatile data storage. (June 2009)
Volatile Data Storage
1. Volatile data storage losses the stored
information when the power is turned
off.

Non-volatile Data Storage

Non volatile data storage retains the
stored information even when the
power is turned off.
Ex: ROM, PROM, EPROM, EEPROM

Ex: SRAM & DRAM

8. How is combinational logic generated in FPGA (June 2009).
The FPGA has three types of configurable elements. They are I/O blocks, CLBs
and resources for interconnection.
A configuration program stored in internal static memory cells determines the logic
functions and the interconnection.
9. Define Propagation delay. (June 2010)
It is a time interval between application of an input pulse and occurance of the
resulting pulse.
The propagation delay is determined using two basic time intervals:
1. tPHL : Delay Time measured when output is changing from logic 1 to logic 0
state.
2. tPLH : Delay Time measured when output is changing from logic 0 to logic 1
state.

3. When tPHL and tPLH are not equal, the larger value is considered as propagation
delay.
4. The shorter the propagation delay, the higher the speed of the circuit and vice
versa.
10. What is open collector output TTL? Where is it used? (June 2010)
When the collector terminal of a transistor is kept open without any pull up
transistor the arrangement is called open collector output.
The output is taken directly from the open collector terminal of a transistor at the
output.
But, a gate with open collector will not work properly until an external resistor is
connected.
11. Explain FPGA. Give an example of such device. (June 2010).
Field programmable Gate Arrays (FPGA) provide the next generation in
the programmable logic devices. The word field in the name refers to the ability
of the gate arrays to be programmed for a specific function by the user instead of
by the manufacturer of the device. The word array is used to indicate a series of
columns and rows of gates that can be programmed by the end user.
As compared to standard gate arrays, the field programmable gate arrays
are larger devices. The basic cell structure for FPGA is some what complicated
than the basic cell structure of standard gate array. The programmable logic
blocks of FPGAs are called configurable logic blocks (CLBs).
Example: XILINUX 3000 & XILINUX 4000
12. List basic types of programmable logic devices.
Read only memory
Programmable logic Array
Programmable Array Logic
13. What are the types of ROM?

Masked ROM.
Programmable Read only Memory
Erasable Programmable Read only memory.
Electrically Erasable Programmable Read only Memory.

14. What is mask - programmable?

With a mask programmable PLA, the user must submit a PLA program table to
the manufacturer.

15. Give the comparison between PROM and PLA.

16. Define Speed Power Product and what is the other name for speed Power
product?
The Speed Power Product is defined as the product of Propagation delay and
average power dissipation. Its unit is Joules / Seconds
The other name for speed power product is Figure of merit.
17. For a certain IC family, propagation delay is 10ns with average power
dissipation
of 6 mW. What is the speed power product?
Solution:
SPP = propagation delay x average power dissipation.
= 10 ns x 6 mW
= 60 pico joules (pJ)
18. Give the comparison between Totem pole and Open collector Output
configuration.
Totem Pole
1. Output stage consists of pull up
transistor, diode resistor and pull down
transistor.
2. External pull up resistor is not
required.
3. Output of two gates can not be tied
together.
4. Operating speed is high.

Open Collector
Output stage consists of only pull down
transistor
External pull up resistor is required for
proper operation of gate.
Output of two gates can be tied together
using wired AND technique.
Operating speed is low.

19. What are the three types of output configuration in TTL family?

 Open Collector configuration

Totem pole output configuration
Tristate logic
20. Define Interfacing and what is the function of Interfacing?
Interfacing means connecting the output of one circuit or system to the input of
another circuit or system that may have different electrical characteristics.
Its function is to take the driver output signal and condition it so that it is
compatible with requirements of the load.
21. What are requirement while interfacing two circuits or systems.
The driver output must satisfy the voltage and current requirements of the
load circuit.
The driver and load circuit may require different power supplies. In such
cases the output of both circuits must swing between its specified voltage
ranges.
22. What is the limitation of TTL family?
The TTL family uses transistors operating in the saturation mode. As a result,
their switching speed is limited by the storage delay time associated with a transistor that
is driven into saturation.
23. Give any 2 points of ECL characteristics.
It is the fastest of logic families. The popular 10K and 100K ECL families
offer propagation delay as short as 1 ns.
Transistors are not allowed to go into complete saturation and thus
eliminating storage delays.
24. Define High level input voltage and Low level input voltage.
VIH (min) High level input voltage: It is the minimum voltage level required for
a logical 1 at an input. Any voltage below this level will not be accepted as a HIGH by
the logic circuit.
VIL (max) Low level input voltage: It is the maximum voltage level required for
a logic 0 at an input. Any voltage above this level will not be accepted as a LOW by the
logic circuit.
25. Define High level output voltage and Low level output voltage.
It is the minimum voltage level at a logic circuit output in the logical 1 state under
defined load conditions.

It is the maximum voltage level at a logic circuit output in the logical 0 state
under defined load conditions.

26. Define High level input current and Low level input current.
It is the current that flows into an input when a specified high-level voltage is
applied to that input.
It is the current that flows into an input when a specified low-level voltage is
applied to that input.
27. Define High level output current and low level output current.
It is the current that flows from an output in the logical 1 state under specified
load conditions.
It is the current that flows from an output in the logical 0 state under specified
load conditions.
28. List the characteristics of digital Ics
i)
ii)
iii)
iv)
v)

propagation delay
power dissipation
Fan-in
Fan-out
Noise margin

29. Define Flash memory and what is the other name for flash memory?
Flash memory is a type of constantly powered nonvolatile memory that can be
erased and reprogrammed in units of memory called blocks.
The other name is Flash RAM. But Flash memory is not useful as random access
memory because RAM needs to be addressable at the byte level.
30. Compare between PROM, PLA and PAL.
PROM
PLA
1.
AND array is fixed Both AND and OR
and OR array is arrays
are
programmable.
programmable.
2.
Cheaper and simple to Costliest and complex
use.
than PAL and PROMs.
3.
All minterms are AND array can be
decoded.
programmed to get
desired minterms.

PAL
OR array is fixed and
AND
array
is
programmable.
Cheaper and Simpler.
AND array can be
programmed to get
desired minterms.

4.

Only
Boolean Any Boolean functions
functions in standard in SOP form can be
SOP form can be implemented using PLA.
implemented
using
PROM.
UNIT V
VHDL

Any Boolean functions

in SOP form can be
implemented
using
PLA.

1. Define VHDL. (June 2010)

VHDL is a Very High Speed Integrated Circuit Hardware Description Language.
This hardware description language is used to describe the behaviour and structure of
digital system.
2. List the operators used in VHDL. (Juen 2010).
Binary logical operators: AND, OR, NAND, NOR, XOR, XNOR
Relational operators: = /= < <= > >=
Shift operators: sll srl sla sra rol ror
Adding Operators: + - & (Concatenation)
Unary sign operators: + Multiplying operators: * / mod rem
Miscellaneous operators: not abs **
3. What is meant by Packages?
A Package is used to provide a convenient method to store and share declarations
that are common for many design units. It is represented by:
a package declaration and
a package body
4. What is package declaration & package body?
It contains a set of declarations that may be shared by various design units.
It defines items which are made visible to other design units.
A package body contains the hidden details of a package. ie., It contains
the behaviour of the subprograms and the values of the deferred constants which
are declared in a package declaration.
5. What are the types of data types?
There are four types of data types:
1. Scalar type
2. Composite types
3. Access types
4. File types
6. Name two subprograms and give the difference between these two.

1. Function 2. Procedure
Only one output is possible in function.
Many outputs possible using procedure.
7. Write the syntax for FOR/GENERATE statement.
Generate_label: for identifier in range generate
[begin]
concurrent statements;
end generate[generate_label];
8. Compare signal and variable.
Variables must be declared within the process in which they are used and
are local to that process. Signals must be declared outside of a process. Signals
declared at the start of an architecture can be used anywhere within that
architecture.
9. List the syntax of WAIT UNTIL statement with example.
Wait until Boolean_ expression ;
Wait until a = b;
10. Define sensitivity list for process statement.
A process have the form
Process ( sensitivity- list)
Begin
Sequential-statements
End process;
11. Compare behavioral level, data flow level and structural level of describing a
digital system in VHDL?
Behavioral level

Data flow level

Structural Level

A digital system in VHDL A digital system in VHDL

A digital system in
is described in terms of its is described by giving the VHDL is described by
function.
logic equations.
specifying
the
interconnections of the
gates.
12. Model 4 to 1 MUX using a selected signal assignment statememt.
f <= i0 when sel=0
else i1 when sel =1
else i2 when sel =2

else i3;
13. Give the program structure of VHDL.
entity entityname is
---- declaring input ,output variables
---end entityname;
architecture architecturename of entityname is
---- signal declaration
begin
--------end
architecturename;

entity
architecture
----------entity
architecture
module1

entity
architecture
moduleN

14. What is concurrent code?

Concurrent code are VHDL signal assignment statements in which they are
not contained in VHDL process or block.
Eg.,
C <= A and B after 5 ns;
E <= C or D after 5ns;
15. What is the symbol <=?
The symbol <= is the signal assignment operator , which indicates the value
computed on the right side is assigned to the signal on the left side.
Eg.,
C <= A and B ;
E <= C or D ;
16.Give the VHDL code for full adder.
entity fulladder is
port( x,y cin : in bit;

cout,sum: out bit);

end fulladder;
architecture equations of fulladder is
begin
sum<=x xor y xor cin after 10 ns;
cout<=(x and y) or (x and cin) or (y and cin) after 10 ns;
end equations;
17. Give the modeling of sequential logic in VHDL process.
process(sensitivity-list)
begin
sequential-statements
end process;
18. What is sequential code?
process(sensitivity-list)
begin
sequential-statements
end process;
Whenever one of the signals in the sensitivity list changes, the
sequential-statements in the process body are executed in sequence one time.
19. What is the use of VHDL compiler?
The VHDL compiler also called an analyzer ,first checks the VHDL source
code to see that it conforms to the syntax and rules of VHDL.
20. What is elaboration?
The VHDL intermediate code must be converted to a form that can be
used by the simulator. This is called elaboration.
21.Give the general form of variable declaration.
variable list-of-variable-names:type_name[:=initial_value];
22. Give the general form of signal declaration.
signal list-of-signal-names:type_name[:=initial_value];
23. Give the general form of constant declaration.

constant constant_name : type_name:=constant_value;

eg.,
constant delay1:time:= 5 ns;

24. Give the VHDL program for D flip flop.

library ieee;
use ieee.std_logic_1164.all;
entity dfff1 is
port (D,CLK,reset:in std_logic;
Q:out std_logic);
end dff1;
architecture arch_dflipflop of dff1 is
begin
process(CLK)
begin
if(CLKevent and CLK=1) then
if reset =0 then
Q<=0;
else
Q<=D;
endif;
endif;
end process;
end;
25. What is event?
A change in a signal is called an event. Each time an event occurs ,any
processes that have been waiting on the event are executed in zero time, and any
resulting signal changes are queued up to occur at some future time.