Documente Academic
Documente Profesional
Documente Cultură
turn translates to having a fixed number of states in my machine. From the data path, it
should be obvious that I need 5 states. Aside from having a fixed number of states, it also has
a fixed path, which means I would simply be using a counter from 0 to 4. The only problem
would be the Hold when Start = 0 and count is in State0.
This is what I implemented to hold in State0 if Start = 0.
As for the other states, they are pretty straight forward. Once it gets to State1, it would
just go to the next state after every positive edge of the clock.
Since the selector of the mux is Start and S0, as shown, LD will only happen on the
first computational clock cycle. This effectively initializes the Register and the flipflop in
preparation for (based on the logic mentioned previously) adding, checking and shifting. For
D4 to D7, the reason why ProductA is ANDed to D0 is because from the logic, it will only Load
ProductA if D0 is 1. If this is not done, ProductA will always be loaded to D4 to D7 regardless
if D0 is not asserted, resulting to a failure of computation.
Shift will happen whenever it is not in State0 regardless of the input Start, which means
in the middle of computation, it will always finish no matter the input.
Hold happens when the machine is in State1 but the Start = 0. It just feeds the current
outputs back to the Register and D-flipflop.
V. Notes, Problems, and Things That Aren't Really Important But I Put Them Anyway
Because This DP Messed Me Up (And There's Another Half Page to Fill Up)
Now that I reread this Documentation for editing, I realized there's something wrong
with the Logic Used Figure. The first clock cycle doesn't ADD ProductA to the Upper Product,
it chooses between LOADING it or not based on the Check. I could have fixed that but doing
that would be too troublesome so I'm just noting it here :D
Also, that was a problem that I encountered. First time I finished the circuit, I was so
happy it worked when I tried it but then I tried 15 times 15 (1111 x 1111 = 11100001) IT GOT
THE WRONG ANSWER. What's worse is that it gets a DIFFERENT WRONG ANSWER if I
don't reset the whole machine, which is a big no-no so I had to trace A LOT of wires just to
find what went wrong.
In conclusion, debugging circuits is as difficultif not moreas debugging a written
program. I have learned my lesson, sensei.
If you noticed that there was more detail on the LD for the mux part (the one on top of
the page) it's because the morning after I finished the circuit, I woke up to the realization that I
forgot to consider that. It was a problem that I personally encountered so no one can blame
me for putting that into detail in the Documentation.
On a final note, I hope I won't get minus points for putting this unrelated/useless/
unnecessary heading to my Documentation. If it will get me deductions, I'll happily print and
submit a version without it :D