E0-286 (2:1) Testing and Verification for SoC Design (Jan 2008)

6/19/2014

E0-286 (2:1) - Testing and Verification for SoC

Design
Semester: Jan - Apr 2008
Instructor: Virendra Singh
Class Timings: 1200 - 1300 Hrs (MWF) @202, SERC
Syllabus:
VLSI design flow, Introduction to electronic system testing and test
economics, Fault modeling (Stuck-at, Bridge, Delay, and Cross-talk fault
models), Fault simulation, Test generation for combinational circuits, ATPG
algorithms (D-Algorithm, PODEM, and FAN), Test generation complexity, Test
generation for sequential circuits, Time frame expansion model, Design for
test, Built-In Self Test (BIST), Memory test, Delay test, SoC test issues and
methodologies, test data compression and power conscious testing, fault
diagnosis and Synthesis for test.
High level design flow and verification issues, Simulation based verification,
Formal verification techniques: Model checking, equivalence checking, SAT
solvers, BDDs, Symbolic model checking with BDDs. Semi-formal Verification
techniques: Symbolic Simulation, Bounded Model Checking, Sequential ATPG
based Model Checking.
Reference:
1. M. L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for
Digital Memory and Mixed Signal VLSI Circuits, Springer, 2005
2. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985
3. M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and
Testable Design, IEEE Press, 1994
4. M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ.
Press, 2004
5. Current Literature
6. Class notes
Prerequisite: Knowledge of Digital System Design
Class Test Schedule:
Test1: March 3 (Mon) @ 1130 Hrs - R.N 309, SERC (Open Book)
Test2: April 07 (Mon) @ 1200 Hrs R.N 202, SERC (Open Book)
Test3: April 11 (Fri) @ 1200 Hrs R.N 202, SERC (Open Book)
Final Exam: April 22, 2008 (2:00 - 5:00 PM) @202, SERC (Close Book)
Class Schedule:
Jan 9
Jan 14

Course Introduction
Basics of testing
(By Prof. Erik Larsson)

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E0-286 (2:1) Testing and Verification for SoC Design (Jan 2008)

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Jan
Jan
Jan
Jan
Jan

18
21
23
25
28

Introduction
Yield Analysis
Fault modeling
Fault Simulation
Fault Simulation

Jan 30

Test pattern Generation

Feb 1

Test pattern Generation

Feb 4
Feb 6
Feb 8

Algorithmic TPG
ATPG
Formal Verification

Feb 9
Feb 13
Feb 13

ATPG - II
Testability Analysis
Formal Verification - I

Feb 15
Feb 16

Testability Analysis
Formal Verification - II
(By Dr. Subir Roy)
ATPG - III
Sequential Circuit test - I

Feb 18
Feb 20
Feb 20
Feb 22
Feb 22
Feb 27
Feb 29
Feb 29
Mar 3
Mar 7
Mar 7
Mar 12
Mar 14
Mar 17
Mar 17
Mar 19
Mar 24

(By Dr. Subir Roy)

(By Dr. Subir Roy)

VLSI design flow, need of testing

Yield Analysis and fault modeling
Fault Modeling, Fault collapsing
Fault Simulation (Serial and parallel)
Fault
Simulation
(Deductive,
concurrent, and fault sampling)
TPG
basics,
Boolean
Difference
method
Boolean Difference and BDD based
TPG
Basics, D-Algorithm
D-Algorithm
Need of formal verification, SoC
verification
9-Valued Logic TG, PODEM
Testability analysis, SCOAP
Basics
of
formal
verification,
introduction to LTL
Testability analysis
LTL
FAN Algorithm
Test Compaction, Sequential ckt.
Testing, Time frame expansion model
LTL

Formal Verification - III

(By Dr. Subir Roy)
Sequential Circuit test - Sequential ATPG
II
Formal Verification - IV
Introduction to CTL
(By Dr. Subir Roy)
Sequential Circuit test - DfT (Scan Design)
III
Sequential Circuit test - Partial Scan,
IV
Formal Verification - V
CTL*
(By Dr. Subir Roy)
Test 1 (Testing)
Random Access Scan
Random Access Scan: Attack problem
in 3 way
Formal Verification - VI
SMC Algorithms
(By Dr. Subir Roy)
Sequential
Circuit Class of sequential circuits with
Classes
combinational circuit TG complexity
Formal Verification - VII
(By Dr. Subir Roy)
Sequential
Circuit Class of sequential circuits with
Classes
combinational circuit TG complexity
Delay Fault Testing
Delay Fault testing and classification
Formal
Verification Verification of LTL properties
VIII
(By Dr. Subir Roy)
Delay Fault Testing - II
Path Delay fault testing,

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Mar 26

Delay Fault Testing - III

Mar 28
Mar 29
Mar 31
Apr 02
Apr 02

BIST - I
BIST-II
BIST - III
Memory Test
Formal Verification - IX
(By Dr. Subir Roy)
SoC Test Methodology - I
Semi-Formal Verification
(By Dr. Subir Roy)

Apr 08
Apr 09

DFTG, Enhanced Scan Design, Test

application
Built-In Self-Test
BIST - TPG, LFSR
BIST - RA
Memory fault model, March tests

Selected Readings (Papers):

1. D. Baik, K. K. Saluja and S. Kajihara, "Random Access Scan: a solution to test power,
test data volume and test time," International Conference on VLSI Design, Jan. 2004
2. H. Fujiwara, A new class of sequential circuits with combinational test generation
complexity, IEEE Trans. on Computers, Vol. 49, No. 5, Sep 2000, pp. 895-905
3. S. Ohtake, T. Masuzawa, and H. Fujiwara, A non-scan DfT method for controllers to
achieve complete fault efficiency, Proc. of the IEEE Asian Test Symposium (ATS)
1998, pp. 204-211.
4. T. Iwagaki, S. Ohtake, and H. Fujiwara, A design methodology to realize delay
testable controllers using state transition information, Proc. of the IEEE European
Test Symposium (ETS) 2004, pp. 168-173.
5. Y. Bonhomme et al., Power driven chaining of flip-flops in scan architecture,
Proc. of the IEEE International Test Conference (ITC) 2002, pp. 796-803.

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