VLSI

VLSI Testing
Testing

Yield
Yield Analysis
Analysis &
& Fault
Fault Modeling
Modeling
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 2

VLSI
VLSI Chip
Chip Yield
Yield

A manufacturing defect is a finite chip area with

electrically malfunctioning circuitry caused by errors
in the fabrication process.
A chip with no manufacturing defect is called a good
chip.
Fraction (or percentage) of good chips produced in a
manufacturing process is called the yield. Yield is
denoted by symbol Y.
Cost of a chip:
Cost of fabricating and testing a wafer
-------------------------------------------------------------------Yield x Number of chip sites on the wafer

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Clustered
Clustered VLSI
VLSI Defects
Defects
Good chips
Faulty chips

Defects
Wafer
Unclustered defects
Wafer yield = 12/22 = 0.55
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Clustered defects (VLSI)

Wafer yield = 17/22 = 0.77

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Yield
Yield Parameters
Parameters

Defect density (d ) = Average number of defects per

unit of chip area
Chip area (A)
Clustering parameter ()
Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x )
(Ad /) x
= ------------- . ---------------------x ! () (1+Ad /) +x
where is the gamma function
= 0, p (x ) is a delta function (maximum clustering)
= , p (x ) is Poisson distribution (no clustering)

(+x )

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Yield
Yield Equation
Equation
Y = Prob ( zero defect on a chip ) = p (0)

Y = ( 1 + Ad / )
Example: Ad = 1.0, = 0.5, Y = 0.58
Unclustered defects: = , Y = e

- Ad

Example: Ad = 1.0, = , Y = 0.37

too pessimistic !
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Defect
Defect Level
Level or
or Reject
Reject Ratio
Ratio

Defect level (DL) is the ratio of faulty chips

among the chips that pass tests.
DL is measured as parts per million (ppm).
DL is a measure of the effectiveness of tests.
DL is a quantitative measure of the manufactured
product quality. For commercial VLSI chips a DL
greater than 500 ppm is considered
unacceptable.

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Determination
Determination of
of DL
DL

From field return data: Chips failing in the field

are returned to the manufacturer. The number of
returned chips normalized to one million chips
shipped is the DL.
From test data: Fault coverage of tests and chip
fallout rate are analyzed. A modified yield model
is fitted to the fallout data to estimate the DL.

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Modified
Modified Yield
Yield Equation
Equation

Three parameters:
Fault density, f = average number of stuck-at
faults per unit chip area
Fault clustering parameter,
Stuck-at fault coverage, T
The modified yield equation:

Y (T ) = (1 + TAf / ) -
Assuming that tests with 100% fault coverage
(T =1.0) remove all faulty chips,

Y = Y (1) = (1 + Af / ) -
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Defect
Defect Level
Level
Y (T ) - Y (1)

DL (T ) = -------------------Y (T )

( + TAf )
= 1 - -------------------

( + Af )
Where T is the fault coverage of tests, Af is the
average number of faults on the chip of area A,
is the fault clustering parameter. Af and are
determined by test data analysis.
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Yield
Yield and
and Fault
Fault Coverage
Coverage

Defect Level

30
25
20
15
10
5
0
0
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10

20

30

40 50 60 70
Fault Coverage
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80

90 100
10

Computed
Computed DL
DL

Defect level in ppm

237,700 ppm (Y = 76.23%)

Stuck-at fault coverage (%)

SEMATECH Chip
Jan 18, 2008

(Courtesy: IBM)
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Revenues

Time
Time to
to Market
Market

Loss of
Revenues

Time to
Market
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Time in Months

T
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Failure Rate Vs Product Lifetime

Working Life Span

Wearout

Failure Rate

Infant
Mortality

1-20 weeks

10-20 years
Product Life Time

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Definitions
Definitions

Defect: A defect in an electronic system is

the unintended difference between the
implemented hardware and its intended
design
Error: A wrong output signal produced by
defective system is called error. An error is
an effect whose cause is some defect
Fault: A representation of a defect at the
abstracted function level is called a fault

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Why
Why Model
Model Faults?
Faults?

I/O function tests inadequate for

manufacturing (functionality versus
component and interconnect testing)
Real defects (often mechanical) too
numerous and often not analyzable
A fault model identifies targets for testing
A fault model makes analysis possible
Effectiveness measurable by experiments

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Some
Some Real
Real Defects
Defects in
in Chips
Chips
Processing defects
Missing contact windows
Parasitic transistors
Oxide breakdown
. . .
Material defects
Bulk defects (cracks, crystal imperfections)
Surface impurities (ion migration)
. . .
Time-dependent failures
Dielectric breakdown
Electromigration
. . .
Packaging failures
Contact degradation
Seal leaks
. . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
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Electromigration
(a)

(b)

(c)

(a) Open in a line

(b) Short between two lines (whisker)
(c) Short between lines on different layers (hillock)

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Mapping Physical Defect into

Faults 1
Z

RL
A

R1
R2

(a)

B
A

Z
A

Z
(b)

Both the defective resistance in bipolar

and a the oxide breakdown in oxide
between the source and drain of the NMOS
transistor form a short failure mode
Both cases are mapped into a stuck-at
fault

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Mapping Physical Defect into

Faults 2
A
A

A
Z

Poly

Metal

Diffusion

Physical defect: A missing metal

o NMOS is missing the gate
Failure mode: an open
Fault: open
A possible circuit representation is shown

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Mapping Physical Defect into

Faults 3
L1

L1

L2

L2

(a)

(b)

Stuck-at 1
Vdd

Stuck-at 0
GND
(c)

Bridging Fault
(d)

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Observed
Observed PCB
PCB Defects
Defects
Occurrence frequency (%)

Defect classes
Shorts
Opens
Missing components
Wrong components
Reversed components
Bent leads
Analog specifications
Digital logic
Performance (timing)

51
1
6
13
6
8
5
5
5

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

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Failure Classification
IC Failures
M ode

D uration

Incorrect D esign

Perm anant
H ard

Param eter D egradation

Tem poraty
Soft
Transient
Interm ittent

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Common
Common Fault
Fault Models
Models
Single stuck-at faults
Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults

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Single
Single Stuck-at
Stuck-at Fault
Fault

Three properties define a single stuck-at fault

Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and

24 single stuck-at faults
c
1
0

Faulty circuit value

Good circuit value

s-a-0

g
1

1(0)

h
i
k

0(1)

Test vector for h s-a-0 fault

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