VLSI Testing

Sequential
Sequential ATPG
ATPG -- II
II
Virendra Singh
Indian Institute of Science (IISc)
Bangalore
virendra@computer.org
E0-286: Testing and Verification of SoC Design
Lecture 15
Feb 22, 2008

E0-286@SERC

Sequential
Sequential Circuits
Circuits
A sequential circuit has memory in addition to
combinational logic
Test for a fault in a sequential circuit is a
sequence of vectors, which
Initializes the circuit to a known state
Activates the fault, and
Propagates the fault effect to a PO
Methods of sequential circuit ATPG
Time-frame expansion methods
Simulation-based methods

Feb 22, 2008

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Example:
Example: A
A Serial
Serial Adder
Adder
An Bn

s-a-0

1
1

Cn

X
Cn+1

X
Combinational logic

FF
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Sn X

Time-Frame
Time-Frame Expansion
Expansion
An-1 Bn-1
1

An Bn

Time-frame -1
s-a-0

Cn-1

Time-frame 0
s-a-0

Cn

Cn+1

Combinational logic

Combinational logic

Sn-1

Sn

FF

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Concept
Concept of
of Time-Frames
Time-Frames
If the test sequence for a single stuck-at fault
contains n vectors,
Replicate combinational logic block n times
Place fault in each block
Generate a test for the multiple stuck-at fault
using combinational ATPG with 9-valued logic
Fault
Unknown
or given
Init. state

Comb.
block
Feb 22, 2008

Vector -n+1

Timeframe
-n+1
PO -n+1

State
variables

Vector -1

Vector 0

Timeframe
-1

Timeframe
0

PO -1

PO 0

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Next
state

Example
Example for
for Logic
Logic Systems
Systems

FF1

Feb 22, 2008

s-a-1

FF2

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Five-Valued
Five-Valued Logic
Logic (Roth)
(Roth)
A 0
s-a-1
FF1
FF2

s-a-1

Time-frame -1
Feb 22, 2008

A 0

B X
E0-286@SERC

Time-frame 0

FF1
FF2

B X
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Nine-Valued
Nine-Valued Logic
Logic (Muth)
(Muth)
A 0

A X

s-a-1

s-a-1
0/1

FF1
FF2

0/X

0/X

0/1

X/1

Time-frame -1
Feb 22, 2008

X/1

B X
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Time-frame 0

FF1
FF2

0/1
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Implementation
Implementation of
of ATPG
ATPG
Select a PO for fault detection based on drivability

analysis.
Place a logic value, 1/0 or 0/1, depending on fault
type and number of inversions.
Justify the output value from PIs, considering all
necessary paths and adding backward time-frames.
If justification is impossible, select another PO and
repeat justification (use drivability).
If the procedure fails for all reachable POs, then the
fault is untestable.
If 1/0 or 0/1 cannot be justified at any PO, but 1/X or
0/X can be justified, the the fault is potentially

detectable.

Feb 22, 2008

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Complexity
Complexity of
of ATPG
ATPG
Synchronous circuit -- All flip-flops controlled by clocks;

Smax

PI and PO synchronized with clock:

Cycle-free circuit No feedback among flip-flops:
Test generation for a fault needs no more than
dseq + 1 time-frames, where dseq is the
sequential depth.
Cyclic circuit Contains feedback among flipflops: May need 9Nff time-frames, where Nff is the
number of flip-flops.
Asynchronous circuit Higher complexity!
TimeFrame
max-1

TimeFrame
max-2

S3

Time- S2 Time- S1 TimeFrame

Frame
Frame
-2
-1
0

S0

max = Number of distinct vectors with 9-valued elements = 9Nff

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Cycle-Free
Cycle-Free Circuits
Circuits
Characterized by absence of cycles among flipflops and a sequential depth, dseq.
dseq is the maximum number of flip-flops on
any path between PI and PO.
Both good and faulty circuits are initializable.
Test sequence length for a fault is bounded by
dseq + 1.

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11

Cycle-Free
Cycle-Free Example
Example
Circuit
F2
2
F3

F1
Level = 1

F2
2

s - graph
F1

F3

Level = 1

dseq = 3

All faults are testable.

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12

Cycle-Free
Cycle-Free Example
Example
-1

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13

Thank You
Feb 22, 2008

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