VLSI Testing

Scan
Scan Design
Design
Virendra Singh
Indian Institute of Science (IISc)
Bangalore
virendra@computer.org
E0-286: Testing and Verification of SoC Design
Lecture 16
Feb 27, 2008

E0-286@SERC

Cyclic
Cyclic Circuit
Circuit Example
Example
Modulo-3 counter
CNT

F2

F1

s - graph
F2

F1

Feb 27, 2008

E0-286@SERC

Modulo-3
Modulo-3 Counter
Counter

Cyclic structure Sequential depth is undefined.

Circuit is not initializable. No tests can be generated
for any stuck-at fault.
After expanding the circuit to 9Nff = 81, or fewer,
time-frames ATPG program calls any given target
fault untestable.
Circuit can only be functionally tested by multiple
observations.
Functional tests, when simulated, give no fault
coverage.

Feb 27, 2008

E0-286@SERC

Adding
Adding Initializing
Initializing Hardware
Hardware
Initializable modulo-3 counter
CNT

F2

F1

s-a-0

s-a-1

CLR
s-a-1

s-a-1

Untestable fault
Potentially detectable fault

s - graph
F2

F1

Feb 27, 2008

E0-286@SERC

Difficulties
Difficulties in
in Seq.
Seq. ATPG
ATPG

Poor initializability.
Poor controllability/observability of state
variables.
Gate count, number of flip-flops, and sequential
depth do not explain the problem.
Cycles are mainly responsible for complexity.
An ATPG experiment:
Circuit

Number of
gates

Number of
flip-flops

Sequential
depth

ATPG
CPU s

Fault
coverage

TLC

355

21

14*

1,247

89.01%

1,112

39

14

269

98.80%

Chip A

* Maximum number of flip-flops on a PI to PO path

Feb 27, 2008

E0-286@SERC

Benchmark
Benchmark Circuits
Circuits
Circuit
PI
PO
FF
Gates
Structure
Sequential depth
Total faults
Detected faults
Potentially detected faults
Untestable faults
Abandoned faults
Fault coverage (%)
Fault efficiency (%)
Max. sequence length
Total test vectors
Gentest CPU s (Sparc 2)
Feb 27, 2008

s1196
14
14
18
529
Cycle-free
4
1242
1239
0
3
0
99.8
100.0
3
313
10
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s1238
14
14
18
508
Cycle-free
4
1355
1283
0
72
0
94.7
100.0
3
308
15

s1488
8
19
6
653
Cyclic
-1486
1384
2
26
76
93.1
94.8
24
525
19941

s1494
8
19
6
647
Cyclic
-1506
1379
2
30
97
91.6
93.4
28
559
19183
6

Scan
Scan Design
Design
Circuit

is designed using pre-specified design rules.

Test structure (hardware) is added to the verified
design:
a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect to
form one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
Add

Use

combinational ATPG to obtain tests for all

testable faults in the combinational logic.
Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing test.
Feb 27, 2008

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Scan
Scan Flip-Flop
Flip-Flop (SFF)
(SFF)
Master latch

Slave latch

TC
Q

Logic
overhead

MUX

SD

CK

D flip-flop

CK

TC

Feb 27, 2008

Master open Slave open

Normal mode, D selected

E0-286@SERC

t
Scan mode, SD selected

Level-Sensitive
Level-Sensitive Scan-Design
Scan-Design
Flip-Flop
Flip-Flop (LSSD-SFF)
(LSSD-SFF)
Master latch

Slave latch

D
Q

MCK

Q
D flip-flop

SD

MCK

TCK

Feb 27, 2008

overhead

TCK
MCK
TCK

Scan
mode

Logic

Normal
mode

SCK

SCK

E0-286@SERC

Adding
Adding Scan
Scan Structure
Structure
PI

PO
Combinational

SFF

logic

SFF

SCANOUT

SFF

TC or TCK
SCANIN
Feb 27, 2008

Not shown: CK or
MCK/SCK feed all
SFFs.
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10

Comb.
Comb. Test
Test Vectors
Vectors

PI

I1

I2

Feb 27, 2008

O2

Combinational

SCANIN
TC
Present
state

O1

SCANOUT

logic
S1

N1

S2

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PO

N2

Next
state

11

Comb.
Comb. Test
Test Vectors
Vectors

SCANIN

I2

I1

PI

S1

Dont care
or random
bits

S2

TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

PO

SCANOUT

O2

O1

N1

N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops

Feb 27, 2008

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Testing
Testing Scan
Scan Register
Register
Scan register must be tested prior to
application of scan test sequences.
A shift sequence 00110011 . . . of length
nsff+4 in scan mode (TC=0) produces 00, 01,
11 and 10 transitions in all flip-flops and
observes the result at SCANOUT output.
Total scan test length: (ncomb + 2) nsff +
ncomb + 4 clock periods.
Example: 2,000 scan flip-flops, 500 comb.
vectors, total scan test length ~ 106 clocks.
Multiple scan registers reduce test length.

Feb 27, 2008

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Multiple
Multiple Scan
Scan Registers
Registers

Scan flip-flops can be distributed among any number

of shift registers, each having a separate scanin and
scanout pin.
Test sequence length is determined by the longest
scan shift register.
Just one test control (TC) pin is essential.

PI/SCANIN

Combinational
logic
SFF
SFF

M
U
X

PO/
SCANOUT

SFF

TC
CK
Feb 27, 2008

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14

Scan
Scan Overheads
Overheads

IO pins: One pin necessary.

Area overhead:
Gate overhead = [4 nsff/(ng+10nff)] x 100%,
where ng = comb. gates; nff = flip-flops;
Example ng = 100k gates, nff = 2k flip-flops,
overhead = 6.7%.
More accurate estimate must consider scan
wiring and layout area.
Performance overhead:
Multiplexer delay added in combinational
path; approx. two gate-delays.
Flip-flop output loading due to one additional
fanout; approx. 5-6%.

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15

Hierarchical
Hierarchical Scan
Scan

Scan flip-flops are chained within subnetworks before

chaining subnetworks.
Advantages:

Automatic scan insertion in netlist

Circuit hierarchy preserved helps in debugging and
design changes

Disadvantage: Non-optimum chip layout.

Scanin

SFF4

SFF1

Scanout
Scanin

SFF2

SFF3

SFF3
Scanout

SFF4

Hierarchical netlist
Feb 27, 2008

SFF1

SFF2

Flat layout
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16

Optimum
Optimum Scan
Scan Layout
Layout
X

X
IO
pad
Flipflop
cell

SFF
cell
SCANIN

TC

Routing
channels
Interconnects
Feb 27, 2008

SCAN
OUT

Active areas: XY and XY

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17

ATPG
ATPG Example:
Example: S5378
S5378
Original
Number of combinational gates
Number of non-scan flip-flops (10 gates each)
Number of scan flip-flops (14 gates each)
Gate overhead
Number of faults
PI/PO for ATPG
Fault coverage
Fault efficiency
CPU time on SUN Ultra II, 200MHz processor
Number of ATPG vectors
Scan sequence length

Feb 27, 2008

E0-286@SERC

2,781
179
0
0.0%
4,603
35/49
70.0%
70.9%
5,533 s
414
414

Full-scan
2,781
0
179
15.66%
4,603
214/228
99.1%
100.0%
5s
585
105,662

18

Automated
Automated Scan
Scan Design
Design
Behavior, RTL, and logic
Design and verification

Rule
violations
Scan design
rule audits

Gate-level
netlist

Combinational
ATPG

Scan hardware
insertion

Scan
netlist

Combinational
vectors
Scan sequence
and test program
generation

Test program
Feb 27, 2008

Scan chain order

Design and test
data for
manufacturing
E0-286@SERC

Chip layout: Scanchain optimization,

timing verification

Mask data
19

Scan
Scan Design
Design Rules
Rules
Use only clocked D-type of flip-flops for all state
variables.
At least one PI pin must be available for test;
more pins, if available, can be used.
All clocks must be controlled from PIs.
Clocks must not feed data inputs of flip-flops.

Feb 27, 2008

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Correcting
Correcting a
a Rule
Rule Violation
Violation

All clocks must be controlled from PIs.

Comb.
logic D1

Q
Comb.
logic

FF

D2
CK

Comb.
logic
Q

D1
D2

Feb 27, 2008

FF

CK
E0-286@SERC

Comb.
logic

21

Thank You
Feb 27, 2008

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