VLSI Testing

Random
Random Access
Access Scan
Scan Design
Design
Virendra Singh
Indian Institute of Science (IISc)
Bangalore
virendra@computer.org
E0-286: Testing and Verification of SoC Design
Lecture 18
Mar 7, 2008

E0-286@SERC

No
No Serial
Serial Scan
Scan (???)
(???)
A
A solution
solution to
to test
test power,
power, test
test time
time and
and test
test
data
data volume
volume

Three Problems with serial-scan

Test power
Test application time
Test data volume
Efforts and limitations
ATPG for low test power consumption
Test power

Test length

Test power

Test application time

Reducing scan clock frequency

Scan-chain re-ordering (with additional logic insertion)

Test power/time Design time

Test Compression

Test time/data size Has limited capability for Compacted test

Orthogonal attack
Random access scan instead of Serial-scan
Hardware overhead? Silicon cost << Testing cost

Mar 7, 2008

E0-286@SERC

Random
Random Access
Access Scan
Scan
Saluja et al [ITC04]

Architecture
Each FF has unique
address

Address shift register

X-Y Decoder

Select FF to
write/read

A d d re s s d e c o d e r(y )

CUT

F ilp - flo p s

A d d re s s d e c o d e r(x )

A d d re s s R e g is te r
S c a n - in
Mar 7, 2008

E0-286@SERC

Scan
Scan Operation
Operation Example
Example

Scan operation for t2

Test vector
Test

PPI(ii)

PPO(oi)

t1

00101

00110

t2

00100

00101

t3

11010

11010

t4

00111

01011

t1

t2

1
0

0
0
1
0
1

i1

1
0

1
1
0
0
1
1
0

CUT

o1

i2

0
0
1
0
0

1
1
CUT

0
0
1
0
1

o2

Scan-in
operation

Complete test application

Total number of scan operation = 15
i1

o1

i2 o 2

i3 o 3

i4 o 4

No. of s can

Mar 7, 2008

E0-286@SERC

Test
Test Vector
Vector Ordering
Ordering

Test data volume and Test application

time is proportional to the random
access scan operation
Goal: Reduce # scan operation

V1

5
Test

PPI(ii)

PPO(oi)

t1

00101

00110

t2

00100

00101

t3

11010

11010

t4

00111

01011

# Scan operation = 8
Mar 7, 2008

0
1

Dummy

1
5
5

V2

V4
4

4
5

V3

4
E0-286@SERC

Hamming
Hamming Distance
Distance Reduction
Reduction
Dont care values in PPI do not need scan operation
Use Dont care identification method

1.
2.
3.
4.

Fully specified test vector Vectors w/ X values on targeted bit positions

without loss of fault coverage

Before vector ordering: Identify dont cares in PPI

Vector ordering
Simulate test vector in order / Fill Xs with previous vectors PPO
Identify more Xs on targeted bit in PPI
Change allowed
- odd vector
- even vector
Targeted
5. Repeat 3,4 until no more Xs are identified

TF1

1
X
1
0
X
X

C
U
T

Mar 7, 2008

TF2

1
X
1
1
0

1
0
X
1
X
1
0

C
U
T

TF3

1
X
1
0
1
1
1

X
1
1
1
01
X
1

E0-286@SERC

C
U
T

TF4

1
1
0
1
X
0
1

1
X
1
0
0
1

C
U
T

1
0
0
X
0
6

Optimizing
Optimizing Address
Address Scan
Scan
The cost of address shifting

# of scan operation x ASR width

Example address set = { 1, 5, 6, 11 } for 4-bit ASR
4 X 4 = 16
Proper ordering of address can minimize shifting cost
Apply 11(1011) after 5(0101) needs only 1 left-shift
Minimizing address shifting cost
Construct Address Shifting Distance Graph (ASD-graph)
Find min-cost Hamiltonian path using ATSP algorithm ( Result
: 5 shifts )

0001

1
4

G = < V, E >
3

2
3

2
4

1011

0000

1
3
3
Las t ASR contents of
prev ious tes t v ector

Mar 7, 2008

0101

2
3

E0-286@SERC

0110

V = Aij = {1,5,6,11}
E = {eij | eij is an edge
between vi and vj}
w(eij ) =
The number of
minimum left-shift
operation for the
transition
from vi to vj .

Result
Result (Test
(Test Time/Data)
Time/Data)
Test Application time

Mar 7, 2008

2s
b2

0s
b2

7s
b1

84

s3

85

17
84

s3

59
s3

58

32
s1

Benchmarks

32

RAS

50

2s
b2

0s
b2

7s
b1

84
85

17
s3

s3

84

32
59

50
s3

58
s1

32

07

C lo c k s

RAS

Serial

s1

Serial

1000K
900K
800K
700K
600K
500K
400K
300K
200K
100K
K
07

1000K
900K
800K
700K
600K
500K
400K
300K
200K
100K
K

s1

B its

Test data volume

Benchmarks
E0-286@SERC

Result
Result on
on Power
Power Consumption
Consumption
Switching activity is measured by simulation ( # of switching gate / total # of gate ) X 100 %
Peak Power consumption
Circuit

Serial

RAS

Avg. Power Consumption

Rate(%)

Serial

RAS

Rate(%)

s5378

39.76

12.58

22.79

0.218

0.957

s9234

42.27

10.81

25.57

25.72

0.22

0.857

s13207

38.8

4.15

10.7

24.93

0.052

0.207

s15850

40.75

8.51

20.89

24.55

0.092

0.374

s35932

21.5

0.21

0.96

6.3

0.032

0.506

s38417

34.58

1.46

4.22

23.62

0.001

0.002

s38584

31.31

18.86

60.23

24.23

0.04

0.165

b17s

30.65

5.01

16.34

13.5

0.004

0.033

b20s

37.87

12.37

32.67

24.39

0.006

0.027

b22s

36.52

8.16

22.34

22.67

0.003

0.015

Peak power consumption is reduced 40% to 99%

Average power consumption is negligible!
Mar 7, 2008

E0-286@SERC

Thank You
Mar 7, 2008

E0-286@SERC

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