VLSI Testing

Sequential
Sequential Circuits
Circuits with
with
Combinational
Combinational TG
TG complexity
complexity
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org
E0-286: Testing and Verification of SoC Design
Lecture 19
Mar 17, 2008

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Classification
Classification

Sequential Circuit of
Acyclic structure
Sequential Circuit of
Balance Structure
[Gupta & Breuer]

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Balanced
Balanced Circuit
Circuit ??

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Transformation
Transformation C*
C*
1. For a PI with fanout branches, the set of fanout
branches of the PI is denoted by X. Obtain a
smallest partition of X which satisfies the following
statement:
If branches xi and xj belongs to different blocks X(i)
, X(j) of the partition, then xi and xj are separable.
Each partitioned block is provided with a new PI
separated from original PI.
2. FF are replaced by wires

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Internally
Internally Balanced
Balanced Circuit
Circuit
If a circuit S* resulting from operation 1
in transformation C* on circuit S is a
balanced circuit, then S is regarded as an
internally balanced circuit

Fujiwara TC 2000
Mar 17, 2008

E0-286@SERC

Classification
Classification

Sequential Circuit of
Acyclic structure
Sequential Circuit of
Internally Balance structure
[Fujiwara]
Sequential Circuit of
Balance Structure
[Gupta et al]
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FSM
FSM Realization
Realization
Theorem1 : The necessary and sufficient
condition for realization of an FSM M as an
acyclic structure is mk(I) = O for some
constant, where mk(I) is inductively defined
as m1(I) = m(I) and mk(I) = m(mk-1(I)) for
k>1
Lemma1: The statement that an FSM M is
expressed as mk(I) = O for any k is
equivalent to the statement that M can be
realized by a finite memory machine of
length k. In addition, it is equivalent to the
statement any input sequence of length k
become a synchronizing sequence of M
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FSM
FSM Realization
Realization

Corollary 1: The necessary and sufficient

condition for realization of an FSM M as an
acyclic structure is that M can be realized by a
finite input memory machine
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Acyclic
Acyclic Realization
Realization
Theorem 2: Any sequential circuit of acyclic
structure can be transformed into an
equivalent circuit allowing realization with a
finite input memory, by operation of retiming
and logic duplication

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Transformation
Transformation
Retiming

Logic
Duplication

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Acyclic
Acyclic Seq.
Seq. Circuits
Circuits
Theorem 2: Any FSM allowing realization as an
acyclic structure can be realized as an
internally balanced structure
Theorem 3: An FSM exists which can be
realized as an acyclic structure, but which
cannot be realized as a balanced structure

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FSM
FSM Realization
Realization

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TGC:
TGC: Acyclic
Acyclic Circuits
Circuits

Duplicates

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TGC:
TGC: Balanced
Balanced Circuits
Circuits
C-Transformed circuit

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TGC:
TGC: Internally
Internally Balanced
Balanced
Theorem 4: If a sequential circuit S is an internally
balanced structure, S allows TG with
combinational TG complexity
If fault f in S can be tested, then fault fc in C*(S)
corresponding to f can be testedin C*(S)
It is sufficient to prove that a test pattern Tc for
fc in C*(S) can be generated from the test
sequence T for f in S

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TGC:
TGC: Internally
Internally Balanced
Balanced
If sequential depth of S is d, the length of T is d+1
Assume f can be detected in time frame t at PO zk (1 <
t < d+1)
From this test sequence T, we define the PI value xi in
C*(S) for test pattern Tc, in following way:
1. Case of xi not being a PI resulting from separation:
The sequential depth from xi is uniquely determined.
Let the depth from be dik. The value of xi require to
detect f in T at zk is the value of the PI xi in time frame
t-dik. Therefore the PI value xi in time frame t-dik in T
can be set to define the PI value xi of test pattern Tc.
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TGC:
TGC: Internally
Internally Balanced
Balanced
2. Case xi being a PI resulting from separation
Suppose that the original PI value of xi in S is denoted
x. Although x is a PI in S, xi is not a PI. In C*(S), xi is
a PI. Since this is a case of an internally balance
structure, we can uniquely determine the sequential
depth from xi to zk, which is denoted as dik. The value
of xi required to detect f in T at zk equals the x value
in time frame t-dik. The x value in time frame t-dik in T
is set to define the PI value xi in the test pattern
sequence Tc.

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Internally
Internally Balanced
Balanced Circuit
Circuit

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Internally
Internally Balanced
Balanced

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Kernel
Kernel Extraction
Extraction

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Kernel
Kernel Extraction
Extraction

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Internally
Internally Balanced
Balanced Circuit
Circuit

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Internally
Internally Balanced
Balanced Circuit
Circuit

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Internally
Internally Balanced
Balanced Circuit
Circuit

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Internally
Internally Balanced
Balanced Circuit
Circuit

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Thank You
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