VLSI Testing

Delay Test
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org
E0286: Testing and Verification of SoC Designs
Lecture 23
Mar 26, 2008

E0286@SERC

Path Delay Fault

On-input
cv -> ncv

ncv -> cv

Mar 26, 2008

Side-inputs
Stable cv
Stable ncv
cv -> ncv
ncv -> cv
Stable cv
Stable ncv
cv -> ncv
ncv -> cv
E0286@SERC

Testability
Untestable
Robust
Untestable
Untestable
Robust
NR
FS
2

Robust Test Conditions

Real events on target path.
Controlling events via target path.
V1 V2

V1 V2
U1

V1 V2

S1

U1/R1
V1 V2

Mar 26, 2008

U0/F0

S0

U0/F0
V1 V2

S0

S1
U0/F0

V1 V2

U0

U1
U1/R1

U0

U0/F0

E0286@SERC

U1/R1

U1/R1

A Five-Valued Algebra
Signal States: S0, U0 (F0), S1, U1 (R1), XX.
On-path signals: F0 and R1.
Off-path signals: F0=U0 and R1=U1.
Input 1

S0
U0
S1
U1
XX

S0

U0

S0 S0
S0 U0
S0 U0
S0 U0
S0 U0

S1

U1

S0
U0
S1
U1
XX

S0 S0
U0 U0
U1 XX
U1 XX
XX XX

NOT

Mar 26, 2008

XX

S0

OR
Input 2

Input 2

AND

Input 1

S0 S0
U0 U0
S1 S1
U1 U1
XX XX

S0

Input
U0 S1 U1

XX

S1

U1

XX

S0

U0

E0286@SERC

U0

S1

U1

XX

U0
U0
S1
U1
XX

S1 U1 XX
S1 U1 XX
S1 S1 S1
S1 U1 U1
S1 U1 XX
Ref.:
Lin-Reddy

IEEETCAD-87
4

Robust Test Generation

Test for

P3 falling transition through path P3: Steps A through E

E. Set input of AND gate to

S0 to justify S0 at output
XX S0
C. F0 interpreted as U0;
propagates through
AND gate

Path P3

F0

U0

Mar 26, 2008

U0

D. Change off-path input

to S0 to Propagate R1
through OR gate
R1

A. Place F0 at
path origin

XX

S0
U0

F0

R1

B. Propagate F0 through OR gate;

also propagates as R1 through
NOT gate
E0286@SERC

Robust Test:
S0, F0, U0

Non-Robust Test Generation

Fault

P2 rising transition through path P2 has no robust test.

C. Set input of AND gate to

propagate R1 to output

D. R1 non-robustly propagates
through OR gate since offR1 path input is not S0

XX U1
R1

Path P2

A. Place R1 at
path origin

U1

R1
R1

U1

U0

XX
S0

Mar 26, 2008

Non-robust test requires

Static sensitization:
S0=U0, S1=U1

B. Propagate R1 through OR gate;

interpreted as U1 on off-path signal;
propagates as U0 through NOT gate
E0286@SERC

Non-robust test:
U1, R1, S0
6

Functional Sensitizable TG

Mar 26, 2008

E0286@SERC

FS Untestable Faults
Fault

P2 falling transition through path P2 has no test.

D. F0 cannot be propagated
C. Set input of AND gate to
through OR gate since offpropagate F0 to output
path input is not S0
XX S1
F0
F0
Path P2

A. Place R1 at
path origin

S1

F0
F0

U0

U1

NO TEST

XX
U0

Mar 26, 2008

B. Propagate R1 through OR gate;

interpreted as U1 on off-path signal;
propagates as U0 through NOT gate
E0286@SERC

Slow-Clock Test
Input
latches

Combinational
circuit

Input
test clock

Test
clock
period

Input
test clock

Rated
clock
period

Output
latches
Output
test clock

Output
test clock
V1
applied
Mar 26, 2008

V2
applied Output
latched
E0286@SERC

Enhanced-Scan Test
CK
period
PI

Combinational

PO
CK

circuit
CK TC
SFF

HL

SFF

HOLD

HOLD
V1 settles
SCANIN

CK TC
CK: system clock
TC: test control
HOLD: hold signal
SFF: scan flip-flop
HL: hold latch

Mar 26, 2008

Scanout
result

TC

Scanin
V1
states
V1 PI
applied
E0286@SERC

Scan mode

Normal
mode

HL

Normal
mode

SCANOUT

Scanin
V2 states

Result
latched
V2 PI
applied
10

Normal-Scan Test
V2 states generated, (A) by one-bit scan shift of V1, or
(B) by V1 applied in functional mode.
Combinational

V1 PIs
applied

PO

Scanin
Gen. V2
V1 states states

circuit
CK TC

SCANOUT

Slow clock

SFF
SFF

SCANIN

TC
(A)

Slow CK
period

Mar 26, 2008

TC
(B) Scan mode

E0286@SERC

Path
tested

Result
scanout

Rated
CK period

Scan mode

CK TC
CK: system clock
TC: test control
SFF: scan flip-flop

V2 PIs
applied

Normal
mode

PI

Result
latched

Normal mode

Scan mode

Scan mode

11

Variable-Clock Sequential Test

Off-path
flip-flop
PI

PI

PI
0

n-2

PO

PI

PI

n-1

PO

PI

PO

Initialization sequence
(slow clock)

D
PO

Path
activation
(rated
Clock)

n+1

PO

n+m

PO

Fault effect
propagation
sequence
(slow clock)

Note: Slow-clock makes the circuit fault-free in the presence of

delay faults.
Mar 26, 2008

E0286@SERC

12

Comparing PDF Test Modes

Combinationally
testable PDFs

PDFs
testable
by variableclock seq.
test

All PDFs of
seq. circuit
PDFs testable by
rated-clock seq. test
Ref.: Majumder, et al., VLSI Design - 98
Mar 26, 2008

E0286@SERC

13

Timing Design & Delay Test

Timing simulation:
Critical paths are identified by static (vector-less)
timing analysis tools like Primetime (Synopsys).
Timing or circuit-level simulation using designergenerated functional vectors verifies the design.

Layout optimization: Critical path data are used in

placement and routing. Delay parameter
extraction, timing simulation and layout are
repeated for iterative improvement.
Testing: Some form of at-speed test is necessary.
PDFs for critical paths and all transition faults are
tested.
Mar 26, 2008

E0286@SERC

14

Thank You
Mar 26, 2008

E0286@SERC

15

Thank You
Mar 26, 2008

E0286@SERC

16