University of Malaya

KEEE 4469
Analog VLSI Circuit Design
Dr.Harikrishnan
Department of Electrical Engineering
e-mail: hrkhari@um.edu.my

Course Outline

Course work (mini project)

20 %

Test

20 %

Final Examination

60 %

Reference

CMOS Analog Circuit Design, P.E.Allen and D.R.Holberg, Oxford University

Press, 2002.

Design of Analog CMOS Integrated Circuit,B.Razavi, McGraw Hill, 1999.

Analysis and Design of Analog Integrated Circuits, P.R.Gray, P.J. Hurst, S.H.
Lewis and R.G. Meyer, John Wiley & Sons, Inc., 2009.

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Enhancement- Type MOSFET

Field effect transistor (FET) derives its name from the essence of its physical operation,
where the current-control mechanism is based on an electric field established to the
control terminal.

The current is conducted by only one type of carrier (electrons or holes) depending on the
type of FET (n channel or p channel) which gives FET another name, the unipolar
transistor.

Compared to BJTs, MOS transistors can be made quite small (occupying small silicon
area on IC chip). Digital logic and memory functions can be implemented with circuits that
use only MOSFETs in very-large-scale integrated (VLSI) design.

MOS technology has been applied extensively in the design of analog integrated circuits
and in integrated circuits that combine both analog and digital circuits.

Although the FET family of devices has many different types, the discussion shall be
devoted to the enhancement type MOSFET, which is by far the most significant
semiconductor device available today.

OBJECTIVE : physical operation, terminal characteristic and application.

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Device Structure

Figure 1(a)

Figure 1(b)

The n-channel enhancement device is fabricated on a p-type substrate or body, with two
heavily doped n-type regions indicated in Figure 1 as the n+ source and n+ drain regions.

Metal is deposited on top of the oxide layer to form the gate electrode of the device.

Four terminals are brought out : Gate (G), Source (S), Drain (D) and Substrate / Body / Bulk
(B).

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Device Operation
No Gate Voltage Operation

With no bias voltage applied to the gate, two back-to-back diodes exist in series between
the drain and source. These diodes prevent current conduction from drain to source when
a voltage vDS is applied.

Current Flow Channel

Figure 2
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Device Operation (contd)

A positive gate voltage (vGS) repels the holes of the substrate under the gate, leaving
behind a carrier depletion region, populated by negative charge.

Positive gate voltage attracts electrons from the n+ source and drain regions (where they
are in abundance) into the channel region. When sufficient number of electrons
accumulate near the surface of the substrate under the gate, an n region is in effect
created, connecting the source and drain regions.

If a voltage is applied between the drain and source, current flows through this induced n
region, carried by electron. The induced n region thus forms a channel for current flow
from drain to source and is aptly called so. Correspondingly, the MOSFET is called an nchannel MOSFET of an NMOS transistor.

An n-channel MOSFET is formed in a p-type substrate. The channel is created by

inverting the substrate surface from p type to n type and hence is also called an inversion
layer.

The value of vGS at which a sufficient number of mobile electrons accumulate in the
channel region to form a conducting channel is called the threshold voltage and denoted
as VT.

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Device Operation (contd)

The gate and body of the MOSFET form a parallel plate capacitor with oxide layer being
the dielectric. The positive gate voltage causes positive charge to accumulate on the top
plate of the capacitor. The corresponding negative charge on the bottom plate is formed
by the electrons in the induced channel.

An electric field develops in the vertical direction. It is this field that controls the amount of
charge in the channel and thus it determines the channel conductivity and in turn the
current that will flow through the channel when a voltage vDS is applied.

Applying small vDS

Having induced a channel, if a positive voltage vDS is applied between the drain and
source. The voltage vDS causes a current iD to flow through the induced n channel. Current
is carried by free electrons traveling from source to drain as illustrated in Figure 3(a).

The magnitude of iD depends on the density of electrons in the channel, which in turn
depends on the magnitude of vGS. Specifically, for vGS = VT the channel is just induced and
the current conducted is still negligibly small. As vGS exceeds VT more electrons are
attracted into the channel and increases the charge carriers with increasing channel depth
or conductance. The fact that the conductance of the channel increases with the excess
gate voltage (vGS-VT), also known as the effective voltage.

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Device Operation (contd)

Figure 3(b) shows the sketch of iD versus vDS for various values of vGS.

Figure 3(a)

Figure 3(b)

From Figure 3, it is noted that for the MOSFET to conduct, a channel has to be induced.
Increasing vGS above VT, enhances the channel, hence the name enhancement mode
operation. Finally it is observed that the current that leaves the source terminal (iS) is equal to
the current that enters the drain terminal (iD) and the gate current iG =0.

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Device Operation (contd)

Increasing vDS

With vGS held constant to a value of greater than VT and vDS is increased across the
channel from source to drain as illustrated in Figure 4(a), the voltage increases from 0 to
vDS. Thus the voltage between the gate and points along the channel decreases from vGS
at the source end to vGS vDS at the drain end. Since the channel depth depends on this
voltage, the channel is no longer of uniform depth, rather the channel takes a tapered form
as shown in Figure 4(a).

Figure 4(a)
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Figure 4(b)
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Device Operation (contd)

As vDS is increased, the channel becomes more tapered an its resistance correspondingly
increases. Thus the iD-vDS curve does not continue as a straight line but bends as shown
in Figure 4(b).

Eventually when vDS is increased to the value that reduces the voltage between gate and
channel at the drain end to VT that is vGS vDS = VT the channel depth at the drain end
decreases to almost zero and the channel is said to be pinched off.

Increasing vDS beyond this value has little effect on the channel shape and the current
through the channel remains constant at the value reached for vDS = vGS VT. The drain
current saturates at this value and the MOSFET is said to have entered the saturation
region of operation.

The voltage vDS at which saturation occurs is denoted vDSsat,

v DS,sat = v GS VT

The device operates in saturation region if vDS vDS,sat. The region of the iD-vDS
characteristic obtained for vDS < vDS,sat is called the triode region.

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CMOS

Figure 5

Figure 5 shows a cross section of a CMOS chip illustrating how the PMOS and NMOS
transistors are fabricated. Observe that while the NMOS transistor is implemented directly
in the p-type substrate, the PMOS transistor is fabricated in a specially created n region,
known as an n well. The two devices are isolated from each other by a thick region of
oxide that functions as an insulator.

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Circuit Symbol
NMOS

PMOS

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iD-vDS Characteristic

Figure 6(a)

Figure 6(b)

The characteristic curves in Figure 6(b) indicate that there are three distinct regions of
operation: the cutoff region, the triode region and the saturation region. The saturation
region is used if the FET operates as an amplifier. For operation as a switch, the cutoff
and triode region are utilized.

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NMOS Current Equation

Triode region :

1
W

i D = n C x ( v GS VT ) v DS v 2DS
2
L

Saturation region :
2
1
W
i D = n C x ( v GS VT )
2
L

where, iD

Drain current

Electron mobility

Cox

Capacitance per unit area

Width

Length

vGS

Gate-source voltage

VT

Threshold voltage

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ID Derivation

Q n ( y ) = WC ox Vgs V ( x ) VT
where C ox

(1)

= x t x is the capacitance per unit area.

Triode region of operation is defined as one in which Vgs is large enough to guarantee the
formation of an inversion layer. From (1), zero charge occurs :

Vgs V ( x ) VT = 0

The charge density thus first becomes zero at the drain end at some particular voltage.
The boundary for the triode region is defined by :

Vds = Vgs VT Vdsat

As long as Vds < Vdsat, the device will be in linear region.

I = Q n v
= Q n E

(2)

where is the mobility of charge carriers and E is the electric field.

Substituting (1) into (2) and given that E = dV

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dx

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ID Derivation (contd)

I dx = WC x n Vgs V ( y ) VT dV
0
0
Vds

ID =

W
1

C x n ( Vgs VT ) Vds Vds2

L
2

(3)

With no bias voltage applied to the gate, two back-to-back diodes exist in series between
the drain and source. These diodes prevent current conduction from drain to source when
a voltage Vds is applied.

When Vds is high enough so that the inversion layer does not extend all the way fro,
source to drain, the channel is said to be pinched off. In this case, the field felt by the
channel charge ceases to increase, causing the total current to remain constant despite
increases in Vds.

Calculating the value of this current is easy; all that is needed to do is to substitute Vdsat for
Vds in (3):

ID =

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2
C x n W
( Vgs VT )
2 L

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Circuit Condition Summary- NMOS

Operation Region

Condition

Cutoff

Triode

v GS < VT
iD = 0
v GS VT
v DS < v GS VT
1 2
W
v

V
v

v DS
(
)
GS
T
DS

2
L

i D = n C x

Saturation

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v GS VT
v DS v GS VT

iD =

2
1
W
n C x ( v GS VT )
2
L

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MOS dc Analysis
Example 1
Design the circuit in Figure 1 to obtain a current ID of 0.4 mA. Find the value required for R and find
the dc voltage VD. Let the NMOS transistor have VT = 2 V, nCox = 20 A/V2, L= 10 m and W = 100
m. Neglect the channel length modulation effect.
Example 2
Design the circuit in Figure 2 to establish a drain voltage 0.1 V. What is the effective resistance
between the drain and source at this operating point. Let VT = 1 V and kn(W/L) = 1 mA/V2

Figure 1
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Figure 2
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MOS dc Analysis (contd)

Example 3
Design the circuit so that transistor shown in Figure 3 operates at ID=0.4 mA and VD= +1V. The NMOS
transistor has threshold voltage, VT= 2V, nCox = 20 A/V2 , length, L=10 m and width, W= 400 m.

Example 4
Analyze the circuit in Figure 4 to determine the voltages at all nodes and the currents through all
branches. Let VT = 1 V and kn(W/L) = 1 mA/V2

Figure 3
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Figure 4
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MOS dc Analysis (contd)

Example 5
For the circuit in Figure 5, R1 = 30 k , R2 = 20 k, RD = 20 k, VDD = 5 V, VT= 1 V and kn(W/L) = 0.1
mA/V2. Calculate the drain current and the drain to source voltage
Example 6
Design the circuit in Figure 6, such that IDQ = 0.5 mA and VDSQ = 4 V. Given that VT= 1.2 V and
kn(W/L) = 0.25 mA/V2.

Figure 5
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Figure 6
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