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J. Shukla and B.G. Fernandes
Abstract: A novel soft-switched inverter topology in which three mutually coupled inductors at a
time are involved in the resonance process is proposed. By the introduction of magnetic coupling
between three resonant inductors, the zero-voltage instants for the inverter can be generated by one
auxiliary switch. Also, the resonant energy can be recycled, and the maximum voltage stress on the
auxiliary circuit diode components is conned to the DC-link clamp voltage level. The DC link can
be clamped to 1.11.3 times the DC-source value. This is unlike the soft-switched inverter in which
two mutually coupled inductors are at a time are involved in a resonance process [14], wherein the
clamping diode experiences voltage stress of the order of 11 per unit when clamping the DC-link
voltage at 1.1 per unit. The proposed inverter also provides pulse-width modulated operation. An
analysis of this novel quasi-resonant DC-link inverter topology is presented to reveal its softswitching characteristics. Simulation and laboratory experiments are performed to validate the
analysis.
Introduction
Principle of operation
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93
i3
+
L1
i1
L2
+
D3
IO
L3
Sa
Sb
Sc
VC
Sa
L2
S2
IO
L1
i2
Vs
i3
D3
i1
i2
Sb
S2
Sc
Sa
Sc
VC
Sa
Sb
Sc
D2
D2
IM
IM
a
Fig. 1
Sb
Vs
Inverters
a Passively clamped QRDCL inverter with mutually coupled inductors proposed in [14]
b Quasi-resonant inverter using separate low-voltage DC source for clamping purpose [14]
D1
i1
VC
CF
L1
+
L2
i2
Vs
CR
S2
Fig. 3
VC
D
R
D3
Io
L3
i3
D2
Fig. 4
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as follows:
v CR t t 1
Vs
L1 L2 2M12
ripple is Vs Vc=o1 L1 , where o1 1= L1 CR . The DClink voltage vCR settles to Vs owing to the nite resistance of
the resonant components. This mode of operation ends at
time t1 , when S2 is turned on under the ZV condition to
reduce the DC-link voltage vCR to zero. If we neglect the
resistance of the circuit, the state equations of this mode are
given by
iL1 t t0 Vs Vc=R01 sino1 t t0 Io 1
vCR t t0 Vs Vs Vc coso1 t t0
2
p
p
where R01 L1 =CR and o1 1= L1 CR . Initial conditions for this mode are vCR t0 Vc and iL1 t0 Io .
Fig. 5
i1 t t1 Io
Vs
oL1 L2 2M12
L1 M12 L2 M12
sin
o
t
t
ot t1
1
2
L1 L2 M12
4
i 2 t t 1
Vs
oL1 L2 2M12
"
#
L1 M12 2
o t t 1
sin ot t1
2
L2 L2 M12
5
p
2
,
L12 L1 L2 M12
where, o 1= L12 CRp
=L1
L2 M12 and M12 k12 L1 L2 . Initial conditions for
this mode are vCR t1 Vs, i1 t1 Io , and i2 t1 0. The
duration of this mode is given as
1
A
cos1
t2 t1
6
o
B
where
A Vc
2
VsM23 L1 M12
M13 L1 M12 L2 M12
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95
i1 t
L1
dt
dt
dt CR 0
i3 t i2 t Io dt Vs
7
Z t
di2
di1
di3
1
M21
M23
i1 t i3 t
L2
dt
dt
dt CR 0
i2 t Io dt 0
8
Z t
di3
di1
di2
1
M31
M32
L3
i1 t
dt
dt
dt CR 0
i3 t i2 t Io dt vCF
9
p
p
where M13 k13 L1 L3 , M23 k23 L2 L3 , M12 M21 ,
M23 M32 , and M13 M31 . Initial conditions for this mode
are i1 i1 t2 , i2 i2 t2 , i3 0 and vCR vCR t2 . It was
found that this mode of operation occurs for a negligible
small interval of time. From Fig. 4, it can be observed that
the duration of this mode is very small compared with the
time taken by the DC-link voltage to reduce to zero from
source voltage value (which itself is small). Thus the change
in currents i1 , i2 and i3 during this mode is negligibly small
and can be neglected. Also, as the area enclosed by current
iCF during this mode is negligible, the contribution of this
mode towards steady-state DC-voltage build-up across CF
is neglected. A situation in which three mutually coupled
inductors are involved in a resonance process with CR
occurs twice during the entire circuit operation. One such
situation occurs during this mode, and another occurs
during mode 4 of operation (discussed later). During mode
4 of operation, such a situation lasts for a longer duration
and, hence, is not neglected.
10
i1 t t3 i1 t2
2
t t3 L2 M13 M12 M23 vCF L2 L3 M23
Vs
D
11
i 2 t t 3 i 2 t 2
96
i3 t t3 i3 t2
2
t t3 L1 L2 M12
vCF L2 M13 M12 M23 Vs
D
13
2
2
where D L1 L2 L3 L3 M12
L2 M13
2M12 M13 M23
2
L1 M23 . Initial conditions for this mode are i1 i1 t2 ,
i2 i2 t2 , i3 t2 0 and vCR 0. It should be noted that
the initial conditions for currents i1 ; i2 and i3 are their
respective values at the end of mode 1 (the effect of mode 2
is neglected), and that of vCR is zero.
The duration of this mode is given as
TZero t4 t3
i2 t2 Io i1 t2 i3 t2 D
14
vCF C Vs E
M12 M23 Vs
2D
15
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i1 t i3 t Io dt Vs 16
L1
dt
dt CR 0
di3
di1
1
M13
L3
dt
dt CR
i1 t i3 t Io dt vCF 17
Vs Vc
t t7 iL1 t7
L1
vCR t t7 Vs vCF
21
22
t8 t7
Io i1 t7 L1
Vs Vs vCF
23
24
iL1 t t6 Io i1 t6 Io coso1 t t6
Vs vCR t6
sino1 t t6
R01
18
19
2ab2 4b2 c2 a2 c2
1
A
t7 t6
tan1 @
2b2 c2
o1
20
where a Vs vCR t6 , b i1 t6 Io R01 and c vCF .
Fig. 6
Plot of vCF against iCF ;area;average , TZero and zero-voltage turn-off time available for S2
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97
Fig. 7
25
Simulation results
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Fig. 8
Zero-voltage
time period
Tzero
Clamp voltage
Available
level Vs vCF zero-voltage
turn-off
period for S2
k12 m
decreases
negligible
change
increases
k13 m
negligible
change
decreases
increases
k23 m
negligible
change
increases
negligible
change
CR m
increases
decreases
decreases
L1 m
increases
decreases
decreases
L2 m
decreases
marginal
increase
marginal
increase
L3 m
negligible
change
increases
negligible
change
Simulation results
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99
PWM
Command
Generator
(Phase A)
Sa
Q
D
To Phase A
Flip
Switches
Flop
Q
CLK
Sb
PWM
Command
Generator
(Phase B)
Q
D
Flip
Flop
Q
CLK
Sc
D
To Phase B
Switches
Sd
Se
D D Q
To Phase C
Flip
Switches
Flop
Q
CLK
Sf
PWM
Command
Generator
(Phase C)
Link
Detector
Edge
Detector
Mono
Shot
To Auxiliary
Switch S2
Fig. 10
Table 2: List of SABER templates used for simulating various circuit components and power dissipated in them for different
values of inverter switching frequencies
Circuit component
SABER
template
Template properties/
comments
Power dissipated
with SPWM, 5 kHz
Power dissipated
with SPWM, 6 kHz
Power dissipated
with SPWM, 7 kHz
r 220 mO
9.1 W
9.81 W
10.9 W
r 80 mO
0.52 W
1.86 W
1.91 W
r 120 mO
0.18 W
0.45 W
0.55 W
Switch S2
irg4ph50u
4.5 W
9W
10.5 W
Diode D1
mur10150e
0.21 W
0.33 W
0.6 W
Diode D3
mur10150e
0.84 W
2.59 W
4W
Inverter switches
irg4ph40u
48 W
52 W
60 W
Free-wheeling
diodes across
inverter switches
dp
5.2 W
5.7 W
6.2 W
68.55 W
81.74 W
94.66 W
Total
Load and source parameters are: RL 19.68 O, LL 63.94 O, Vs 600 V, Power factor 0.7, Output power 3.6 kW
100
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Average switching
frequency of S2, kHz
% efficiency
30
98.09
36
97.72
42
97.37
Fig. 11
Experimental results
a DC-link voltage vCR (top trace, 200 Vper division), S2 gate driver
input signal (middle trace, 10 V per division) and current through L2
(bottom trace 16 A per division)
Time: 5 ms per division
b DC-link voltage (top trace 300 V per division), current through L2
(middle trace, 10 A per division), and current through L1 (bottom
trace, 10 A per division)
Time: 5 ms per division
Simulation results
Fig. 12
Experimental results
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101
for about 686 ns. The rise time for the DC-link voltage to
reach clamp voltage level after a brief zero-voltage period is
3.6 ms.
The proposed circuit behaves identically when load
regenerates (Io in Fig. 3 reversed in direction). A simulation
study was carried out during regeneration with Io 50 A
(see Fig. 8d). Figure 10 shows the waveforms of the current
through CF and its voltage during starting. It can be
observed that vCF settles at 100 V, giving a clamp factor of
K 1.16. The on-time of S2 is 1.5 ms.
So that the theoretical efciency of the inverter at
difference switching frequencies can be estimated, the
proposed circuit was simulated using actual SABER
templates for various components. The inverter was
assumed to be feeding an RL load at power factor of 0.7,
Fig. 13
Value
Rated voltage
400 V
Rated line-current
7.8 A
Frequency
50 Hz
Rs
1.1 O
Rr
0.9 O
Xsl
1.8 O
xrl
1.8 O
XM
68 O
Experimental results
a DC-link voltage vCR (top trace, 250 V per division), inverter line-to-line voltage (middle trace, 250 V per division) and current through L1 i1
(bottom trace, 8 A per division)
Time: 20 ms per division
b Waveforms at fundamental frequency of 50 Hz: DC-link voltage vCR (top trace, 500 V per division), inverter line-line voltage (middle trace, 500 V
per division), and motor phase current (bottom trace, 16 A per division)
c Waveforms at fundamental frequency of 60 Hz: inverter lineline voltage (top trace, 300 V per division) and motor phase current (bottom trace,
10 A per division)
Time: 5 ms per division
102
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Experimental results
Conclusions
In this paper, a new circuit topology for a QRDCL softswitching PWM inverter is proposed. It is a simple softswitching topology that is easy to implement and control.
The proposed circuit uses one additional switch to create
zero-voltage instants in the DC link. The maximum voltage
stress on auxiliary circuit diodes is conned to the DC-link
clamp voltage level. Also, the resonant energy associated
with clamping is recycled. The proposed inverter conguration is a solution to the problem of maintaining a
separate low-voltage DC source using a low-power DC-toDC converter for clamping the DC link. It is shown that the
extra resonant energy can be recycled, while the voltage
stress on the clamping diode is maintained equal to the DClink clamp voltage level. The introduction of magnetic
coupling between three resonant inductors can minimise the
device count. Various modes of operation and link waveforms were analysed to reveal the soft-switching characteristics. Simulation and experimental studies were carried out
to verify the proposed concept.
References
9 Appendix
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103
29
i3 t t4 cos373683t t4 8:50709 0:170142i1 t4
33
30
34
7
2:54897 10 i1 t4 t t4 4:77932
108 i2 t4 t t4 373683t t4
35
1 cos1:62534 106 t t5
104
107 t t5 vCF
36
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