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MOSFET operation
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal behavior at low frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal behavior at low frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
[www.intel.com]
Technology
generation
2004
90 nm
2007
2009
65 nm
45 nm
2011
32 nm
2013
22 nm
2015
14 nm
year of
production
1st
1200
ITRS 2003
1000
fT is a measure for
the transistor speed
(see later)
800
600
400
200
100
80
60
40
Gate length [nm]
20
digital
CMOS prototype
for 60GHz
wireless
communication
(UC Berkeley,
2007)
increasing |VGS|
|VOVER| (V)
iTHROUGH
-
vOVER
ITHROUGH
vOVER
vCONTROL
+
vCONTROL
ITHROUGH
vCONTROL
Gate
Bulk
Source
Source
normal operation: iDS
(A)
VGS > 0
VDS 0
VSB 0
saturation
VDS (V)
Gate
More complete:
Drain
normal current
flow IDS
More complete:
Source
Gate
Bulk
Drain
|iDS|
normal operation: (A)
VGS < 0
VDS 0
VSB 0
saturation
|VDS| (V)
Drain
|VGS|=|VGS7| (> |VGS6|)
(A)
6
-3
x 10
W = 10 m
L= 90 nm
VGS=1.2 V
VGS=1.125 V
VGS=1.05 V
VGS=0.975 V
VGS=0.9 V
VGS=0.825 V
VGS=0.75 V
2
VGS=0.675 V
VGS=0.6 V
1
00
0.2
0.4
0.6
VDS (V)
0.8
VGS=0.525 V
VGS=0.45 V
V
GS=0.375
VGS=0.3
VV
=0.225
=0.15
=0.075
1.2 =0
10
IDS
W
(VGS VT ) VDS 21 VDS2
= C 'ox
L
IDS
W
2
= C 'ox
(VGS VT ) (1 + VDS )
2L
= oversimplification
reality is much more complex, as we will see
11
Ithrough = gm.vcontrol
-
gm: transconductance
Zin =
Zout =
12
Zin
gm . vcontrol
Zout
contact
source
STI
n+
contact
silicide
poly
Si
Leff
oxide
trench
n-
silicide
p bulk
shallow
trench
isolation
tox
n-
drain
silicide
oxide
trench
n+
p
p
This is a so-called planar bulk device
14
Cross-section of a p-MOS up to
contacts
L
gate
contact
contact
silicide
poly
Si
source
silicide
oxide
trench
p+
p-
tox
p-
drain
silicide
p+
oxide
trench
n-well
p-type substrate
15
contact
contact
silicide
poly
Si
source
silicide
oxide
trench
n+
n-
tox
n-
drain
silicide
n+
oxide
trench
p-well
n-well
p-type substrate
16
Metal 8
Metal 7
Metal 6
Metal 5
Metal 4
Metal 3
Metal 2
via contact
Metal 1
contact
p-MOS
n-MOS
17
drain
metal 1
active region
polysilicon
18
gate
source
drain
source
19
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal behavior at low frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
20
+ VGB
-
gate material
gate oxide
induced channel
depletion zone
p-type Si (bulk)
terminal 2
L
21
gate material
gate oxide
source
n+
+ VGB
-
n+
drain
p-type Si (bulk)
Electrons in the silicon are attracted to the interface with the oxide
This happens more when VGB increases
For small VGB values, well below VT, charge made up by the electrons that are
attracted to the interface is macroscopically invisible compared to the charge of the
depletion zone, even if their concentration per volume unit is higher than the concentration
of charges in the depletion zone. If this concentration is higher, then we speak about
an inversion situation
22
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
23
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
24
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
25
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
26
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
27
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
28
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
29
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
30
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
31
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
32
VGS
source
n+
+
-
gate material
gate oxide
current
depletion zone
+ V
SB
p-type Si (bulk)
VGS=VGB-VSB
drain
n+
+ VDS > 0
33
strong inversion:
inversion charge clearly present, forms a well conducting strip
underneath the gate oxide, cfr. parallel-plate capacitance (C = Q/V
or per unit area: C = Q/V)
Here: Cox=QI/(VGB-VT)
VT is the threshold that has to be surmounted by VGB to come into
strong inversion
Moderate inversion:
situation in between
QI dependence on VGB makes transition between exponential and
linear dependence
34
Expression of VT
VT 0 = VFB + 0 + 0
subscript 0
means: VT without
body bias
(see also further)
thermal voltage
kT/q
(25.8 mV at room
temperature)
acceptor concentration
NA
+ a few times Ut
0 = U t ln
ni
intrinsic concentration
in Si (1.2 x 1010 cm-3)
2 Si qN A
C 'ox
poly
Si
source
silicide
n+
drain
n-
n-
silicide
n+
p
p
STI
bulk
# atoms in channel of
downscaled devices is not
much anymore
difference of a few atoms
causes a visible shift of VT
(over)simplified
picture of a MOS
transistor
2008: Physical gate length
= 22nm (65nm node)
37
wanted
gate operation
VGC
+
-
gate
oxide
channel
depletion zone
n+
bulk (or body)
Channel affected by gate control
and by body control
one finds:
VT = VT 0 +
0 + VCB 0
Counteracting
operation from
the body
+ V
CB
-
channelbulk
voltage
VGS
source
n+
+
-
gate
gate oxide
+ V
SB
-
VCB
current
depletion zone
drain
n+
p-type Si (bulk)
+ VDS > 0
-
39
Terminology on inversion
level and VT of a transistor
Inversion level of a transistor corresponds to inversion level
at the source end
Inversion level at drain end is lower than at source end as soon
as VDS > 0 V or, in other words, when VDB>VSB, there is
more body effect at the drain end than at the source end
the VT of a transistor corresponds to VT at the source end
40
(A)
10-5
10-6
10-7
10-8
almost quadratic
dependence
leakage
current when
transistor is off
10-9
exponential
dependence
10-10
10-11
subthreshold slope
ideally 60 mV/decade
10-12
-0.5
-0.1
-0.4
0
-0.3
0.1
weak inversion
-0.2
0.2
-0.1
0.3
0
0.1
0.2 VGS-VT
0.6 VGS (V)
0.4
0.5
=VT
strong inversion
moderate inversion
41
42
iDS
(A)
1.4
x 10
VGS=VGS7
1.2
VGS=VGS6
Increase of
inversion level
at source end
0.8
VGS=VGS5
0.6
VGS=VGS4
0.4
VGS=VGS3
0.2
VGS=VGS2
VGS=VGS1
0.5
1.5
2.5
VDS (V)
43
IDS
(A)
1.4
VGS=VGS7
1.2
Nonsaturation
or triode region saturation
: onset of
saturation
This occurs
at VDS = VDSAT
VGS=VGS6
0.8
VGS=VGS5
0.6
VGS=VGS4
0.4
VGS=VGS3
0.2
VGS=VGS2
saturation voltage
Clearly, VDSAT
is a function of
VGS (at least
in strong inversion)
VGS=VGS1
0
0.5
1.5
VDS (V)
2.5
44
VGS=VGS5
At small VDS:
VGS cannot increase the current,
0.6 of I (V )
VGS can only change the slope
DS
DS
VGS=VGS4
IDS
(A)
VDS = 0V: MOS is a purely
passive device, namely a
voltage-controlled resistor
with small-signal value rds0:
rds 0
IDS
=
VDS
0.4
VGS=VGS3
0.2
VGS=VGS2
VDS =0
VGS=VGS1
0
0
0.5
1.5
VDS (V)
45
W
(VGS VT ) VDS a2 VDS2
= C 'ox
L
with a 1 +
and
2 0 + VSB
VT = VT 0 +
0 + VSB 0
IDS
W
(VGS VT ) VDS 21 VDS2
= C 'ox
L
46
must be independent of x
47
VDSAT
VGS VT
=
a
VDSAT = VGS - VT
48
source
source
gate material
gate oxide
channel
VDS1 < VDSAT
gate material
gate oxide
channel
VDS2 = VDSAT
source
gate material
gate oxide
channel
VDS3 > VDSAT
source
gate material
gate oxide
channel
VDS4 > VDS3
drain
drain
drain
drain
49
Physical interpretation of
saturation in strong inversion
saturation means: IDS does not change when VDS(which is assumed to
be > VDSAT) changes
When part of the channel in the vicinity of the drain end is weakly
inverted, then this part of the channel can be represented as a very
poor conductor, almost an insulator (in which we can neglect the
presence of the electrons that form the drain current). Now, when the
drain voltage changes, which is at the right side of that insulator, then
at the left side of that insulator, nothing is felt of this change.
50
IDS
W
2
= C 'ox
(VGS VT )
2aL
square-law model
IDS
W
2
= C 'ox
VOV
2aL
51
I DS = I drift = W ( Q' I ) E
goes to zero
at VDS=VDSAT
this will then go
to to have a
nonzero IDS
v = E
v at drain end
This is physically impossible. We will correct this later
52
source
gate material
gate oxide
channel
VDSAT
drain
: saturation point
Average horizontal electrical field in strongly inverted part of channel= VDSAT/L
drain
VDS-VDSAT
1.4
x 10
-3
1.2
current increases
for VDS > VDSAT
due to CLM
nonsaturation saturation
0.8
ideal current
source behavior
0.6
IDS
0.4
0.2
W
2
= C 'ox
(VGS VT ) (1 + VDS )
2aL
= IDSAT . (1+. VDS)
= (over)simplified SPICE level 1 model
0.5
VDSAT
1.5
2.5
VDS (V)
54
55
IDS
(A)
10
weak inv.
moderate inv.
-5
10
VGS=0.5V
Log scale
VGS=0.4V
VT = 0.47V
-6
10
VGS=0.3V
-7
10
VGS=0.2V
-8
10
VGS=0.1V
-9
10
VDSAT in
weak inv.
VGS=0V
-10
10
0.5
1.5
VDS (V)
2.5
56
I diff
VGS
(Q' Idrain Q' Isource ) exp
nU t
VGS
exp
nU t
VGD
exp
nU t
VDS
1 exp
nU t
= 1 as soon as
VDS > a few Ut
dependence on VDS
vanishes saturation
VDSAT in weak inversion is a few times Ut
57
|QI|
|QI source|
in saturation:
|QI drain| << |QI source|
Slope = driving force
for diffusion current
|QI drain|
0
source
end
L
drain
end
58
VGS VM
VDS
W
2
1 exp
= C'ox
Ut exp
L 2 2F + VSB
nU
U
t
t
59
60
diffusion
drift
10 -6
10 -7
10 -8
10 -9
10 -10
10 -11
10 -12
-0.5
-0.3
-0.1
0.1
0.3
0.5
VGS-VT (V)
0.7
0.9
1.1
1.3
[Volt]
0.8
DD
0.6
0.4
V
0.2
0
100
80
60
40
Gate length [nm]
20
63
[Volt]
0.8
VGS
range
0.6
V
DD
strong inversion
almost 50 %
of VGS range
is moderate inv.
VT
0.2 V 0.4
moderate inversion
0.2
0
weak inversion
100
80
60
40
Gate length [nm]
20
64
design choice
(determines the
inversion level)
design choice
determined by
specification on the current
weaker dependence
than on VGS, at least
in saturation;
guessed, or
determined from
the rest of the
circuit
65
66
10-8
10-10
10-12
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.1
0.2
V
W (m)
10
10
10
10
10
0.3
0.4
(V)
0.5
0.7
0.8
0.9
1.1
1.2
OV
0.6
IDS L
Cox f(VGS, VDS, VSB)
-2
-4
-6
1.1 1.2
67
68
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal behavior at low frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
69
Small-dimension effects
Long and wide channels:
IDS W
1
IDS
L
71
source
gate material
gate oxide
channel
Ey
Ex
drain
eff =
1 + (VGS VT )
< 0
proportional to 1/tox
73
Velocity saturation
Absolute value of the velocity of electrons in Si is about 105 m/s
at room temperature. This is called the saturation velocity vsat
zero electrical field
s
o
u
r
c
e
x
Average velocity in x direction = 0
d
r
a
i
n
x
v = E
5
10
10
10 5
10
10
EC
10
10
E (V/m)
75
IDS = eff
1
W
1
C 'ox [(VGS VT ) VDS 2 a VDS ]
VDS
L
1+
L EC
<1
Velocity saturation
more severe as L decreases
with EC=vsat/eff
critical electrical field
76
IDSAT =
1 + (VGS
1
W
2
C 'ox
(VGS VT )
VDSAT
2aL
VT )
1+
L EC
(1)
77
IDSAT =
1 + (VGS
1
W
2
C 'ox
(VGS VT )
VDSAT
2aL
VT )
1+
L EC
1
both of the form
1+ x
1
1
1
using
1+ x 1+ y 1+ x + y
and VDSAT VGS-VT and ECvsat/0
we find from eq. (1) on previous slide
IDSAT =
0
(VGS VT )
1 + +
v sat L
W
2
C 'ox
(VGS VT )
2aL
78
0
vsat L
(VGS VT ) + >> 1
IDSAT
W v sat C 'ox
(VGS VT )
2a
79
VDSAT
(
VGS VT )
=
[1 + (VGS VT )]
0
(VGS VT )
1 + +
2av sat L
source
drain
poly
Si
source
silicide
oxide
n+
drain
n- R
IDS
n- R
silicide
n+
p
p
DIBL (continued)
Situation at VDS = 0V
DIBL (continued 2)
Situation at VDS > 0V
85
poly
Si
source
silicide
oxide
n+
tox
n-
n-
drain
silicide
n+
p
p
pocket implants
p
86
VT (V)
0.5
0.4
VT (V)
0.54
0.52
0.3
0.2
0.1
0.5
0.48
0.46
0.44
0.42
10
L (normalized to Lmin)
L=0.18m
0.4
VT ~ (L ) VDS
: DIBL coefficient (> 0)
0.38
0.36
0.34
0
L=2m
0.2 0.4 0.6 0.8
1.8
VDS (V)
87
IDS exp
nUt
89
oxide
trench
gate
gate
oxide
Si bulk
oxide
trench
90
L = 0.18 m
V (Volt)
0.45
0.18 m CMOS
0.4
0.35
L = 2 m
0.3
0.25
0.2
0.3
1.0
10
W (micrometer)
depleted zone in
n-type polysilicon
inversion layer
= extra insulating
layer that adds to oxide
layer
silicided
polysilicon
n-type polysilicon
tox
depletion zone
Similar for p-MOS structure
93
IGSO
IGC
IGCS
IGB
IGCD
10
10
10
10
-9
-10
90 nm CMOS
W = 10 m
L = 90 nm
n-MOS with VGS = 0 V
-11
-12
-13
0.2
0.4
0.6
0.8
1.2
VDS (V)
95
x 10
-3
VGS=0.30
VGS=0.40
VGS=0.50
iDS (A)
VGS=0.60
VGS=0.70
VGS=0.80
0.5
0
0
VGS=0.90
0.2
0.4
0.6
0.8
1
|VDS (V)|
1.2
1.4
1.6
1.8
-3
2.5
x 10
VGS=0.20
VGS=0.30
VGS=0.40
L = 4 m, W/L = 10/0.18
VGS=0.50
VGS=0.60
1.5
iDS (A)
VGS=0.70
VGS=0.80
VGS=0.90
0.5
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
|VDS (V)|
10
-4
10
-6
10
-8
10
-10
10
straight line
= exp. behavior
(weak inversion)
-12
10
0.2
0.4
0.6
0.8
VGS (V)
1.2
1.4
1.6
1.8
1.2
1
|VDSAT| (V)
Long channel
slope < 1
since a > 1
0.8
0.6
45
level 1:
VGS-VT
0.4
0.2
-0.4
-0.2
a few Ut
in weak inversion
0.2
0.4
0.6
0.8
1.2
100
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal equivalent circuit at low
frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
101
D
gm.vgs
gmb.vsb
go
S
B
iDS = f(vGS, vDS, vSB) = IDS + ids
DC
AC, small-signal
i DS
gm =
v GS
i DS
i DS
g0 =
= 1/ro=1/rds=gds g mb =
v SB
v DS
102
gate
+
vgs
gmvgs
ro
source
103
0.8
IDS
(A)
At VDS = 0 V: gm = 0, go 0
regardless of the inversion region
At VDS = 0V: IDS = 0 for any VGS
IDS/ VGS= 0 gm=0
0.6
VGS=VGS4
0.4
VGS=VGS3
drain
gate
vin
0.2
gmvin
ro
VGS=VGS2
0
0
source
VGS=VGS1
0.5
VDS (V)
1.5
2.5
104
IDS
W
2
a
(VGS VT ) VDS 2 VDS
gm =
=
C 'ox
VGS VGS
L
W
= C 'ox
VDS
L
VGS
2aL
long-channel
approximation
W
W
= C 'ox
(VGS VT ) = C 'ox
VOV
aL
aL
(1)
2 I DS
gm =
VOV
W
= 2 C 'ox
I DS
aL
(2)
(3)
106
gm
2
=
I DS VOV
IDSAT
W v sat C 'ox
(VGS VT )
2a
W vsat C 'ox
independent of Vov and L
gm =
2a
gm
1
=
I DS VOV
108
VGS
exp
nU t
g m = I DS / VGS
VGS
1
gm
exp
nU t
nU t
gm
1
=
I DS nU t
109
gm
2
=
I DS VOV
gm
1
=
I DS nU t
10
-4
10
long-channel transistor
-6
gm(S)
10
-8
10
-10
10
-12
10
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
1.2
VOV(V)
111
long-channel transistor
gm/IDS (V-1)
10
proportional to Vov-1 in
strong inversion
10
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
I DS
W
= C 'ox
f (VGS , VDS , VSB )
L
W f
g m = C 'ox
L VGS
g m specified L
required W =
f
C 'ox
VGS
113
1. typically, we choose L
2. next we choose the inversion level
3. based on gm for a given reference
width and the spec on gm, we find the
width for the transistor
the lower the inversion level, the wider the
transistor will be
114
L =180nm
L = 2.00m
gm/IDS (V-1)
30
25
20
15
10
5
0
-0.5
weak inv.
max. and
constant
mod. inv.
0.5
1.5
VGS - VT (V)
strong inv.
115
Study of go
Large in the triode region
Much smaller in saturation
Nonzero due to CLM and DIBL
Dependent both on VGS and VDS
can be decreased by increasing the channel length
3
x 10
-7
2.5
go (A/V)
saturation
1.5
1
0.5
0
0
0.2
0.4
0.6
1
0.8
VDS (V)
1.2
1.4
1.6
1.8
116
g0 =
=
VDS VDS
2
a
(VGS VT ) VDS 2 VDS
C 'ox
L
for VDS = 0 V :
W
g 0 = C 'ox (VGS VT )
L
This is the same expression as for gm in strong inversion, saturation
We will use that when we will calculate the thermal noise from a MOS
transistor.
117
VDD
RL
vout
M1
vin
vin
v out
gm
=
v in
g o + 1 / RL
vout
gate
gm vin
drain
go
source, bulk
v out g m
intrinsic gain =
=
v in
go
118
35
30
VGS=0.20
VGS=0.30
20
VGS=0.40
g /g (-)
25
15
VGS=0.50
VGS=0.60
10
VGS=0.70
VGS=0.80
VGS=0.90
0
0.2
0.4
0.6
1
0.8
VDS (V)
1.2
1.4
1.6
gm/go 20
measured
modeled
15
VDS=1.2 V
10
VDS=0.6 V
Technology
node
(gm/go)max
for Lmin (n-MOS)
180 nm
25 - 30
90 nm
10 - 15
65 nm and
beyond
< 10
0
0.4
0.6
0.8
1.0
1.2
VGS (V)
120
mb
6.7
g /g
6.8
(-)
VGS=0.20
VGS=0.30
VGS=0.40
VGS=0.50
6.6
VGS=0.60
6.5
VGS=0.70
6.4
VGS=0.90
note:
VT0 0.5 V
VGS=0.80
0.2
0.4
0.6
0.8
1.2
1.4
1.6
VDS (V)
121
122
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal equivalent circuit at low
frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
123
125
QI
VG +
+ + + + + + + + + +
gate oxide
B
VS +
+
QB
VB
QG = W QG' ( x )dx
0
VD
QB = W QB' ( x )dx
0
x=0
x=L
QI
VG +
+ + + + + + + + + +
gate oxide
B
VS +
+
VB QB
QG+QG
+
VD
QI
VG +
+ + + + + + + + + +
gate oxide
VS +
+
+
+VS
V
V
D
B QB +QB
Cgsi
QG
=
VS
VG ,VD ,VB
127
and Cbsi
QG
QI
QG+QG
VG +
+ + + + + + + + + +
gate oxide
B
VS +
+
VB QB
+
VD
QI
VG +
+ + + + + + + + + +
gate oxide
VS +
+
+
+VS
V
V
D
B QB +QB
Cbsi
QB
=
VS
VG ,VD ,VB
128
QG
=
VD
and
VG ,VS ,VB
Cbdi
QB
=
VD
VG ,VS ,VB
QG
=
VB
VG ,VS ,VD
129
+ + + + + + + + + +
gate oxide
QI
long channel
QB
B
Cgsi
Cgdi
1 '
= Cox WL
2
1 '
= Cox WL
2
Cbsi = Cbdi
1 '
= Cbc WL
2
'
: capacitance per unit area of the
Cbc
reverse
biased field-induced junction formed
by the inversion layer and the substrate:
C =
'
bc
Cgbi = 0
2 0 + VSB
'
Cox
+ + + + + + + + + +
gate oxide
QI
Cgsi
2 '
= Cox WL
3
Cgdi = 0
Cgbi
< Cox !!
a 1
= Cox
3a
< Cbc
VD has no influence on
QG and QB
'
Cbc
WL
=
'
Cbc
31 + '
Cox
long channel
QB
Cbsi
2 '
= Cbc WL
3
Cbdi = 0
> 0 since bulk is visible at
drain side, due to absence of
inversion layer there
131
+ + + + + + + + + +
long channel
gate oxide
D
QB
B
C gsi = 0
Cbsi = 0
C gdi = 0
Cbdi = 0
Extrinsic capacitors
Extrinsic capacitors
Proportional to W, expressed per unit width
- between gate and source (Cgso W)
[F/m]
Junction capacitors
depend on layout
- between source and bulk (Cjs)
- between drain and bulk (Cjd)
133
gate
Ctop
silicide
poly
Si
tox
n-
n-
COV: overlap
capacitance
134
135
intrinsic (see
previous slides)
intrinsic (see
previous slides)
Usually:
Cjs >> Cbsi
Cjd >> Cbdi
poly
Si
STI
source
tox
n-
silicide
Cjswg
n+
drain
STI
silicide
n+
bulk
Cjsw
Cj
p
p
Cj: bottom plate capacitance (F/m2)
Cjsw: sidewall capacitance (F/m)
Cjswg: sidewall capacitance (F/m) at gate side
137
source
drain
source
gate
gate
gate
gate
lsos
lsogd
lsogs
lsogd
lsos
138
source
drain
source
gate
gate
gate
gate
139
C junction =
C junction V
inverse = 0
Vinverse
1 +
V
j
mj
140
141
triode
region
Cgs/(C'oxWL)
0.8
weak inversion:
only extrinsic
0.6
VDS=0.00
VDS=0.45
0.4
VDS=0.90
VDS=1.35
VDS=1.80
0.2
0
0
0.2
0.4
0.6
VT
0.8
1
VGS (V)
1.2
1.4
1.6
1.8
142
normalized Cgd VSB = 0 V, L = 0.18m,n-MOS of UMC CMOS 180 nm, C'ox = 8.21fF/m2
1
Cgd/(C'oxWL)
0.8
0.6
VDS=0.00
triode
region
VDS=0.45
VDS=0.90
VDS=1.35
VDS=1.80
0.4
0.2
0
0
0.2
0.4
weak inversion:
only extrinsic
0.6
VT
0.8
1
1.2
VGS (V)
1.4
1.6
1.8
143
Cgb/(C'oxWL)
0.2
weak inversion:
series connection of Cox
and depletion layer capacitance
VDS=0.00
VDS=0.45
VDS=0.90
0.15
VDS=1.35
VDS=1.80
0.1
0.05
0.2
0.4
VT
0.6
0.8
1
|VGS| (V)
1.2
1.4
1.6
144
2 2 / 4 + VGB VFB
Cgs
Cgso W
Cgd
Cgdo W
strong inversion
+ Cgbo W
a 1
+ Cgbo W
Cox
3a
2
3
Cox + Cgso W
Cgdo W
junction cap. +
junction cap.
2
3
Cox
2 0 + VSB
145
Iin
Cgs+Cgb
g m v1
AC
short
circuit
i out
gm
current gain:
i in
(Cgs + Cgd + Cgb )
Cgg
146
Expression for fT
gm
gm
= 1 for f =
2 f Cgg
2 Cgg
gm
fT =
2 Cgg
f T (Hz)
10
10
10
10
12
10
180 nm CMOS:
fT in the vicinity
of 60 GHz
8
-0.4
-0.2
0.2
0.4
0.6
V
VT (V)
VGS -(V)
ov
0.8
1.2
1.4
147
W
g m = C 'ox
VOV and C gg C gs 23 C 'ox W L
aL
VOV
fT
2
2 aL
3
2
W v sat C 'ox
gm =
2a
150
65 nm
185
45 nm
280
v sat
fT
2 aL
3
4
148
G'
Rg
Cgd
G
Cgs
Rd
D
gmb
gm
drain
ro
Cgb
S
Rs
Csb
B
Rb
source
Cdb
S'
bulk
Rjs
Rjd
Rsub
B'
149
input impedance
matching network
RG
Cgs+Cgb
source
Rgate
gate
drain
diffusion
polysilicon
metal 1
1 W
RG
3 L
due to distributed
nature
Sheet resistance of
gate material
(polysilicon: 8/)
151
Rgate
gate
drain
1 W
RG
12 L
152
Cgs
drain
Cgd
gmvgs
gmbvsb
ro
source
Cbd
Cbs
bulk
but this model is often used to higher frequencies
note: we neglected RG, RS, RD, RB
153
Qx Qy
Vy
Vx
Cx: transcapacitance
154
Cgs
drain
Cgd
gmbvsb Cmb
dv sb
dt
gmvgs Cm
dv gs
dt
ro
Cbd
source
Cbs
Cmx
Csd
dv gb
dt
bulk
long channel, strong inversion, saturation:
4
Cm =
Cox
15
Cmb =
Cmx = 0
Csd = 0
2 0 + VSB
Cm
155
156
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal behavior at low frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
157
large table
iD(vGS, vDS, vSB, L)
Example:
table for 0.18 m CMOS process
go (vGS, vDS, vSB, L)
Wref = 10 m
gmb (vGS, vDS, vSB, L)
based on simulations with BSIMv3
49 VGS values
Cgs (vGS, vDS, vSB, L)
49 VDS values
9 VSB values
VT(vGS, vDS, vSB, L)
11 L values
size: 100 MB for n-MOS + p-MOS
VDSAT(vGS, vDS, vSB, L)
extrinsic junction capacitors:
2
Sv, white(vGS, vDS, vSB, L) [V /Hz]
not in the table
computed separately, based on
Sv, 1/f(vGS, vDS, vSB, L) [V2/Hz]
number of fingers
158
n1
VGS=0.9
= 14.5 m
0
0
VGS=1.05
VGS=1.2
VGS=0.75
90 nm CMOS IMEC
VSB = 0 V
L = 0.09 m
W = 10 m
VGS=0.6
VGS=0.45
VGS=0.3
0.2
0.4
0.6
0.8
1.2
VDS (V)159
160
source
drain
gate
source
drain
source
lsos
lsogd
lsogs
lsogd
lsos
L = 0.18 m
VSB = 0V
0.51
0.5
0.49
0.48
0.47
0.46
0.45
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS (V)
1.25
x 10
-3
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
0.853 mS
0.75
We need gm = 2 mS
W = 10 m
0.5
0.25
0.853
0
0
0.2
= 23.45 m
This is an acceptable width
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS [V]
165
1.2
depends on amount of
fingers
x 10 -4
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
0.8
0.6
0.0511 mA
0.4
0.2
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS [V]
166
Triode region
go
[mS]
Similar for go
CLM dominates
DIBL dominates
0.6
0.5
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
0.4
0.3
0.2
0.1
34 S
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
VDS [V]
Wref
N.B.: gm/go = 2 mS/0.08 mS = 25
167
1.2
x 10
-14
8.51 fF
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
Cgs
Cgd
CsbI
CdbI
Cgb
0.8
0.6
0.4
0.2
0 0
Cgs = Cgs
0.2
W = Wref
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS [V]
W
23.45
= 8.51 fF
= 20 fF
Wref
10
Similarly we find: Cgd =8.79 fF, Cgb = 4 fF, Cdbi= 2.62 aF, Csbi = 1.53 fF
168
CdbE = ad
extrinsic part
of Csb
CsbE = as
C j0
VDB
1 +
PB
mj
C j0
VSB
1 +
PB
mj
+ pd
+ ps
C jsw0
VDB
1 +
PBSW
mjsw
C jsw0
VSB
+
1
PBSW
mjsw
+ pdg
+ psg
C jswg 0
VDB
1 +
PBSWG
mjswg
C jswg 0
VSB
+
1
PBSWG
mjswg
bottom-plate
sidewall capacitances
capacitances
Cj0, Cjsw(g)0, PB, PBSW(G), mj and mjsw(g) depend on the CMOS process
For an nMOS in a typical 0.18 m process:
cj0: 1 mF/m2
cjsw0: 13.4 nF/m
cjswg0: 13.4 nF/m
pb: 0.813 V
pbsw: 0.88 V
pbswg: 0.88 V
mj: 0.443
mjsw: 0.33
mjswg: 0.33
For an pMOS: similar values (but pb, pbsw, pbswg < 0)
169
10
CsbE
[fF]
number of fingers
number of fingers
20
10
source
drain
S
D
D D
S
S
D
S
D
S
170
C
[fF]
4 fingers
20
15
10
Cgs
Cgd
Cgb
Cdb
Csb
Dominance of Cgs is even more pronounced in strong inversion
171
1.6
1.4
L = 0.18 m
VDS = 0.6 V
VSB = 0V
1.2
1
0.8
0.6
0.4
0.2
0.09 V
0
-0.2
-0.4
-0.5
0.5
1.5
Vov [V]
OK !
172