INTRODUCCIN

En esta prctica se nos pidi que hiciramos un semforo con una mquina de estados, ya tenamos
anteriormente un semforo que no funcionaba de manera intermitente; para el actual semforo se
tiene que modificar el tiempo de cada color y adems agregarle una intermitencia al color mbar.

DESARROLLO
La primera parte que se modific del cdigo original fue el delay, el delay original tena un tiempo
fijo pero esta vez necesitbamos un tiempo que pudiramos ajustar de manera externa, as que
aadimos una entrada ms para el tiempo G1_E7_T.

Antes Qp se comparaba con un nmero fijo, pero ahora se compara con la nueva entrada, as que
cada vez que el contador llega al valor de G1_E7_T se manda un pulso hacia el control del semforo.

Despus se modific la mquina de estados que controlaba los colores que se encendan. Se le
agregaron dos salidas a la mquina, una para el semforo peatonal y otra para enviar el tiempo al
delay.

Aqu vemos que en cada estado se especifica un valor para G1_E7_T, el cual despus es enviado al
delay, el cual al llegar a ese valor manda un pulso que regresa al semforo quien despus avanza al
siguiente estado.

Bsicamente fue todo lo que se hizo, lo nico restante es unir los dos componentes en un top. A
continuacin, se puede ver un diagrama de bloques del programa.

ANEXOS
CODIGO DELAY

architecture funcion of G1_E7_DELAY is

signal G1_E7_QP, G1_E7_QN : std_logic_vector(29 downto 0);

begin

comb: process(G1_E7_QP)
begin
if(G1_E7_QP = G1_E7_T)then
G1_E7_QN<=(others => '0');
G1_E7_DELAY<='1';
else
G1_E7_QN<=G1_E7_QP+1;
G1_E7_DELAY<='0';
end if;

end process;

sec: process(G1_E7_CLK, G1_E7_RST)

begin
if(G1_E7_RST = '1')then
G1_E7_QP<=(others => '0');
elsif(G1_E7_CLK = '1' and G1_E7_CLK'event)then
G1_E7_QP<=G1_E7_QN;
end if;
end process;
end architecture;

CDIGO SEMAFORO
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity G1_E7_semaforo is
port(
G1_E7_CLK,G1_E7_RST: in std_logic;
G1_E7_C: in std_logic;
G1_E7_RAV: out std_logic_vector(2 downto 0);
G1_E7_PT: out std_logic_vector(1 downto 0);
G1_E7_T: out std_logic_vector(29 downto 0)
);
end entity;

architecture funcion of G1_E7_semaforo is

signal Qp,Qn: std_logic_vector (3 downto 0);

begin

comb: process(Qp,G1_E7_C)
begin

Case Qp is

when "0000"=>--s0;
G1_E7_RAV<="001";
G1_E7_PT<="10";
G1_E7_T<="011101110011010110010100000000";
if(G1_E7_C='1') then

-- 5 seg verde

Qn<="0001";
else
Qn<="0000";
end if;

when "0001"=>--s1;
G1_E7_RAV<="000";
G1_E7_PT<="10";
G1_E7_T<="000010111110101111000010000000";

-- .5 seg

if(G1_E7_C='1') then
Qn<="0010";
else
Qn<=Qp;
end if;

when "0010"=>--s2;
G1_E7_RAV<="001";
G1_E7_PT<="10";
G1_E7_T<="000010111110101111000010000000";
parpadeo verde
if(G1_E7_C='1') then
Qn<="0011";
else
Qn<=Qp;
end if;

when "0011"=>--s3;
G1_E7_RAV<="000";
G1_E7_PT<="10";

-- .5 seg

1er

G1_E7_T<="000010111110101111000010000000";

-- .5 seg

if(G1_E7_C='1') then
Qn<="0100";
else
Qn<=Qp;
end if;

when "0100"=>--s4;
G1_E7_RAV<="001";
G1_E7_PT<="10";
G1_E7_T<="000010111110101111000010000000";

-- .5 seg2do

verde
if(G1_E7_C='1') then
Qn<="0101";
else
Qn<=Qp;
end if;

when "0101"=>--s5;
G1_E7_RAV<="000";
G1_E7_PT<="10";
G1_E7_T<="000010111110101111000010000000";
if(G1_E7_C='1') then
Qn<="0110";
else
Qn<=Qp;
end if;

-- .5 seg

parpadeo

when "0110"=>--s6;
G1_E7_RAV<="001";
G1_E7_PT<="10";
G1_E7_T<="000010111110101111000010000000";

-- .5 seg3er parpadeo verde

if(G1_E7_C='1') then
Qn<="0111";
else
Qn<=Qp;
end if;

when "0111"=>--s7;
G1_E7_RAV<="010";
G1_E7_PT<="10";
G1_E7_T<="010001111000011010001100000000";

-- 3 seg ambar

if(G1_E7_C='1') then
Qn<="1000";
else
Qn<=Qp;
end if;

when others=>--s8;
G1_E7_RAV<="100";
G1_E7_PT<="01";
G1_E7_T<="111011100110101100101000000000";
if(G1_E7_C='1') then
Qn<="0000";
else
Qn<=Qp;
end if;

-- 10 seg

rojo

--when others=>--s2;
--G1_E7_RAV<="100";
--if(G1_E7_C='1') then
--Qn<="0000";
--else
--Qn<=Qp;
--end if;

end case;
end process;

Sec: process(G1_E7_RST,G1_E7_CLK)
begin
if(G1_E7_RST='1') then
Qp<=(others=>'0');
elsif(G1_E7_CLK='1' and G1_E7_CLK' event) then
Qp<=Qn;
end if;

end process;
end architecture;

CDIGO TOP
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity G1_E7_top_semaforo_automatico is
port(
G1_E7_CLKt,G1_E7_RSTt: in std_logic;
G1_E7_PTt: out std_logic_vector(1 downto 0);
G1_E7_RAVSem: out std_logic_vector(2 downto 0)
);
end entity;

architecture funcion of G1_E7_top_semaforo_automatico is

component G1_E7_DELAY is
port(

G1_E7_CLK, G1_E7_RST : in std_logic;

G1_E7_T: in std_logic_vector(29 downto 0);
G1_E7_DELAY: out std_logic
);
end component;

component G1_E7_SEMAFORO is
port(

G1_E7_CLK,G1_E7_RST: in std_logic;
G1_E7_C: in std_logic;
G1_E7_RAV: out std_logic_vector(2 downto 0);
G1_E7_PT: out std_logic_vector(1 downto 0);
G1_E7_T: out std_logic_vector(29 downto 0)

);
end component;

signal G1_E7_sem: STD_LOGIC;

signal G1_E7_Tt: std_logic_vector(29 downto 0);

begin

m0: G1_E7_delay port map (G1_E7_CLK=>G1_E7_CLKt,

G1_E7_RST=>G1_E7_RSTt,
G1_E7_T=>G1_E7_Tt,
G1_E7_DELAY=>G1_E7_sem);

m1: G1_E7_semaforo port map(G1_E7_CLK=>G1_E7_CLKt,

G1_E7_RST=>G1_E7_RSTt,
G1_E7_C=>G1_E7_sem,
G1_E7_RAV=>G1_E7_ravsem,
G1_E7_PT=>G1_E7_PTt,
G1_E7_T=>G1_E7_Tt);

end architecture;