Self-Aligned Graphene-on-SiC and Graphene-on-Si MOSFETs on 75 mm Wafers

J. S. Moonl), D. Curtisl), M. Hul), S. Bui, D. Wheeler, T. Marshall, H. Sharifi, D. Wong, D. K.

Gaskiltl), P. M. Campbe1l2), P. Asbeck3), G. Jemigan2>, J. Tedesco2), B. VanMil2>, R. Myers
Ward2), C. Eddy, Jr. 2), X. Weng4), J. Robinson4), and M. Fanton4)
1) HRL Laboratories,LLC,3011 Malibu Canyon Road,Malibu,CA 90265
2) Naval Research Laboratories,4555 Overlook Ave.,SW,Washington,DC 20375
3) University of California at San Diego,9500 Gilman Drive,La lolla,CA 92093
4) Electro-Optics Center,Penn State University,University Park,PA 16802

2
Graphene has shown the highest carrier Hall mobility of> 100,000 cm /Vs with theoretical saturation
velocity (Vsat) and source-injection velocity converging at 5E7 cm/sec [1] and 6E7 cm/sec, respectively.

A potential combination of high current-carrying density, transconductance, and low access resistance
could make graphene an attractive candidate for high-performance RF applications. So far, epitaxial
graphene MOSFETs [2] in the early stages of development have revealed technical challenges: the current
voltage characteristics are quasi-linear with weak saturation behaviors and low transconductance per gate
capacitance 100 mS/mm). In addition, the lon/loff ratio has been <10. While epitaxial graphene RF FETs
with Fmax of 14 GHz per 2 f..lm gate length were demonstrated in a self-aligned top-gated layout with the

highest ever on-state current density of 3 A/mm at Vds = 5 V, field-effect mobility was limited below 200
2
cm /Vs. There are only a few reports of a graphene-on-Si platform with on-stage current <0.02 mA/mm. [3]
In this talk, we present recent progress in epitaxial graphene n-MOSFETs and p-MOSFETs on both
SiC and Si substrates for graphene-on-SiC and graphene-on-Si technologies. Both graphene MOSFETs
were fabricated in a self-aligned manner on 75 mm wafers and exhibited gate-controlled ambipolar
characteristics. For the graphene MOSFETs on SiC substrates, the graphene was grown by Si-sublimation
of Si-face 6H-SiC substrates in a commercial Aixtron VP50S epitaxial reactor. For the graphene MOSFETs
on Si substrates, the graphene was synthesized by graphitizing a thin 3C-SiC layer grown on float-zone Si
(111) substrates using a halogen process. Figure 1 shows sheet resistance maps of 3-inch graphene-on-SiC
2
and graphene-on-Si wafers. Typical Hall mobility ranges from 500 to 2000 cm /Vs depending on electron
carrier density. Both graphene MOSFETs were fabricated with a gate oxide layer and metal gate stack. The
gate length was 3 f..lm. The graphene-on-SiC MOSFETs showed excellent I-V saturation behavior as shown
in Figure 2(a). Figure 2(b) shows measured ambipolar behaviors with n-type MOSFET at Vgs
p-type behaviors are observed at Vgs <-1.5 V.

= 0 V, while

An lon/loff ratio of 33 was measured. Figure 2(c) shows

measured peak transconductance of 600 mS/mm at Vds = 3 V. Figure 3 shows the extrinsic field-effect
2
2
mobility of 6000 cm /Vs for electron and of 3200 cm /Vs for hole obtained at an effective electric field of
0.27 MV/cm, approaching Dirac point. The measured graphene field-effect mobility is eight to 10 times
higher than that of ITRS Si n-MOSFETs and SO times higher than that of ultra-thin-body SOl n
MOSFETs.
The graphene-on-Si MOSFETs are fabricated in a similar manner. Figure 4 shows measured transfer
curves of graphene-on-Si MOSFETs, showing ambipolar behaviors with the Dirac point close to zero gate
bias, unlike the graphene-on-SiC MOSFETs. The on-state current is measured at 50 to 125 mA/mm with

lon/loff ratio of 3 to 2, respectively. This is the highest performance observed among graphene-on-Si
technologies so far. RF performance of graphene FETs will be discussed. This work was supported by
DARPA, monitored by Dr. M. Fritze, under SPAWAR contract number N66001-0S-C-204S.
The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be
interpreted as representing the official views or policies, either expressed or implied. of the Defense Advanced Research Projects Agency
or the Department of Defense.

[1] A. Akturk and N. Goldsman,1. Appl. Phys. Vol. 103,p. 053702,2008

[2] C. Berger et aI.,Science,vol. 312,p. 1191,2006; Wu et aI.,Appl. Phys. Lett.,vol. 92,p092102,2008; 1. Kedzierski
et aI.,IEEE Trans. Elect. Dev,vol. 55,p2078,2008; 1.S. Moon et aI.,IEEE EDL.,vol 30,p650,2009
[3] H. Kang et aI.,ISDRS,2009

Presenting and contact author: Jeong-S. Moon,

HRL Laboratories, 3011 Malibu Canyon Rd. Malibu, CA 90265
Phone: (310) 317-5461, Fax: (310) 317-5485 Email: jmoon@HRL.com

978-1-4244-7870-5/101$26.00 2010 IEEE

209

maps of a 3-inch graphene-on-SiC wafer is shown with mobility of 840

Figure

cm2Ns and carrier density of 1.8E 13 /cm2,(b) A sheet resistance map of a 3-inch graphene-on-Si wafer
is shown with a graphene-on-Si wafer are shown with mobility of 950 cm2Ns and carrier density of
6EII /cm2. (c) An optical photograph of fabricated MOSFETs on 3-inch graphene-on-Si wafer is shown.

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978-1-4244-7870-5/101$26.00 2010 IEEE

210

122

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