Contents

Foreword

ix

Preface

xv

Acknowledgments
Chapter 1

Fundamentals of Quantitative Design and Analysis

1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13

Chapter 2

xxiii

Introduction
Classes of Computers
Defining Computer Architecture
Trends in Technology
Trends in Power and Energy in Integrated Circuits
Trends in Cost
Dependability
Measuring, Reporting, and Summarizing Performance
Quantitative Principles of Computer Design
Putting It All Together: Performance, Price, and Power
Fallacies and Pitfalls
Concluding Remarks
Historical Perspectives and References
Case Studies and Exercises by Diana Franklin

2
5
11
17
21
27
33
36
44
52
55
59
61
61

Memory Hierarchy Design

2.1
2.2
2.3
2.4
2.5
2.6
2.7

Introduction
Ten Advanced Optimizations of Cache Performance
Memory Technology and Optimizations
Protection: Virtual Memory and Virtual Machines
Crosscutting Issues: The Design of Memory Hierarchies
Putting It All Together: Memory Hierachies in the
ARM Cortex-A8 and Intel Core i7
Fallacies and Pitfalls

72
78
96
105
112
113
125

xi
Computer Architecture: A Quantitative Approach
2012 Elsevier, Inc. All rights reserved.

xii

Contents

2.8
2.9

Chapter 3

3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16

Instruction-Level Parallelism: Concepts and Challenges

Basic Compiler Techniques for Exposing ILP
Reducing Branch Costs with Advanced Branch Prediction
Overcoming Data Hazards with Dynamic Scheduling
Dynamic Scheduling: Examples and the Algorithm
Hardware-Based Speculation
Exploiting ILP Using Multiple Issue and Static Scheduling
Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and
Speculation
Advanced Techniques for Instruction Delivery and Speculation
Studies of the Limitations of ILP
Cross-Cutting Issues: ILP Approaches and the Memory System
Multithreading: Exploiting Thread-Level Parallelism to Improve
Uniprocessor Throughput
Putting It All Together: The Intel Core i7 and ARM Cortex-A8
Fallacies and Pitfalls
Concluding Remarks: Whats Ahead?
Historical Perspective and References
Case Studies and Exercises by Jason D. Bakos and Robert P. Colwell

131

148
156
162
167
176
183
192
197
202
213
221
223
233
241
245
247
247

Data-Level Parallelism in Vector, SIMD, and GPU Architectures

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Introduction
Vector Architecture
SIMD Instruction Set Extensions for Multimedia
Graphics Processing Units
Detecting and Enhancing Loop-Level Parallelism
Crosscutting Issues
Putting It All Together: Mobile versus Server GPUs
and Tesla versus Core i7
4.8 Fallacies and Pitfalls
4.9 Concluding Remarks
4.10 Historical Perspective and References
Case Study and Exercises by Jason D. Bakos

Chapter 5

129
131

Instruction-Level Parallelism and Its Exploitation

3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8

Chapter 4

Concluding Remarks: Looking Ahead

Historical Perspective and References
Case Studies and Exercises by Norman P. Jouppi,
Naveen Muralimanohar, and Sheng Li

262
264
282
288
315
322
323
330
332
334
334

Thread-Level Parallelism
5.1
5.2
5.3

Introduction
Centralized Shared-Memory Architectures
Performance of Symmetric Shared-Memory Multiprocessors
Computer Architecture: A Quantitative Approach
2012 Elsevier, Inc. All rights reserved.

344
351
366

Contents

5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11

Chapter 6

378
386
392
395
400
405
409
412
412

Introduction
Programming Models and Workloads for Warehouse-Scale Computers
Computer Architecture of Warehouse-Scale Computers
Physical Infrastructure and Costs of Warehouse-Scale Computers
Cloud Computing: The Return of Utility Computing
Crosscutting Issues
Putting It All Together: A Google Warehouse-Scale Computer
Fallacies and Pitfalls
Concluding Remarks
Historical Perspectives and References
Case Studies and Exercises by Parthasarathy Ranganathan

432
436
441
446
455
461
464
471
475
476
476

Instruction Set Principles

A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.12

Appendix B

Distributed Shared-Memory and Directory-Based Coherence

Synchronization: The Basics
Models of Memory Consistency: An Introduction
Crosscutting Issues
Putting It All Together: Multicore Processors and Their Performance
Fallacies and Pitfalls
Concluding Remarks
Historical Perspectives and References
Case Studies and Exercises by Amr Zaky and David A. Wood

xiii

Warehouse-Scale Computers to Exploit Request-Level and

Data-Level Parallelism
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10

Appendix A

Introduction
Classifying Instruction Set Architectures
Memory Addressing
Type and Size of Operands
Operations in the Instruction Set
Instructions for Control Flow
Encoding an Instruction Set
Crosscutting Issues: The Role of Compilers
Putting It All Together: The MIPS Architecture
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References
Exercises by Gregory D. Peterson

A-2
A-3
A-7
A-13
A-14
A-16
A-21
A-24
A-32
A-39
A-45
A-47
A-47

Review of Memory Hierarchy

B.1
B.2
B.3

Introduction
Cache Performance
Six Basic Cache Optimizations

Computer Architecture: A Quantitative Approach

2012 Elsevier, Inc. All rights reserved.

B-2
B-16
B-22

xiv

Contents

B.4
B.5
B.6
B.7
B.8

Appendix C

Virtual Memory
Protection and Examples of Virtual Memory
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References
Exercises by Amr Zaky

B-40
B-49
B-57
B-59
B-59
B-60

Pipelining: Basic and Intermediate Concepts

C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10

Introduction
The Major Hurdle of PipeliningPipeline Hazards
How Is Pipelining Implemented?
What Makes Pipelining Hard to Implement?
Extending the MIPS Pipeline to Handle Multicycle Operations
Putting It All Together: The MIPS R4000 Pipeline
Crosscutting Issues
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References
Updated Exercises by Diana Franklin

C-2
C-11
C-30
C-43
C-51
C-61
C-70
C-80
C-81
C-81
C-82

Online Appendices
Appendix D

Storage Systems

Appendix E

Embedded Systems
By Thomas M. Conte

Appendix F

Interconnection Networks
Revised by Timothy M. Pinkston and Jos Duato

Appendix G

Vector Processors in More Depth

Revised by Krste Asanovic

Appendix H

Hardware and Software for VLIW and EPIC

Large-Scale Multiprocessors and Scientific Applications
Computer Arithmetic
by David Goldberg

Appendix I
Appendix J

Appendix K

Survey of Instruction Set Architectures

Appendix L

Historical Perspectives and References

References
Index

R-1
I-1

Computer Architecture: A Quantitative Approach

2012 Elsevier, Inc. All rights reserved.