Documente Academic
Documente Profesional
Documente Cultură
EtherCAT
2014. 12. 22
-1-
제1장 Introduction
목차
EtherCAT Overview
-2-
제1장 Introduction
EtherCAT Overview
Layer Model: Physical, Data Link, and Application Layer
-3-
제1장 Introduction
EtherCAT Overview
Physical Layer
Shielded twisted pair of wires
RJ45 connector standard
PHY for auto negotiation and auto crossover recommended
EtherCAT Overview
Data Link Layer
Links physical and application layer
Operate based on EtherCAT Slave Controller (ESC)
Microcontroller
SPI interface/
Parallel interface
Process Data
EtherCAT Address Space
Interface
FMMU
PHY
EtherCAT Processing Unit
Management
PHY
EtherCAT Overview
Data Link Layer
Frame Structure
-6-
제1장 Introduction
EtherCAT Overview
Data Link Layer
Memory/Registers: Divided into registers and DPRAM
Registers: first 4 kByte of memory
DPRAM: up to 60 kByte, start at 1000h
-7-
제1장 Introduction
EtherCAT Overview
Data Link Layer
SyncManager
Both master and local microcontroller access DPRAM in the ESC
SyncManager is a mechanism to protect data in the DPRAM from
being accessed simultaneously
-8-
제1장 Introduction
Application Layer
State Machine: Init, Pre-Op, Safe-Op, and Op
Slave checks ESC register settings received from master and
mailbox. When appropriate, go next sate in AL status register
-9-
제1장 Introduction
Application Layer
EtherCAT State Machine Registers
- 10 -
제1장 Introduction
EtherCAT
- 11 -
제1장 Introduction
- 12 -
제1장 Introduction
- 13 -
제1장 Introduction
- 14 -
제1장 Introduction
ADR [15:0]
SPI_CLK
DATA [15:0]
MOSI EtherCAT Slave EtherCAT Slave
Microcontroller Microcontroller
Controller (ESC) RD Controller (ESC)
MIS0 ARM Cortex-M3 ET100
ARM Cortex-M3 ET100 WR
SPI_IRQ
BUSY
EEPROM_LOADED IRQ
- 15 -
제1장 Introduction
EtherCAT
- 16 -
제1장 Introduction
- 17 -
제1장 Introduction
Slave
- 18 -
제1장 Introduction
- 19 -
제1장 Introduction
- 20 -
제1장 Introduction
- 21 -
제1장 Introduction
감사합니다.
- 22 -