USB 3.

0 Architecture

June, 2009
Centre of Excellence for FPGA/ASIC Research
NUST School of Electrical Engineering and Computer Sciences

A.D Usama Bin Najam

Research Associate

Muhammad Umer
Research Assistant

Motivation for USB 3.0

Overview

USB 3.0 System Description

Architectural Overview

Super Speed Communication Layers

Super Speed Power Management

Comparison b/w Super Speed USB and USB 2.0

Conclusion

References

USB 3.0 Architecture

To increase data transfer rate

To decrease power consumption

To enable Swift and seamless integration of USB 3.0

into various devices

USB 3.0 Architecture

On Nov 17th,2008 USB 3.0 specifications were released by USB 3.0 promoter
Group

USB 3.0 is also known as Super Speed USB (SS USB)

10 times performance increase over USB 2.0 (480 Mbps)

Supports transfer rates up to 5 Gbps (600 GBps)

Provide better power management features

Provides backward compatibility with earlier standards

Supports127 devices per host controller/ Bus

Full support for real-time data for voice, audio, and video
USB 3.0 Architecture

 USB 3.0 uses Dual Bus Architecture

Provides concurrent operation of SS and nonSS info exchange
Electrically/Mechanically backward and
forward compatible

Main Architectural components include:

USB 3.0 interconnect
USB 3.0 devices
USB 3.0 host

USB 3.0 Architecture

USB Interconnect

The manner in which USB devices are connected to and communicate with
the host over the SS bus
Includes:
Bus Topology: Connection model b/w Usb Devices and the host
Inter-layer Relationship: Usb tasks performed at each layer in the system and

its relationship
Data Flow Models: Information exchange b/w host and devices over the USB
USB Schedule: Scheduling of shared interconnects in order to support isochronous

data transfer and to eliminate arbitration overheads

USB 3.0 Architecture

USB Host

There is only one host in any USB system, which acts as a source or sink of
information

The USB interface to the host system is referred to as the Host Controller

A root hub is integrated within the host system to provide one or more
attachment points

Manages the SS bus and all devices connected to it

Manages Control and Data flow between host and USB devices

USB 3.0 Architecture

USB Devices

Includes Hubs, peripheral devices, functions

Act as a source or sink of information exchange

Each device supports one or more pipes through which the host may
communicate with the device

Simultaneous operation of SS and non-SS modes is not allowed for peripheral

devices

USB 3.0 Architecture


USB 3.0 hub architecture includes logical USB
2.0 and Super Speed USB hubs
USB 3.0 hub provides bus expansion upto 5
levels of hubs and 127 devices
Different kinds of Hubs include:
Root port hubs:
Directly attached to the USB Host Controller.
Hub power is derived from the same source as
the Host Controller

Bus-powered hubs:
Draw all of their power for any internal functions and
downstream

Self-powered hubs:
Separate power supply available

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USB 3.0 Architecture

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USB 3.0 Architecture

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USB 3.0 Architecture

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HUB

HOST

USB 3.0 Architecture

DEVICE

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The physical layer defines the PHY portion of a port and

the physical connection between a downstream port and
the upstream port on a device (chip to Chip delivery)

Unidirectional differential link

Each differential link is initialized by enabling its receiver

termination.
Transmitter managing the status of the receiver termination

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Low frequency periodic signal(LFPS)

Spread Clock CDR

8b/10b encode/ decode

Scrambled/Descrambled

Elasticity Buffer/skips

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Low frequency periodic signal(LFPS)

Used for signal initialization and power management information

Spread Clock CDR

Each PHY has its own clock domain with spread spectrum clocking

(SSC) modulation
No reference clock
Synchronization between transmitter & receiver clock by phase locking

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8b/10b encode/ decode

The transmitter encodes data and control characters into symbols using

8b/10b code
Control symbols are used to achieve byte alignment and are used for
framing data and managing the link

Scrambler/Descrambler
Physical layer receive 8 bit data from the link layer and scrambles the

data to reduce EMI emissions.

Encodes 8 bit scrambled data into 10 bit symbols for transmission over
the physical connection
Receiver decode 10 bit symbols and descrambles, producing 8 bit data
and sent to link layer for further processing
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HUB

HOST

USB 3.0 Architecture

DEVICE

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The link layer provides the link connectivity

Packets are prepared in the link layer to carry data and
control information between the host and a device
Packet framing
Link command definition and usage
Link initialization and flow control
Link power management
Link error rules /recovery
Resets
LTSSM specifications

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Packets delimiters
Packets delimiters describes packet types, packet structures, and CRC

requirements for each packet i-e LMP, TP, ITP & DP e.t.c

Link Commands
The link command section defines special link command structures,

that control various functionalities at the link layer

Link Control/Management
Power management, Link level data integrity, flow control and error

control

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HOST

HUB

USB 3.0 Architecture

DEVICE

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Defines the end to-end communication rules between a

host and device

Protocol layer provide uni cast communication between host

and device

Super Speed protocol provides

for application data
information exchanges between a host and device end point

It is host directed protocol which means the host determines

when application data is transferred between host and
device
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The protocol layer supports reliable delivery of data packets

via explicit acknowledgement packets and retransmission of
lost or corrupt data

The protocol layer allows efficient bus utilization by

concurrently transmitting and receiving over the link.

The protocol provides flow control

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Notifications

Transactions

Transaction packets

Data Packets

Link Management Packets

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Super Speed power management at distinct areas in the bus

architecture, link , device and function
Device sends asynchronous ready notifications to the host
Packets are routed , allowing links that are not involved in data

communication to transition to and/or remain in a low power state

Packets that encounter ports in low power states cause those ports to
transition out of the low power state with indications of the transition
event
Multiple host or device driven link states with progressively lower
power at increased exit latencies

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Logical Idle U0
Period of one or more symbols period when no information is being

transferred on the link

U1/U2 entry flow

Low power states
Either a downstream port or upstream port can initiate request
U1/U2 link state is accomplished using link commands

U3 entry flow

Suspended states (device disconnected)

Only downstream port can initiate U3 entry
Upstream port cannot reject U3 request

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Link Layer Power Management

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USB 3.0 Architecture

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Data Rate

Super speed USB supports data rates upto 5 Gbps (600 MBps)

USB 2.0 supports data rates upto

480Mbps (high speed USB)

12 Mbps (full speed USB)

1.5 Mbps (low speed USB)

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Data Interface and Primary Conductors

USB 2.0 Cable

USB 3.0 Cable

Half Duplex two-wire differential signaling

Dual Simplex, four wire differential signaling

Unidirectional Data flow

Simultaneous bi-directional data flows

Power Pair: VBUS and GND

Power Pair: VBUS and GND

Signal Pair (1 Twisted pair):

Signal Pairs (3 Twisted pairs):

D+ and D-

D+ and DSSTX+ and SSTX- (transmit path)

SSRX+ and SSRX- (Receive Path)
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Bus Transaction Protocol

Super Speed USB:

Uses host directed protocol (host determines when to transfer application data)
Asynchronous traffic flow (Device can asynchronously request service from host)
Packet traffic is explicitly / directly routed (Unicast, not broadcast)

USB 2.0:
Uses host directed protocol
Polled traffic flow (Host use polling to request info from the endpoints)
Packet traffic is broadcasted to all devices

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Power Management
Super Speed USB:
Multi-level link power management supporting idle, sleep, and suspend states
Link-, Device-, and Function-level power management
USB 2.0:
Port-level suspend with two levels of entry/exit latency
Device-level power management

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Bus Power
Super Speed USB:
Increased supply budgets for devices operating at Super Speed
50% increase for unconfigured power
80% increase for configured power
USB 2.0:
Support for low/high bus-powered devices

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Data Transfer types

Super Speed USB:

keeps all the four USB 2.0 transfer types with SS constraints
Bulk transfer has streams capability

USB 2.0:
Four transfer types include: Control, Bulk, Interrupt, Isochronous

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USB 3.0 compliant devices will bring a revolution in the industry in terms of
speed and power efficiency

Backward compatibility will help in reducing the effects to end users

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1.

USB 3.0 Specifications (Revision 1.0)

2.

USB 2.0 Specifications (Revision 2.0)

3.

USB Complete Developers Guide, Book

4.

http://www.usb.org

5.

www.wikipedia.com

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Questions????

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