Assignment 1

1.Q1)
Here the assumption is that the voltage which is applied at the source or drain terminal is considered to
be wholly dropped across the channel. Here we consider the long channel. So the resistance of drain or
source is negligible compared to channel resistance.
As we know the equation for mosfet in triode region is
I=

Wg
C ox((V gV sV t ) V ds0.5 V 2ds)
Lg

the overlap resistance

I =Drain Current

W g=Channel Width

Lg =Channel Length
C ox=oxide capacitance per unit area
=mobility
V g =gate voltage
V s=source voltage
V t =threshold voltage
V ds=voltage between source , drain
The channel resistance is the ratio of change in voltage of drain to source to change in drain current.
Rch =(
(

I 1
)
V ds

1
Lg
I
) =
------1
V ds
W gC ox( V gV sV t V ds )

But the channel resistance can be shown in this

L
Rch = ch g ------2
W gt ch
Now equate both 1 and 2 equations
Lg
L
= ch g
W gCox(V gV s V t V ds) W gt ch
therefore the relation is
ch =

1.Q2)

t ch
C ox(V g V sV tV ds )

Overlap resistance:The overlap part between gate and source/drain causes resistance to the current
flowing through the channel. And the resistance offered by this region is called as overlap resistance.
Equation for overlap resistance is
Roverlap =

overlap l ov
Wt

where overlap=overlap resistivity

l ov =lenght of overlap
W =width of overlap
t=thickness of overlap region
even we can consider it as unit width.
we now that resistivity is inversely proportional to conductivity

So for overlap the expression is

1
overlap=
N ov q
where
is mobility
N ov =the number of charges in overlap region
q=charge of electron.
1.Q3)

Spread resistance

Distance of l

is caused in source/drain region in which the current which flowing from channel spreads in these
regions. The spread resistance is not caused uniformly in source/drain region but we assume that it has
been spread uniformly like cone which is having base at the edge of gate region
as shown in figure above.
Calculating spread resistance
we do integration
taking limits of radius as x to 'l'=this english letter L
x=some distance away from gate edge,here it is considered because the ln(x) has to be finite value
if we take x=0 then ln(0) value is not defined. That is why we take x of some value not 0.
dr
Rspread =
q ND W r
2
where
q=electron charge
W=width of spreading region or channel width
ND is the average number of charges in spreading region
r is a variable
isthe tangential variable
after integration we get the equation as
x
2 ln ( )
l
Rspread =
q ND W
1.Q4)
The transmission line model is

FIGURE1
( z , t )Rzi( z , t )Lz

i ( z ,t )
(z + z , t )=0
t

i ( z , t )Gz (z+ z , t )Cz

(z + z ,t )
i (z + z , t )=0
t

now letting z 0
Now the equations turns into
( z ,t )
i (z ,t )
=Ri ( z ,t )+ L
z
t
i ( z , t )
(z,t)
=Gi(z , t )+C
z
t

These are the coupled equations of transmission line

In the same way we will calculate the contact resistance
Rv
----FIGURE2
x
if we take a contact which is having square cross section above the source or drain.
Here we follow the transmission model to calculate the contact resistance.
It is shown in figure2.
Rsh = the horizontal resistance of small distance x
Rv =the vertical resistance of small distance x
per unit distance both of these resistances are
x
Rsh =R s
W
c
Rv =
Wx
Here
W= width of contact
voltage drop across series resistance
V (x + x )V (x )=I ( x)R sh
x
V ( x + x )V (x )=I ( x)R s
W

current equation is given by

V ( x)
I ( x+ x)I (x )=
Rv
Wx
I ( x+ x)I (x )=V ( x )
c
from above equations it is shown that
dI (x)
W
=V ( x ) ---------1
c
dx
R
dV ( x)
=I (x ) s ---------2
dx
W
decoupling these two equations we get

d 2 I (x) Rs
= I (x)
c
dx2
for this we assume that the current at the entering node is
and the current at the end means at distance L is zero.
So the solution for current is given as
x

I (x)= Aexp +Bexp where =

L

c
Rs

I exp
I exp
A= max
, B= max
L
L
2sinh
2 sinh

we get the solution for I(x) as

L x
sinh
--------3
I ( x)=I max
L
sinh
by substituting 3 into 2 and integrating we get
Lx
R s cosh
V ( x )=I max
W
L
sinh

So now the substituting x=0, we get

I max

Rcsd =

V (0) R s
L
=
coth ( )
I (0)
W

so in the equation given in assignment L=d, L is given in diagram ,but d is given in equation
so here if we consider L as d then the eqution becomes
Rcsd =

V (0) R s
d
=
coth ( )
I (0)
W

if the contact length is small then the Rcsd becomes more

if the contact length is high means d>> then the equation turns into
Rcsd =

Rs
W

1.Q5)
As long as the resistance Rv and R sh are constant through out the region means the voltage to current
ratio has to be constant.
When these to parameters vary then this model is not going to be applicable.
2)
Rchannel :Oxidation(1)----As the oxidation thickness grows then the control over the channel is
effective and the resistance is directly proportional to oxide thickness.
Diffusion(2)-----As the doping concentration varies the channel resistance varies. So for
higher doping the resistance is going to decrease.
Anneal(Reaction)(3)---When we do this dopants in channel go deeper and change the
channel resistance.
Epitaxial of Si/Ge(4)-----In order to make the very high doped region above silicon surface
then we grow epitaxial layer of highly doped region n/p region. Even this changes the channel
resistance.
Lithography(7)------The dimensions of channel are set by this lithography. If we want the
channel window to be large by changing dimensions in lithography we can make it. The resistance is
indirectly depending on this lithography.
Roverlap :Oxidation(1)-----the thickness of oxide affects the overlap resistance. If oxide thickness is
large then we will have more resistance. But when we have smaller thickness of oxide then the overlap
resistance is smaller
Diffusion(2)-------As dopant concentration increases then this resistance decreases. It
indicates there is increment in doping.
Annealing(Reaction)(2)------This decrease the doping by allowing to go deeper. So it affects
overlap resistance.

Rspreading :Sio2-low-k-spacer CVD(6)---------Because of this the current flowing through

source/drain region spreads more. In order to restrict it along the contact then low-k-spacer has to be
small.
Diffusion(2)
Rsh :Diffusion(2)------the doping density in this region is dependent upon the diffusion. If more
doping is there then the sheet resistance is small.
Metal PVD(4)-----if the metal contact width is more then the current directly flows through the
metal contact without spreading. Where as when metal contact width is small then in order to reduce
this sheet resistance then the current spreads in source/drain region.
Anneal(Reaction)(3)---------because of this the doping in source/drain region changes so it
affects the sheet resistance. the depth may vary because of this process.
Rcontact :Metal PVD(4)-----Metal contact width has to be more to reduce the contact resistance.
Anneal(Reaction)(3)------because of this silicidation happens . In this the metal will react
with silicon in order make high doping region in order to reduce the resistance.
Improving contact resistance:
Using the materials like SiGe which gives the barrier height of small are used to reduce the contact
resistance.

c =co exp

2 B s m
)

Where
co is a constant dependent upon metal and the semiconductor. Specific contact
resistivity, c primarily depends upon
the metal-semiconductor work function is B
doping density is N in the semiconductor and
the effective mass of the carrier is m.
1. Specific contact resistivity c decreases as barrier height decreases
2. For a given doping density contact resistance is higher for n-type Si than p-type.
This can be related to the barrier height.
3 Specific contact resistivity c decreases as doping density increases
1. Doping density can't be scaled beyond solubility.
2. N type dopants have higher solid solubility than P type dopants.
Contact Resistance Reduction for Strained N-MOSFET With Silicon-Carbon Source/Drain Utilizing
Aluminum Ion Implant and Aluminum Profile Engineering
single-silicide technology demonstration achieved dual-barrier-height tuning by Al profile engineering
in NiSi contacts and that is applicable in a CMOS process flow. In this technique, Al is introduced by
ion implantation prior to silicidation. Carbon present in n-FETs's Si:C S/D junctions retards Al
diffusion during silicdation. Large amounts of Al atoms will be retained within the NiSi contacts in nFETs, leading to reduction in B .

gate
source

spacer
spacer
Drain

oxide

MODEL FOR ELEVATED SOURCE DRAIN REGIONS

This is used for reducing the contact resistance.
improving channel resistance:

The gate length has to be reduced. We use strain engineering to reduce the effective mass of carriers
and enhance the mobility. This will reduce the resistance of the channel.

nMOS

substrate
Tensile strain in the channel---------------------------------To increase the mobility.
SiGe regions
MODEL FOR STRAIN ENGINEERING.

spreading resistance improvement:

The depth of source/drain has to be reduced. To do that shallow source or drain regions has to be made.
Activation of the dopants reduce the spreading resistance.

3)
Step 1: start with n- wafer <100> orientation
n-Si

Step 2:deposit intrinsic Si and then dope it by implant and anneal to create n+ Si.

n+
n-Si

Step 3:deposit p-type Si on top of n+ layer by CVD.

P region is deposited by CVD because it becomes difficult to make n+ region into p region.

p
n+
n-Si

Step 4 : deposit intrinsic Si and then dope it by implant and anneal to create n+ Si.

n+
p
n+
n-Si

Step 5:creating mask for the middle portion

-------------------------------------------------------------------photoresist
n+
p
n+
n-Si

Step 6: Dry Etching after mask and lithography

Dry etching is also called as plasma etching. Dry etching is anisotropic etching. It is directional.
Because of this the vertical walls will be formed meas we can etch vertically. Wet etching is isotropic
and we cannot get the exact vertical walls. That is why we use dry etching here.

n+
p
n+
n-Si

Step 7:Thermal oxidation of Sio2

Thermal oxidation is the method to grow the oxide layer rapidly over silicon. That is why thermal
oxidation is used here.

n+
p
n+

SiO2

n-Si

Step 8:Lithography & Sio2 etching

Here Lithography is used for making a hole which is used for making Ti/Pt layer underneath of
oxide layer.

----------------------------------------------------------------------

n+
p
n+

SiO2

n-Si

step 9: Lithography
Here again lithography is used after etching sio2 in the above step. Here this is done in order to
restrict Ti/Pt pad at the edges as given in the question paper.
---------------------------------------------------------------

n+
p
n+
n-Si

SiO2

Step 10:Metalization by PVD and Removing metal at the edges

Here after doing metalization the metal which is accumulated over the photo resist will be
removed by lift off method.

Ti/Pt
n+
p

Ti/Pt pad

n+

SiO2

n-Si

Step 11 :Backside metal deposition by PVD.

Ti/Pt
n+
p

Ti/Pt pad

n+

SiO2

n-Si

Backside metal