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MOTOROLA

SEMICONDUCTOR
TECHNICAL

DATA

MC6840
Programmable

Timer

Module

(PTM)

.!,.
A),,),,
l.~:~
:.*L~\,\.
The MC6840 is a programmable
subsystem component of the M6800 Family designed to provide
t,.,
~ ,,.l.,.,$..
,1.
.,
~
*:~\
,:::~
,<$,+
variable system time intervals.
){t t,$.~
t.+
\ :tt+.:?.,:t:i
The MC6840 has three 16-bit binary counters, three corresponding control registers, and a status
\.:?,\\,
+,
,,,.F+
\ ~!,;&~
register. These counters are under software control and may be used to cause system interrupts
.\~<~r..
:,~>.,,,
.~...~.
....+
..+
,.,,.~:,~:;,
andlor generate output signals. The MC6840 may be utilized for such tasks as frequency measure~ L.4!:s+
.<\;:
\ *Y>:
*.
ments, event counting, interval measuring, and similar tasks. The device may be used for square
*;L*
--. ~.\\,\.
~.t.:~,,,
wave generation, gated delay signals, single pulses of controlled duration, and pulse width modul~?~*,., ~
.$
tion as well as system interrupts.
,>~+ $tt<v

Three
Three

MOTOROLA
MOTOROLA

INC , 1988

=
DS9802R3

BLOCK DIAGRAM

E (Enable)

&

Rea,ster

Clock

J!{

,~t..

The average chip-juncti~wt~~$eratu

.,>

re, TJ, in C can be obtained from:

$:

,$>5, -*,
.,d:P:.. 3... ~

where:
TA
OJA
pD
PINT

TJ =TA+ (PD*OJA)
;., $i<
~.s>>,,
:<:*,
.~~
..$.
= Arn~~~m\,fem peratu re, C
= +P@k~dThermal
Resistance, Junction-to-Ambient,
Cm
,~~~~~+ PpORT
, !kd~~

Pp~T3W$=*~ort
.
,4 ~
~ *;.?,,*

(1)

Watts Chip Internal Power

Power Dissipation, Watts User Determined

x Vcc,

~~$@~~#appliCatiOnS
ppORT<plNTand
can be neglected. ppORTmay become significant if the device is configured
.AQ&+$ve Darlington bases or sink LED loads.
~~~~%approximate relationship between PD and TJ (if PpORT is neglected) is:
,,
PD= K: (TJ +273C)
(2)

Solving equations

(1) and (2) for K gives:

(TA+2730C) +0JNPD2
K=PD
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at
equilibrium) for a known TA, Using this value of K, the values of PD and TJ can be obtained by solving equations
(1) and (2) iteratively for any value of TA

MOTOROLA
2

MC6840
DS9802R3

MAXIMUM

RATINGS
Rating

Symbol

Supply Voltage
Input Voltage
Operating Temperature Range TL to TH
MC~,
MC~A40,
MC~B40
MCWOC,

M C6BA40C

Storage Temperature

THERMAL

Range

Value

Unit

Vcc

0.3 to +7.0

V,n

0.3 to +7.0

TA

Oto
40to

Tstg

55to

to protect
to

agatnst

voltages
vised

or electric

that

+70
+85

+150

Value

Symbol

Thermal Resistance
Cerdip
Plastic

fields,

normal

Unit

unused

Inputs

voltage

level

eltner

g.,

Low Voltage

vlL

Input

Leakage

v s s Q,$
, .,,.>?~&:
....
..5
~ .,t. **$*l .0
..,:<.>.!,. $$J
20
,.,., ..}}:,
t$?,:::%
:,::~}:.

Current

Current

Iin

to 5.25 V)
(Vin=

0.5 to 2,4 V)

DO-D7

ITS[

205KA)
2~KA)

DO-D7

v O H,:.,.? V~~+

Other Outputs

Low Voltage

Output

Current

(Off State)

Dissipation

(VOH = 2.4 V)

(Measured

at TA=

TL)

Capacitance

(Vln=O,
Output

TA=250C,

f=l.O

MHz)

f=l.O

MHz)

;%-

2.4

f.$;:~$:,
ii :,+
VSS+2.4
isi~~.*(5.
*?~,~.s~<

Unit

Vcc

VSS+O.8

2.5

PA

10

pA

VSS+O.4

VSS+0,4

.,i.~
$ILOH
.....
-..:*<>. PINT
+:$?1$$.,
tf\
$
>,,p.,~~.D7
Ci
?l$~~fl others

1.0

10

PA

470

7W

mW

12.5
75

pF

5.0

pF

>.

Capacitance

(V,n=O.

or V@&$ , $.~
~, f?.:),:,

mA)

Power

VSS

DO-D7 .2 %Q#
01-05?; :&s~

m,

1.6 mA)

Leakage

Internal
Input

(Vin =0

Input

High Voltage

(l Load =3.2

operation
It IS
Vout be con-

\*,i
,!>$:
.,.:?.
noted) .,ih ~+.,
I T~,?.. ~~ Max

(VCC = 5.o Vdc + 5%, VSS =0, TA= TL to TH unless otherwise

Min
Symbol
Characteristic

Input

(l Load=

to

higher than
this
htgh-

65
100

VSS+2.O

Output

it IS ad-

be taken

cm

9JA

the
static

are tied to an appropr!atewt$~$.

(e

VIH

(lL~ad=
(l Load=

however,

precautions

Input High Voltage

Output

high

to the range VSSS(Vln

or Vout)
Rellabllity of operation
IS enhanced~,

CHARACTERISTICS

HI-Z (Off State)

due

tmpedance
clrcult. For proper
recommended
that V,n and

strained
SVCC.

Characteristic

damage

avoid application
of any voltage
max!mum
rated
voltages
to

CHARACTERISTICS

DC ELECTRICAL

This devtce contains circuitry

Inputs

TA=25C,

%.
.?

,:..>.

Cn,,t

IRQ

,.
AC OPERATING

CHARACTERISTICS

(See Figure:Q~!%&;}$*
..i: $+...i$ kAPcaAn
I

Characteristic

Max

Min

Max

Min

1.0

0.666.

tcyc E + tsu + thd

Input Rise and Fall Times

(Fiaures

I .:cr-~

4 and 5) ~. ~, and RESET

if
Inuut Pulse Width
~As~nchronous

Low (Figure
Input)

2)

Pulse Width

(Asynchronous

High (Figw&~~sp
Input)

~ii~

~$Y

I1

Max

Unit

O.w

:::$; 3:q>%WL
~,({,
~,
:

C, G, and RESET

Input

~~ I

.?:.:
!+>

MC6BB40

MC6BA40

-,
rvvH

tcVcE+

tsu + thd

tcycE+

tsu + thd

tcycE+

tsu + thd

tcyc E + tsu + thd

ns

tcVcE+

ns

tsu + thd

ns

thd

50

50

ns

ion Time (Figure

7)
tsvnc

ln~~:pu]se

Width

C3( 8 Prescaler

Output

V, Load

(V0H=2.4V,
(VOH=O.7
Interrupt

Release

tr and tfs

tcvcE

2m

175

ns

120

80

60

ns

5)

Load D)
Time

PWH

t
TTL

tco

700

460

Mo

ns

MOS

tcm

450

450

MO

ns

tcmos

2.0

1.35

1,0

Us

tlR

1.2

0.9

07

B)

Load D)
VDD,

pWL,

On Iv)

Delay, 01-03 (Figure

(VOH =2.4

MC6840
DS9802R3

Mode

250

(Figure

CMOS
6)

MOTOROLA
3

BUS TIMING

CHARACTERISTICS

(COO~1-+=. I z,~ a,,

--~ Q)
,UUG

Ident.
Numbr

LGa

1,

d,

MC6840 MC68A40

Characteristic

MC68840
Min
Max

..lin

Max

Min

Max

tcvc

1.0

10

0.67

10

0.5

nit

Cycle Time

Pulse Width,

E Low

PWEL

430

9W

280

9500

210

9m

ns

Pulse Width,

E High

PWEH

4W

9W

280

9m

220

9m

ns

tr, tf

25

25

20

ns

tAH

10

10

10

ns

tAS

80

60

40

ns

tcs

80

60

40

Q:.ns

tCH

10

10

10

10

Clock

Address

4..

Rise and Fall Time

Hold Time
;s Setup

Time

Before

14

Chip Select

15

elect Hold
Chip Sf
Time

18
21

Read Data
!

Write

Setu Jp Time
,.,

Hold

,-

Before

Ime

Data Hold Time

:ral Output
sral Input

~!, FI$URE2
..,\:.;?:,
*T:*.*}

Data Delay Time

Data

tDHR1201W01201~.
tDHW

Setup

Time

INPUT PULSE WIDTH LOW

10

10

#s

20 I ~ Qs$f ns
~,Q,
$J*,p~;@ I ns
I ,

tDDR

290

tDSW

~~~

80

I 180 .~ ~.~,~j $~

ns

FIGURE3 INPUT PULSE WIDTH HIGH

MOTOROLA
4

MC6840
DS9802R3

FIGURE4 INPUT SETUP AND HOLD TIMES

FIGURE 5 OUTPUT DELAY

esrpOT
L

300F

NOT E: Timing measurements

MC6840
DS9802R3

are referenced

to and from a low voltage

of 0.8 volts and a high voltage

of 2.0 volts,

unless otherwise

noted.

MOTOROLA
5

DEVICE OPERATION
The

MCW

is part

of the Mm

microprocessor

family

and is fully bus compatible

with MWOO systems. The three
timers in the MC~
operate independently
and in several
distinct modes to fit a wide variety of measurement
and synthesis applications.
The
MCWO
is an integrated,
set of three
distinct
counter/timers.
It consists
of three 16-bit data latches,
three
16-bit
counters
(clocked
independently),
and the
comparison
and enable circuitry
necessary
to implement
various measurement
and synthesis functions.
In addition,
it
contains

interrupt

drivers

to alert the processor

that

a par-

ticular function
has been completed.
In a typical application,
a timer will be loaded by first storing two bytes of data into an associated
Counter Latch. This
data is then transferred
into the counter
via a Counter
initialization
cycle.
If the counter
is enabled,
the counter
decrements
on each subsequent
clock period which may be
an external clock, or Enable (E) until one of several predetermined conditions
causes it to halt or recycle. The timers are
thus programmable,
inputs or the MPU
anv time.
BUS

cyclic in nature, controllable

by external
program,
and accessible
by the MPU at

The Programmable
Timer Module (PTM) interfaces to the
M6BO0 Bus with an 8-bit bidirectional
data bus, two Chip
Select lines, a Read/Write
line, a clock (Enable) line, and interrupt
Request
line, an external
Reset line, and three
Register select lines. VMA should be utilized in conjunction
with an MPU address line into a Chip Select of the PTM
when using the MC6800/6802/680B.
BIDIRECTIONAL
DATA (DGD7) The bidirectional
.data N
t~@skU
lines (DO-D7) allow the transfer of data between
and PTM.
The data bus output
drivers
are t~~$,~$ta$e
devices which remain in the high-impedance
(Q@),%t$~~ ex-

tivated).

the M PU performs
a PTM ~$~~~~eration
and Enable lines high and PT~~$~~~~;Welects ac:*.. i:;?:+
?,$ ?~ .

.,,.,

CHIP SELECT (CSO, CS1 ) T@?e~?W7signals

are used
to activate the Data Bus interfa~{%k~llow
transfer of data
from the PTM. With
C~O = @~an$ CSI = 1, the device is
selected and data transfer,,$~R~,~% fir.
yi

READ/WRITE
MPU to control

!$

(R/~$+
$%is signal is generated
by the
thaj-~%i~~ion
of data transfer on the Data

Bus. With the Pl~~$&lected,

a low state on the PTM R/~
line enables the{~~t
buffers and data is transferred
from the
MPU to the ~~~%nthe
trailing edge of the E (Enable) clock.
Alternat~~T
,J:&fider the same conditions)
R/~=
1 and
Enabl@~$~#!lows
data in the PTM to be read by the MPU.
>.:.+
*,,,.::>.i,,,.>.<,r
.,, ~
!~%~LE
(E CLOCK)
The E clock signal synchronizes
da~;ansfer
between
the MPU and the PTM. It also performs an equivalent
synchronization
function
on the external
clock,

reset,

and gate inputs

of the PTM.

INTERRUPT
REQUEST (~Q)
The active low Interrupt
Request signal is normallv tied directly (or through priority interrupt
circuitry)
to the ~
input of the MPU. This is an

MOTOROLA
6

terrupt Flag (Bit 7 of the Internal Status

The conditions
under which the ~Q
discussed

in conjunction

RESET

with

Register) is asserted.
line is activated
are

the Status

A low level at this input

Register.

is clocked

lnt~ !fi@ PTM

by the E (Enable) input. Two Enable pulses a~~.r~~~~d

to
synchronize
and
process
the
signal.
Th~ ~$~
then
recognizes
the active low
or inactive ~~l~t~~~&ti the third
Enable pulse. If the RESET signal is a~yw~~bus,
an additional Enable period is required if SQ$U9 ttw$s are not met.
The RESET input must be stable ,&@$~P~$$~for the minimum
time stated in the AC Operating;:$~,a]ecteristics.
Recognition
of a low level ~~~hlsh!~put by the PTM causes
the following
action to o~c~s$~~
COUnt
a. All counter latch@ ~r~;$reset to their maximum
.JtQ,ff>
.,.,.&...,>,,?
values.
,i>:,,~:-.....,$.,
b.

All Control %${~~bits

are cleared with the exception
of CRIOJi~~ter~l
reset bit) which is set.

c.

INTERFACE

cept when
(Read/Write

open drain output (no load device on the chip) which permits other similar interrupt
request lines to be tied together in
a wire-OR configuration.
Them
line is activated if, and onlv if, the Composite
in-

All cofi~$~<=.are preset

~:,$..,:
~.~;j,,
, .s.,<.,,>
d. All@ou~$er outputs are
.~;~$w.
.:!..:?~
e.
~$~ Status Register bits
,>..:

:~~:,~:.
SELECT LINES
+r~it,?RwlSTER

to the contents

of the latches.

reset and all counter

(interrupt

flags)

clocks

are

are cleared.

(RSO, RSl~RS2)

These in-

:,.,,,!.i%:~~ts are used in conjunction with the R/W line to select the
* Internal registers, counters and latches as shown in Table 1.
~t!~i.>
~*~:\,,.${\+i
,
.,,.
~t?
NOTE
The PTM is accessed via MPU Load and Store operations
in much the same manner as a memory device. The instructions available with the M6800 family of MPUS which perform read-modify-write
operations on memory should not be
used when the PTM is accessed. These instructions
actually
fetch a byte from memory,
perform
an operation,
then
restore it to the same address location.
Since the PTM uses
the R/~
line as an additional
register
select input,
the
modified
data will not be restored to the same register if
these instructions
are used.
CONTROL

REGISTER

Each timer in the MC6B40 has a corresponding

write-only
Control
Register. Control
Register #2 has a unique address
space (R SO= 1, RS=O, RS2=O) and therefore may be written into at any time. The remaining Control Registers (#1 and
#3) share the Address
Register Select inputs.
CR20

The

Space

selected

least significant

by a logic

bit of Control

zero on all

Register

#2

(CR20) is used as an additional

addressing
bit for Control
Registers #1 and #3. Thus, with all Register selects and R/~
inputs at logic zero, Control Register #1 will be written into if
CR20 is a logic one. Under the same conditions,
Control
Register #3 can also be written into after a RESET low condition has occurred,
since all control
register
bits (except
CR IO) are cleared. Therefore,
one may write in the sequence
CR3, CR2, CRI,

MC6840
DS9802R3

TABLE

1 REGISTER

Register
select Inputs
RS2

RSI

0
1
1
0
0

1
0
1
0
1
o

o
o
o
1

Operations
Rl~

RSO

SELECTION

= O

R/ti

CR20

= O

Write

CR20

= 1

Write Control

Write Control
Write

Write

Register

MSB Buffer

Write Timer

#3

= 1

No Operation

Register #1
Read Status Register

#2

Read Timer

Register

#l

Counter

Read LSB Buffer

Read Timer

Register

Read Timer

Register

Register

#3 Counter

Read LSB Buffer

#3 Latches

.\,

Register

#2 Counter

Read LSB Buffer

#2 Latches

Write MSB Buffer

Write Timer

Register

#1 Latches

MSB Buffer

Write Timer

Control

Register

*,\,

.,k.1+~,,,..,
~,,,
,:), %?
~:: .*:,J!
:,: ~
I}*, \~,}>
$$.~.$,
~..~,
,8,
,*f~,!
**}
~i, t$:,:+
,,,
~,,>i!:
.~~
.*::
.<&@
\.*
,),$ ,,:$,,:$
,.
~:<,:
..... ,..
-,li+

CRIO causes all counters

to be preset with the contents
of
the corresponding
counter
latches, all counter clocks to be
disabled,
and the timer outputs
and interrupt
flags (Status
Register) to be reset. Counter Latches and Control Registers
are undisturbed
by an Internal Reset and mav be written
regardless of the state of CR IO.

%$

the clock input circuitrv

and the i@%~:$p*@ounter #3. It can
therefore be used with either the.int~,~clock
(Enable) or an

CR1O The least significant

bit of Control Register #1 is
used as an Internal Reset bit. When this bit is a logic zero, all
timers are allowed to operate in the modes prescribed
by the
remaining
bits of the control registers. Writing
a one
into

When

s,::;:?

initializing T~@3

$tito the divide-by-eight

mode on

consecutive
E-cycles %~:@~with DMA),
Control Register 3
must be initiali~~~~efore
Timer Latch #3 to insure proper

into

timer initiali~A%~,J
.,<,:... f

The least significant

bit of Control Register #3 is used as a
selector for a -8 prescaler which is available with Timer #3
onlv.

The prescaler,

if selected,

IS effectively

placed

between
~b!:%

TABLE

CONTROL

q#G~$?ER

BITS

rrupt Control

(See Table 3)

!.,

Timer #X Counting
TX configured
TX configured

CR1O Internal

MC6840
DS9802R3

counting

for dual 8-bit counting

CRX1
~+:$

Mode Control

for normal (16-bit)

mode

mode

Timer #X Clock Source

TX uses external

TX uses Enable clock

Reset 8it

All ttmers allowed

to operate

All timers held m preset state

X=l

clock source on ~

CR20 Control Register Address

O
1

CR#3 mav be written

CR#l mav be written
x=2

Blt

input

CR30 Timer #3 Clock Control

O
1

T3 Clock is not prescaled

T3 Clock is prescaled bv B
x=3

MOTOROLA
7

Control Register Bits CR1O, CR20, and CR30 are unique in

that each selects a different
function.
The remaining
bits (1

An interrupt
flag is cleared by a Timer
i.e., External RESET=O
or Internal Reset

Reset con@tion,
Bit (CR1O)= 1. It

through
7) of each Control
Register select common
functions, with a particular
Control Register affecting only its corresponding
timer.

will also be cleared by a Read Timer Counter

vided that the Status Register has previously

Command
probeen read while

the interrupt flag was set. This condition

on the Read Status
Register-Read
Timer Counter (R S-RT) sequence is designed

CRX1
Bit 1 of Control
Register
#1 (CR11 ) selects
whether
an internal or external clock source is to be used
with Timer #l. Similarly,
CR21 selects the clock source for
Timer #2, and CR31 performs this function
for Timer #3. The
function
of each bit of Control Register X can therefore be

to prevent missing interrupts

which might occur after the
status
register
is read, but prior to reading
the Timer
Counter.
An Individual
Interrupt
Flag is also cleared by a Write
Timer Latches (W) command
or a Counter Initializqtf@ie (Cl)

defined

sequence,
responding

provided
that W or Cl affects
to the individual
Interrupt
Flag,

COUNTER

LATCH

as shown

in the remaining

section

of Table

2.

CRX2 Control Register Bit 2 selects whether the binary

information
contained
in the Counter
Latches (and subsequently loaded into the counter)
is to be treated as a single
16-bit word or two 8-bit bytes. In the single 16-bit Counter
Mode (CRX2= O) the counter
will decrement
to zero after
N + 1 enabled [G= O) clock periods, where N is defined as the
16-bit number
in the Counter
Latches.
With
CRX2= 1, a

REGISTER/lNTERRUPT

provided.
are

FLAGS
Register
four Qts

>.!&

pr&~J~~~or

the

register

desired

MSB

latch

Buffer

is

data.

for

the

Three

Register

Most-

addresses

indicated
in
Data from the
into the Most-

(as

the counter
latches provided
first. The storage order must

that the MS B is transferred

be observed to ensure proper

,-

latch oDeration.
In many applications,
the source of the data will be an
M6800 Family MPU. It should be noted that the 16-bit store
operations
of the M68~
family microprocessors
(STS and
STX) transfer data in the order required by the PTM. A Store
Index Register Instruction,
for example,
results in the MSB

condil~~~;~~r
asserting
thwqfd~
be expressed
..
,Y,\,r !!?;?,.Jr,
,,,.
.x
),:
12. CR26&f~;$@%
*jt

of the X register being transferred

to the selected
then the LSB of the X register being written
into
higher
location.
Thus, either the index register
pointer
may be transferred
directly
latch with a single instruction,

INT = Composl@~j~~$~&&pt
Flag (Bit 7)
11= Timer #~Qln~~rrupt Flag (Bit O)
12= Tirq@,#2 ~kerrupt
13= ~~&~~2
Interrupt
*), v+y!~

of a 16-bit

f$?$niflcant
Byte of Timer #X when a Write Timer #X Latches
.$
~$.,~$~kmand
is performed.
So it can be seen that the MC6840
f$~~~;has been designed to allow transfer of two bytes of data into

has an internal
Read-Only
Status
four Interrupt
Flags, (The remaining

IIo CR16+

only

of the

Ta&e 1), %ut they all lead to the same Buffer.

Wy&$JBuffer will automatically
be transferred

trol Register is at a logic one, The

the composite
Interrupt
Flag bit can
as:
INT=

iFmi$~~write

Signific(~tt.Q~]~

of the register are not used, and defaults to zeros whe~~~;

ing read.; Bits O, 1, and 2 are assigned to Timers 1, 20,3NQ @
respectively,
as individual flag bits, while Bit 7 is a,<$o<~~~$~te
Interrupt
Flag. This flag bit will be asserted if{~~~$~~<$~e individual flag bits is set while Bit 6 of the cor~~sw~$~$fig Con-

where

tim~$~~~~~sts

contents
to the counter.
~~}~Q@s
in Table 4 regarding the
binary number N, L, or$@~~*d
into the Latches and their
relationship
to the ~,~~~,~,.waveforms
and counter
Time.,.~:2,
>.b.3*
outs.
:..~:..<
~.$,,
,,\\,,,
Since the PT~,,da;~:$us
is 8-bits wide and the counters are
16-bits wide, ~~~borary
register (MSB Buffer Register) is

CRX3-CRX7
Control
Register 8its 3, 4, and 5 are explained in detail in the Timer Operating
Mode section. Bit 6 is
an interrupt
mask bit which will be explained
more fully in
conjunction
with the Status Register,
and bit 7 is used to
enable the corresponding
Timer Output.
A summary of the
control register programming
modes is shown in Table 3.

The MC~
which contains

Independent

addressable
counter
and a 16-bi$e~~~@sable
latch. The
counters are preset to the binary n~b~rs
stored in the latches. Counter initialization
res~+l~~kin Ne transfer of the latch

similar
Time Out will occur after (L+ I)*(M + 1) enabled
clock periods, where L and M, respectively,
refer to the LSB
and MSB bytes in the Counter Latches.

STATUS

the,,,l~~&~cor.~+
$! ~,~y$.
;% ,<.:
y>.<W,:+$
*11:
,<+i.\.*
.]:i, ..
,,.+,.
\ .,.
~t?<:?f{
,,~.~~,~

iNITIALl~TION

Each of the three

A logic zero at the RESET input

latches.
In this case, all latches

Flag (Bit 1)
Flag (Bit 2)

count

of 65,53510.

It is important

into

a selected

address,
the next
or stack
counter

also initializes the counter

will assume a maximum
to note

that

an Internal

f:...

,.:. ~l.l.,t(;f:j)
..:..l,

hi:.,\,,..--\\
...

~~~$P;Rx4
~cRp7
.:~,.
\?y>,.~
.,
,.t..~,:,:t.t
o 0
.:$ ! ~

. ,.:)\:>I~~\~.*..*.
1
,!!s
.... ...*.,
,,,
i....~
!,..,?.,
b.
,,,..,.L*.~..,,
o
!J:::
-:..1

~Rx5
r
0 Continuous

0 0
1 0
1 0
o 0 1
1 0 1
o 1 1
1

TABLE 3 PTM OPERATING MODE SELECTION

Operating

Frequency

Comparison

Continuous

Operating

Pulse Width

Mode:

Interrupt

to Latches or Reset Causes Counter

If Gate ~

is< Counter

Gate 1 or Reset Causes Counter

Mode:

Interrupt

Gate J or Write

Comparison

Single Shot Mode:

1 Pulse Width

Gate 1 or Write

Mode:

Comparison

Single Shot Mode:

Frequency

Mode:

Mode:

if Gate ~

Mode:

Initialization

Is< Counter

Time Out

to Latches or Reset Causes Counter

Interrupt

If Gate ~

Is> Counter

Gate I or Reset Causes Counter

Comparison

Interrupt

If Gate

Initialization

Time Out

Initialization

T!me Out

Initialization
~ is> Counter

Time Out

MOTOROLA
8

MC6840

DS9802R3

Reset ( Bit zero of Control

the counter latches.

Register

1 Set) has no effect

CLOCK

on

clock

INPUT

Input

programmed
COUNTER
Y

Counter

INITIALIZATION
Initialization

as the transfer

of data from

(R ESET=O or CR1O= 1) is recognized.

It can also occur
depending
on Timer Mode with a Write Timer Latches
command
or recognition
of a negative transition
of the Gate
input.
Counter
recycling
or re-initialization
occurs
when
a
negative

transition

has reached

transferred

of the clock

from

the Latches

is recognized

state.

within

and ~will

accept

IS

asynchronous

clock

line. The inputs

and

level signals

to

one system clock period plus the sum of the setup and hold
times for the clock inputs, The asynchronous
clock rate can
vary from dc to the limit Imposed by the Enable Clock Setup,
and Hold times.
The external clock inputs are clocked In by Enable pulses.
Three

Enable

periods

apply.

are used to synchronize

and process

the external clock. The fourth Enable pulse decrements

the
internal counter.
This does not affect the input frequency,,,$f
merely creates a delay between a clock input transitioK$&~~<,

prescaler

input

counter

transitions.

transition

9). If the synchronization

that the ~

following

E cycle.

The maximum
the

-8

accept

Input
signal
first
not

jitter

negative

ca~%$~
,gw${ansitions

transitiq~.<?~$ecbgnized

great

as the time

the input

one system

jitter,
cycle,

discusse,~~,~~~~ffiputs.
anq:$~ld
J,%:

tlrne

~~.the Gate input

,+~oc~

period

plus

**,. recognition
The

inputs

16-bit counter.
-8

TIMER
duce

MC6840
DS9802R3

(01,

output

Timer

The

output

output

modes,

other
modes,
+

System

the

internal

01, 02,

Continuous
definition

16-bit
mode

or Dual
will

mode

or
IS ac8-bit

produce

and a single

The Dual 8-bit mode will prothe continuous

One bit of each

the corresponding
low (VOL)
while

the first

Register

output.

If this bit

regardless

the output

enable

and

Control

of the

IS high the

cycle

following

Register.
and

Single-Shot

output

manual
during

All

Independent

outputs

for either

appear

Frequency

and

waveform

Modes

is defined

Timer

for a discussion

Signals

but the actual

Timer

response

Refer to the Programmable

CRX7=O)
~

times.

TTL loads and pro-

continuous

If it is cleared

Continuous

modes.

affect

waveform
Single

will remain

onlv ones for which

sheet.

hold

relate to Internal

is therefore

16-bit

mode.

go low during

Applications

and

cycle pulse in both

to the Control

The

either

is used to enable

will

or low

Timer

Output

in the

duty

mode.

write

setup

and the high

up to two

Single

pulse in the single-shot

timer

is recogniz-

(provided

directly

of ~

waveform

bv selecting
modes.

duce a variable

setup

02, 03)

modes.

operating

Input

are used

1, 2, and 3,

transition.

of driving

if the

Recog

which

selection,

OUTPUTS

complished

of

The operation

a defined

pulse

in this document

of all timers

prescaler

Single-Shot

Enable

sum

of the Input

Gate

the output

and

signals

to Timers

are met),

$~~~~:~~?$rences to G transition

is cleared,

~~

Here

AC

must be stable for at least one system

the

input

Either.

the

That IS, a Gate transition

requirements

single-shot

,k..i:~+
J%i:l?!:!?,,.+.s,::
,i~$:.$
.,y)i~
,i~,:i:>
FIGURE 9 INPUT JITTER
.$,*,,,
. ~\ *,!,
.::,
.,~,.,..
.%)
,:.
.,>?$,..t
Ipt

:w~~@under

functions

ed by,,th5~$~tTM on the fourth

tran-

recogni$~d
~~ next cycle, or vice versa. See Figure 9.

Enable~

are

lnternall~$.th~
-8 prescaler out..*.,\**,
in the same manng$~s th~previouslv
discussed

Th$~.$Y4mg inputs are clocked into the PTM bv

~~.~
.~:t.,
E (enab~~b~b%
in the same manner as the previously

(CRX7)
between

plus the svstem

during

is the

synchronization
with
setup and hold time

to be recognized
by eith.~~~eblt
time nearest
sition or the subseque~~%~~+dme.

is

respectively,
the

square-wave

signals be~&ti~*8i~
signal:$wlt~~ginal

mode

or cl~~$lga%~~g

signals.

result of the Input

Enable, permitting

is n~t~~~it

will not be pro,Ge~~&&ntil

the
~;t
~,:.e
.\\s:
:,
.<*,+?**.
t ~~
frequency
and +[~:~ak+~ duty cycles

asvnchronous~j~-~wrnpatlble

as triggers

operating

jitter

bef~en

($$~~~&te

in~uts

tions may require an additional

Enable puls~:J,&~?~Wognltion.
When observing
recurring events, a lack{~~, ~~o~hronization
will result in jitter
being observed+:f~
Jh&Youtput of the
PTM when
using
asynchronou:,,%/@$
and gate Input
- ..**,
System

a certain

Characteristics,

and 03 are capable

does not meet setup and hol~i~,~~!~~cifica-

of ji~er.$

E cycle,
is required

requirement

clock

that a clock

edge of Enable

time

input

low level which

types

all iriput

transition

prescaler

put is treated
clock

(tsYnc)

ripple
do not

are maintain-

process

the current

time

#3 is

(thd)

pulse widths

and the falling

possible

mode.

an asynchronous

and

during

External

prescaler

in order to guarantee

of synchronization

of the

are two

input

However,

the ~3 transition

Timer

(tsu) and hold times

recognize

is processed

amount

MODE)

case when
-8

contains

setup

will

internal
recognition
of that transition
by the PT1~~}@l~&
references
to C inputs in this document
relate t,~:lfi$$r~~l
recognition
of the input transition,
Note that a Q~&$~fi~~~ or

There

its optional

As long as minimum

ed, the
(~)

a special

are

pins Cl, C2,

Input

TTL voltage

ouputs

decrement
Timers 1, 2, and 3, respectively.
The high and low
levels of the external clocks must each be stable for at least

-,

thus,

Operating

output

(Cl, C2, and~)

counter;

for

the PTM has external

as well as a counter

INPUTS

the

data

LINES

are high-impedance,
TTL-compatible
lines
capable of driving two standard TTL loads.
CLOCK

after

In this case,

to the Counter.

lNPUT/OUTPUT

Each of the three timers

and gate Inputs

input

an all-zero

ASYNCHRONOUS

to utilize

The divide-by-8

is defined

the latches to the counter with subsequent

clearing of the individual Interrupt
Flag associated
with the counter.
Counter
Initialization
always
occurs
when
a reset
condition

counter

C= ( + 8 PRESCALER

represents

Fundamentals

of the output
at

the

Pulse

are the

in this data

outputs
Width

and

signals

in

(unless

comparison

is not predictable

in typical

applications.

MOTOROLA
9

TIMER

OPERATING

The MCWO
wide

variety

MODES

that

has been designed

of applications.

to operate

This

effectively

is accomplished

in a

by using

the timer

wave

the Timer

three bits of each control register (CRX3, CRX4, and CRX5)

to define different
operating
modes of the Timers. These

Control

modes

dition

are

divided

MEASUREMENT

into

WAVE

modes,

SYNTHESIS

and are outlined

TABLE 4 OPERATING
CRX3

CRX4

CRX5

o
o
1

o
1
.

Either

mode,

or

programmable
The WAVE

dutycycle

generation.

waves

The other wave svnthesis

is similar

In use

to

the

can

mode,

be
the

Continuous

a single pulse is generated,

with a

width.
modes

and Pulse Width

are used to measure

wave

include

Comparison

cyclic and singular

the Frequenmodes

pulse widths,

which
respec-

tively.
In addition

to the four timer

modes

The type

1), either

a square

will be generated

of output

is selected

at
via

recognition

1 or External

of a negative

Reset=O)
transition

con-

of the

bv clearing
IS

CR X4.
enabled

by an absence

of a TimeA~~eset

condition
and a logic zero at the Gate Input. 1~,%spk5-blt
mode, tke counter
WIII decrement
on the flr~$~~~~
cycle
during or after the counter Initlallzatlon
cvcl~~~~~%nues
to
decrement
on each clock signal so long as.$~~~@alns low and
no reset condition
exists. A Counter Ti.@e,~&&~$the first clock
after all counter
bits = O) results in~~~x~~l~dlvldual
Interrupt
set and relnitlallzatlon.~~

f~~ounter.

In the Dual 8-bit mode (C RX2A= tk~~fer

to the example n
Figure 10 and Tables 5 and 6~$%~$.MSB decrements
once for
everv full countdown
of t~$~~$~+
1. When the LSB = O, the
MSB is unchanged;
on~~~n$$xt clock pulse the LSB IS reset

IS the Continuous

variable

MEASUREMENT

cy Comparison

modes
for cvclic

OX,

Reset (CR1O=

or internal

Flag being

is useful

however,
preset

Measurement

ComDarlson

SelectIon

SYNTHESIS

mode,
mode,

Svntheslzer

Frequency Comparison
Pulse Width

in this mode.

Single-Shot
operating

Mode

Con?lnuous

(CR X7=

cvcle waveform

Bit 2.

Either a Timer

signal

Single-Shot

which

symmetrical

generated

Register

is enabled

duty

Gate input results in Counter

Initialization.
A Write Timer
latches command
can be selected as a Counter Initialization

In Table 4.

MODES

Timer Operating

Timer Function

One cf the WAVE

Operating

WAVE

Output,

The counter

Control Register

. Defines Add!tlonal

and

output

or a variable

in Table 4, the remain-

to the count
in l~~k.~s~
Latches,
and the MSB
IS
<t,~<&<,)*.+:

decremented
by 1 (oR%). *he output, If enabled, remains low
during and af~~j~itiaflzation
and WIII remain low until the
counter
M,$,Q~?$~~~~>eroes. The output will go high at the
beginning $f t$ fiext clock pulse. The output remains high
until b@$~$~k$&SB and MSB of the counter are all zeroes. At
*..+,
,,?!
thei~egmlng
of the next clock pulse the defined Time Out
(~@~~wIll occur and the output WIII go low. In the Dual 8-bit
~.~~d$~~he period of the output of the example in Figure 10
,thr,~:~w,~tild span 20 clock pulses as opposed to IW6 clock pulses

3&$~~~3ing
the normal 16-bit mode
@.$<,.

A special time-out
condition
exists for the dual 8-bit mode
,~~
and enabling
or interrupt
conditions,
,,,,:2
(CR X2= 1) if L=O. In this case, the counter WIII revert to a
,+*<
mode similar to the single 16-bit mode, except Time Out oc.)P\::*
WAVE SYNTHESIS
MODES
,. ~ ~~.,~
~*\+
,,>
curs after M + 1 clock pulses. The output,
if enabled, goes
CONTINUOUS
OPERATING
MODE (TABLE
5k/f#$~\he
low during the Counter Inltlallzatlon
cycle and reverses state
,&~:ye~ith
a
continuous
mode will synthesize
a continuous
at each Time Out. The counter
remains
cyclical
(Is reing control

period
timer

register

proportional
latches.

med to operate

bit is used to modify

to the

preset

Any of the timers

in a continuous

bits 3 and 5 of the corresponding

MOTOROLA

10

counter

number

initialization

im~$~~t~dtticular

in the PTM ~$$&program$, k. ?s.

mode ~~h~,~tr~
zeroes into
co~~~o~k$$ster.

Assuming

initialized

at each Time Out) and the Indlvldual

is set when Time Out

counters do not change,
fi the clock frequency.

Interrupt

Flag

occurs.
If M = L=O,
the Internal
but the output toggles at a rate of

MC6840
DS9802R3

TABLE

Mode

Bit 3

Bit 4

Control Reg.
Bit 5

Frequencv

Comparison

FREQUENCY

COMPARISON

Counter
Initiahzation

.j. ~+

TO)+

Counter Enable
Flip-Flop Set (CE)

T+ R
RI

Comparison

c! .T+F

Counter Enable
Flip-Flop Reset (CE)

~ .~.~.r

GI. W.R. I

GIW. R. I

GI. W.R. I

~1 .~+ R

Pulse Width

MODE
Interrupt

Flag

sat (1)

W+R+I

al

W+R+I

TO Before ~1

Before TO

W+ R+I+G

Et

W+ R+I+G

TO Before ~t

Before TO

PIN ASSIGNMENT

02

26

rz

25

a5
03

24
23

=7
RESET

-/

m9
RSO
RS1
RS2
R/~
vc~

MC6840
DS9802R3

22
21

20

10

19

11

18

1
DO

D1

D2
D3

D4

D5

D6
D7

12

17

13

16

CS1

14

15

CTO

MOTOROLA
13

The three differences

between
Timer Mode can be summarized
Shot

Single-Shot
as attributes

generation

and Continous
of the Single-

mode:

1, Output

is enabled

for only one pulse until it is reinitializ-

ed.
2. Counter

Enable

3. L= M =0
Aside

from

WAVE
TIME

IS independent

or N =0

these

disables

differences,

MEASUREMENT
INTERVAL

of Gate

output.
the two

modes

The Time Interval

Modes

A timers output is normally

ment mode, but it IS defined.

Initialization

Initialization

in Table

8, are satisfied.

The counter

IS also af-

not used in a Wave MeasureIf the output is enabled, [t will

to Counter Time ,Q,ut.Q~nce there is no Individual

Interrupt
Flag generated,,~~~]$$ ~,utomatlcally
starts a new Counter initialization
C@~~$$~e process will continue
with frequencv
comparis~o~$e~,~$

The counter
does operate in either Single 16-bit or Dual
8-bit modes as programmed
bv CRX2. Other features of the

the mo~,~s
changed,
or a cvcle
the ~~de~.mined
limit.
.4:.\,.;*.,,
h., ~,~.a

Frequency

Modes

Comparison

are outlined
Or

Petiod

in Table

7.

Measurement

(CRX3= 1, CRX4=O)
The Frequency
Comparison
Mode
with CR X5= 1 is straightforward.
If Time Out occurs prior to
the first negative transition
of the Gate input after a Count@r
Initialization
cvcle, an Individual
Interrupt
Flag is set. *Q,

dedicated

cRX3
Application

to the purpose.

Frequency

Frequency

Comparison

Interrupt

Comparison

Width

Comparison

Pulse

Width

Comparison

Setting

Time

Time

Generated

Counter

Time

Individual

if
Out
!f
Out

Generated

Counter

Interrupt
than

Time

Generated

Counter

Interrupt
than

for

Generated

Counter

Interrupt
than

Pulse

= 1
Condition

than

until

possible to directlv obtain the width of anv pulse causing an

interrupt.
Similar data for other Time Interval Modes and
conditions
can be obtained,
if two sections of the PTM are

If a
and

,.:$,

c q,%~,:; : 5*X5

cvcle

to be above

FIGURE 7 OUTPUT DELAY

,.,,
~,,/+.
+:::,
<.
?;/,,

is determined

ated when the reverse condition

is true.
As can be seen in Table 8, a positive transition
of the Gate
input disables the counter.
With CR X5= O, it IS therefore

continues
to decrement.
A bit is set ~~ht$~~ti%e timer on the
initial Time Out which precludes fw.tm~+$dividual
interrupt
*3),~.
::,,
,,,:
,,

on each Gate input

applied to the Gate input is less than the time period required
for Counter Time Out, With CR X5= 1, the interrupt is gener-

counter IS disabled, and a Counter Initialization

cvcle ~a~~o~
i?.$\\
@\,.,...?.,
begin u~il the interrupt
flag is cleared and a nega$j$e~dn5~,2,,,,,+,:,,...
+!.\.
tion on G is detected.
~$l~.y,,+:
:
~.l, ..,<.,,,
If CR X5= O, as shown in Tables 7 and 8,,@~{~,;,W~upt
IS

.J*, . ~ . s.
\y,.,,,
.~l)+
,,,.8
J
\~.>;.
,:*+
ii
.J:>!, [:0
!:
:k:\\
;~j
\3..x/~ ~s~ij,.\$
..
....,,
.s.,,.s%}::,:,?
.,>,,,\
t
qj>~,, ; i~,
<,:.-.,,.
~:<$.,F
>,,>,,
t..,
1

performed

&*~ls#Width
Comparison
Mode (CRX3= 1, CRX4= 1) +&,~$~&~rnode is similar to the FrequencV Comparison
Mode ex.t$:\\tfw>::
~.(..,.~ept for a positive,
rather than negative,
transition
of the
>? Gate input terminates
the count. With CRX5= O, an lndivldf} ~
ual Interrupt
Flag will be generated
if the zero level pulse

Mode

generated
if Gate input returns low prior tq$$wOut.
Counter Time Out occurs first, the coukh~fi$
r~cvcled

decreme$~s~%veach

generated
(f CRX5=0
and the pe~~d ,~f the pulse (single
pulse or measured separately
[d~etid-w pulses) at the Gate
input is less than the Count8{~~*,0ut
period. If CR X5= 1,
an interrupt
is generated J&~$&~verse
IS true.
Assume now with Ct$,%$=~$ that a Counter
Initialization
has occurred and tha$i~~fl~~te
input has returned low prior

of a Time-Out.

Measurement

has been

clock signal recognized

during or after Cou<~~##i\~~Mllzation
until an Interrupt
is generated,
a Write Tj*@~hes
command is Issued, or a Timer Reset condl$j~~o~;flrs.
It can be
seen from
Table 8 that an inte(.[*@~<~@fidltion
will be

operate as follows.
During the period between relnitialization
of the timer and the first Time Out, the output
will be a
logical zero. If the first Time Out is completed
(regardless of
Its method of generation),
the output will go high. If further
TOs occur, the output will change state at each completion

Wave

cycle

Gate Input enables the counter

and starts a Coq{]J~$,J,nitlallzatlon
cvcle provided that other condltlon~~+ a9~m8Ed

are

the FrequencV (period) Measurement

and Pulse Width Corrparison
Modes,
and are provided
for those applications
which
require more flexibility
of interrupt
generation
and
Counter
Initialization.
Individual
Interrupt
Flags are set In
these modes as a function
of both Counter Time Out and
transitions
of the Gate Input. Counter
fected bv Interrupt
Flag status.

a new Counter

compare
the period of a pulse (giving the frequencv
after
calculations)
at the Gate input with the time period
requested for Counter Time Out. A negative transition
~f the

are identical,

MODES

MODES

until

completed.
When this internal bit is set, a negative transition
of the Gate input starts a new Counter
Initialization
cvcle.
~TO
is satisfied,
since a T[me Out
(The condition
of ~1
has
occurred
and
no
individual
Interrupt
has
been
generated. )
AnV of the timers within the PTM may be programmed
to

if

Gate

Interrupt
Period

Flag
(l/F)

is

less

(TO)
Gate

Input

Period

(1 /F)

is

greater

(TO)
Gate

Out

(TO)

If

Gate

Out

(TO)

MOTOROLA
12
-

Input

- .

Input

Input

Down

Down

Time

Time

is

less

IS greater

MC6840
DS9802R3
.. . .. . .

FIGURE 10
(Continuous

TIMER OUTPUT WAVEFORM

Dual 8-Bit Mode

EXAMPLE

Using Internal

Enable)
Time

Example:

Contents

of

MSB

Contens

of

LSB

out

= 03 = M
= 04

L
I

~M(L+l)+l~L4

----

Algebraic
03(04+

=
II

16 Enables

I
I
Counter

Expression
1)+

2.4

1:
l\
II
~

1A

~m

Enable
(System

02)
II
_l+L~,+L~l

+L~

5 Enable
I

Pu Ises

~L

5 Enable

5 Enable

Pulses

Pulses

I
~

Ii
I

1[

II

II

I
I

II

I
I

T .

Il.,

1,
(M+l)(L+l)
id:

II
II

ki\\

\\
,,,>:!
$
>$,i ,<~~t
,,~
J
,:. ?.,.* $
,,,,:..
,5,
,,,L,X
,.i:
.*:..{:,
,,s~?p%k
&*$
.,:-
,,,,, iv
*.$&*J
, !,:.
4 Enable
..$,.\\.*
..!:,
.:
Pu Ises
$~,k
.::>.,,+

II

. *Q.
@kr.\:27,,
.b,;:t. .:6
~,~+s~.
~;, ?*,
<~:;*:>~~(~
~$~~$
$~:~..
0.4

Output

1 + LV,*J:,,:: i.
5 E q,~j:
~k$!

p u+!?~~
,*S
+$?
~ . .,,,f,?
~.~:: .?$>.
,.
:?$}>

,k..,&
A l& br$l& E xpression

(M

M(L

1)(L+

L = Pulse

1) = Period

+ 1) + 1 =

LOW

of

width

LSB

and

MSB

* *Preset

LSB

to LSB

to Respective
Latches

of the Continuous

and

Mode

Latches

Decrement

MSB

has assumed

bv one

TIMER

MODE

<$~$~~~1 Register
..@ r ;?*X2
CRX4
$,
Yi*, !.l:.,
>
i<
**.J:$~
~}.:
$<,*
<tfr:$
,.
0
0
:..i$>%
~t,-:.
kw+~s,
,%.
..~>::,
.,:,.-:.
,,\\\:
~%
.,.
0
1

Enable

or

The second

of the Enable

major difference
modes

between

is that the internal

Interrupt

the Single-Shot
counter

enable

and
is not

dependent
on the Gate input level remaining
In the low state
for the Single-Shot
mode.
Another special condition
is Introduced
in the Single-Shot
mode. If L= M=O (Dual 8-bit) or N=O (Single 16-bit), the

to

(CRX3 0,

transition

Continuous

output
goes low on the first clock received during or after
Counter
Initialization.
The output
remains
low until the
Operating
Mode is changed or nonzero data IS written
Into
the Counter

Latches.

of each clock
OPERATING

SINGLE-SHOT

Pulses

+U
*the counter
results in the setting of an Individual
Flag and re-initialization
of the counter.

the Continuous
Mode with three exceptioq~$~$$
first of
these is obvious from the name the o~~pu~it~turns
to a
low level after the initial Time Out a~~:r~w~ns
low until
another Counter Initialization
cyclec,$$~~s,$
As indicated
in Table 6, the inte$~a~~ountlng
mechanism
remains cvclical in the Single-$@@~;~@de.
Each Time Out of
.:..$.., ,*
.,
::::.:.,:,,
~
>J:,i.
,,,.
TABLE 6 SINGLE-SHOT
$1:
:,+.,~ ,*)
\
des
syb$h~;sm
Q~,\-~$>;,<>
..,, . $\ ~

Clock

the Enable

on th~~;~~,ti;$
..
k
~~h
:$s~$
, ,$y
,*,
,, .,\.,..,
.t,te
t$~,)?it
$,<;,}

that

This mode~st~%~%$al

+$&ternal

.$.*\$k
trans[f~o~!of

on the negattve

the application
requires an output signal. It should be noted.
*
,+.:
.{..
that the Timer operates in the same manner with the out~ti%$,,
disabled
(C RX7=O).
A Read Timer Counter
comman&~s
*:
~?$:
J?.S:J:>.
valid regardless of the state of CR X7.
.,,k.
,$.:J?
!,$.
,.. ,.,\i.+::i~\*\$:).\,
SINGLE-SHOT

+ 1) = 20

period
,+,

*Preset

The tilscussion

..$j~9f$?y\(03

portion

Time Outs continue

to occur

at the end

period.

MODES

MODE

CR X7=

I, CRX5=

1)

Initialization/Output
Counter Initialization

Waveforms
Timer Output (OX)

~L+W+R
~F_yN+lTlo
~$+R

6J +W+R

5$+R

~(L+(q::~L)(M+(T)~
lo

TO

TO

Symbols are as defined in Table 5.

MC6840
DS9802R3

MOTOROLA
11

PACWGE DIMENSIONS

NOTES:
1.

,8

h fin AA
,,,

nfitinfinfifi

L:

POSITIONAL
TOLERANCE
OF LEAOS (01,
SHALL
BE WITHIN 0.25rnrn(0.OID) AT
MAXIMUM MATERIAL
CONOITION, IN
RELATION
TO SEATING PLANE ANO
EACH OTHER.

,
2,

OIMENSION L TO CENTER
WHEN FORMEO PARALLEL.

3.

OIMENSION B DOES NOT

MOLO
FLASH.

P SUFFIX
PLASTIC

OF LEAOS

PACKAGE

CASE

71002

IN CLUOE

L-

cNi
,
4
,

--H

-G-

~ ---

---

SF*T,,Z
?,l,,[

NOTES
1. OIM ~
2. POSITIONAL

S SUFFIX

IS OAT,&~
T~j~~O+&&,AOS:

CERDIP
CASE

DIM A&#Q$>J,N5~UOES

OIM

PACKAGE
7S01

MENISCUS.

~k::YY&*ENTER

OF LEA05

6. OIM~&lONING
AN OTOLERANCING
,,~~ PER ~NSl Y14.5, 1973.
,3;:E:;

r:

rA

-)~jjF

-+y[f~k

~
~G~

::wD*t,>+
..,.>

~M

+:\
i,
,,
..! .$v$>>t.$?:
~y -.::::
,)$
~,::.
.,*.,!!.,.~
,.,,~.:..~<.
. . .,,.,,

?:i:,
~,,:t, ,$$.
.*:,*

,>,
.+

, ,i$: ,ij~
%;;* i,<,!l
~::~,,
,!t, \*t:
.<%:,i,,$
,,.i,.
.,?:*
J$!
.. ~.,,
~~
.
,>
.
$:s:,:, ,,$$
.1:$..
.{J:+\ .:;$.
,:.,:$ ~.{?::\\,
:,,
.~> ~
~>$t. .,,
,,\i.$,$$<
\.**...F?
~,$ii,
.,ii:~:!:it:<-,:,,
kb,
*{*,
t
..}
\\ k*i:.. ,
:,$,,;;,:..!,
hotorola
does

reserves

not

assume

the
any

right

to make

Iiabilitv

changes

arising

out

without

further

of the application

notice
or use

to any

of anv

products

product

herein

or circuit

to

improve

described

reliability,
herein;

neither

function
does

or design.
it convev

Motorola
any

license

nor the rights of others. Motorola products are not authorized for use as components in life suppofl devices or systems
intended for surgical implant into the body or intended to support or sustain life. Buver agrees to notify Motorola of anv such intended end use
whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and @ are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative
Action EmploVer.
under

Literature

its

patent

rights

Distribution

-.

Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands Milton KeVnes, MK145BP,
England.
ASIA PACIFIC: Motorola Semiconductors
H.K. Ltd.; PO. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong.

- o
M

MOrOROLA

.-,,,,5., ,.,.,,, 1,,.

MC6840
7-88

IWERW

.=0

C578Z4

5.WO

YCACM

DS9802R3