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4 GHz
RF Vector Modulator
AD8341
Data Sheet
FEATURES
VPRF
QBBP QBBM
VPS2
90
RFOP
RFIP
RFIM
RFOM
0
CMOP
IBBP IBBM
DSOP
04700-001
Figure 1.
APPLICATIONS
RF PA linearization/RF predistortion
Amplitude and phase modulation
Variable attenuators and phase shifters
CDMA2000, WCDMA, GSM/EDGE linear power amplifiers
Smart antennas
GENERAL DESCRIPTION
The AD8341 vector modulator performs arbitrary amplitude
and phase modulation of an RF signal. Since the RF signal path
is linear, the original modulation is preserved. This part can be
used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be
controlled from a maximum of 4.5 dB to less than 34.5 dB,
and the phase can be shifted continuously over the entire 360
range. For maximum gain, the AD8341 delivers an OP1dB of
8.5 dBm, an OIP3 of 17.5 dBm, and an output noise floor of
150.5 dBm/Hz, independent of phase. It operates over a
frequency range of 1.5 GHz to 2.4 GHz.
The baseband inputs in Cartesian I and Q format control the
amplitude and phase modulation imposed on the RF input
signal. Both I and Q inputs are dc-coupled with a 500 mV
differential full-scale range. The maximum modulation bandwidth is 230 MHz, which can be reduced by adding external
capacitors to limit the noise bandwidth on the control lines.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD8341
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Applications..................................................................................... 12
REVISION HISTORY
11/12Rev. 0 to Rev. A
Changes to Figure 2 and Table 3 ........................................................ 5
Replaced Figure 42 and Figure 43 ..................................................... 19
Updated Outline Dimensions ............................................................ 20
Changes to Ordering Guide ............................................................... 20
7/04Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
AD8341
SPECIFICATIONS
VS = 5 V, TA = 25C, ZO = 50 , f = 1.9 GHz, single-ended, ac-coupled source drive to RFIP through 1.2 nH series inductor, RFIM
ac-coupled through 1.2 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Maximum Gain
Minimum Gain
Gain Control Range
Phase Control Range
Gain Flatness
Group Delay Flatness
RF INPUT STAGE
Input Return Loss
CARTESIAN CONTROL INTERFACE (I AND Q)
Gain Scaling
Modulation Bandwidth
Second Harmonic Distortion
Third Harmonic Distortion
Step Response
Conditions
Min
Typ
Max
Unit
2.4
4.5
34.5
GHz
dB
dB
30
360
0.5
50
dB
Degrees
dB
ps
12
dB
2
230
41
47
45
1/V
MHz
dBc
dBc
ns
45
ns
0.5
7.5
dB
4.5
150.5
149
17.5
76
dB
dBm/Hz
dBm/Hz
dBm
dBm
8.5
dBm
1.5
Maximum gain setpoint for all phase setpoints
VBBI = VBBQ = 0 V differential
(at recommended common-mode level)
Relative to maximum gain
Over 30 dB control range
Over any 60 MHz bandwidth
Over any 60 MHz bandwidth
RFIM, RFIP (Pins 21 and 22)
From RFIP to CMRF (with 1.2 nH series inductors)
IBBP, IBBM, QBBP, QBBM (Pins 16, 15, 3, 4)
500 mV p-p, sinusoidal baseband input single-ended
500 mV p-p, 1 MHz, sinusoidal baseband input differential
500 mV p-p, 1 MHz, sinusoidal baseband input differential
For gain setpoint from 0.1 to 0.9
(VBBP = 0.5 V, VBBM = 0.55 V to 0.95 V)
For gain setpoint from 0.9 to 0.1
(VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V)
RFOP, RFOM (Pins 9, 10)
Measured through balun
Maximum gain setpoint
Maximum gain setpoint, no input
PIN = 0 dBm, frequency offset = 20 MHz
f1 = 1900 MHz, f2 = 1897.5 MHz, maximum gain setpoint
CDMA2000, single carrier, POUT = -4 dBm,
maximum gain, phase setpoint = 45 (See Figure 35)
Maximum gain
VPS2 (Pins 5, 6, and 14), VPRF (Pins 19 and 24),
RFOP, RFOM (Pins 9 and 10)
Includes load current
DSOP (Pin 13)
(See Figure 24)
DSOP = 5 V
Delay following high-to-low transition until
RF output amplitude is within 10% of final value.
Delay following low-to-high transition until
device produces full attenuation
Rev. A | Page 3 of 20
4.75
105
5
125
5.25
145
V
mA
Vs/2
33
30
V
dB
ns
15
ns
AD8341
Data Sheet
Rating
5.5 V
5.5 V
2.5 V
5.5V
13 dBm, re: 50
2.8 V p-p
825 mW
59 C/W
125C
40C to +85C
65C to +150C
300C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. A | Page 4 of 20
Data Sheet
AD8341
24 VPRF
23 CMRF
22 RFIP
21 RFIM
20 CMRF
19 VPRF
PIN 1
INDICATOR
AD8341
TOP VIEW
(Not to Scale)
18 IFLP
17 IFLM
16 IBBP
15 IBBM
14 VPS2
13 DSOP
04700-002
1
2
3
4
5
6
CMOP 7
CMOP 8
RFOP 9
RFOM 10
CMOP 11
CMOP 12
QFLP
QFLM
QBBP
QBBM
VPS2
VPS2
NOTES
1. THE EXPOSED PADDLE SHOULD BE SOLDERED TO
A LOW IMPEDANCE GROUND PLANE.
Mnemonic
QFLP, QFLM
3, 4
5, 6, 14, 19, 24
7, 8, 11, 12, 20, 23
9, 10
13
15, 16
17, 18
QBBP, QBBM
VPS2, VPRF
CMOP, CMRF
RFOP, RFOM
DSOP
IBBM, IBBP
IFLM, IFLP
21, 22
RFIM, RFIP
EP
Function
Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass
corner frequency.
Q Channel Differential Baseband Inputs.
Positive Supply Voltage. 4.75 V 5.25 V.
Device Common. Connect via lowest possible impedance to external circuit common.
Differential RF Outputs. Must be ac-coupled. Differential impedance 50 nominal.
Output Disable. Pull high to disable output stage.
I Channel Differential Baseband Inputs.
I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass
corner frequency.
Differential RF Inputs. Must be ac-coupled. Differential impedance 50 nominal.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. A | Page 5 of 20
AD8341
Data Sheet
PHASE SETPOINT = 0
0.5
15
PHASE SETPOINT = 180
20
PHASE SETPOINT = 90
25
30
04700-003
35
40
0
0.1
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
0
0.5
1.0
1.5
2.0
GAIN SETPOINT = 0.25
2.5
3.0
3.5
GAIN SETPOINT = 0.1
4.0
4.5
1.0
225
270
315
360
315
PHASE SETPOINT = 0
PHASE SETPOINT = 45
1
0
1
2
3
PHASE SETPOINT = 90
5
6
8
0
0.1
0.2
0.3
225
GAIN SETPOINT = 0.1
180
135
90
45
04700-004
180
360
7
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
0
0
1.0
45
90
135
180
225
270
PHASE SETPOINT (Degrees)
315
360
2
GAIN SETPOINT = 1.0
6
PHASE ERROR (Degrees)
8
GAIN SETPOINT = 0.5
12
14
GAIN SETPOINT = 0.25
16
18
20
22
26
28
0
45
90
135
180
225
270
315
5
10
04700-005
24
15
04700-008
10
GAIN (dB)
135
90
45
04700-007
GAIN (dB)
10
04700-006
15
0
360
45
90
135
180
225
270
PHASE SETPOINT (Degrees)
315
360
Rev. A | Page 6 of 20
Data Sheet
AD8341
147
0
1
148
40C
2
RF PIN = +5dBm
+25C
3
RF PIN = 0dBm
GAIN (dB)
150
151
04700-009
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
9
10
1500
1.0
GAIN (dB)
14
16
18
20
2200
2300
2400
10
12
4
6
1700
1600
Figure 9. Output Noise Floor vs. Gain Setpoint, Noise in dBm/Hz, No Carrier,
and With 1900 MHz Carrier (Measured at 20 MHz Offset)
Pin = 5, 0, and +5 dBm
2
04700-012
154
0.1
6
7
NO RF INPUT
153
+85C
RF PIN = 5dBm
152
22
04700-010
24
26
28
1500
1600
1700
1800
1900
2000
2100
2200
2300
10
20
30
40
50
60
70
80
THIRD BASEBAND HARMONIC PRODUCT,
1897MHz, 1903MHz
90
100
100
2400
200
300
400
500
600
700
800
900
04700-013
NOISE (dBm/Hz)
149
1000
FREQUENCY (MHz)
12
146
40C
147
10
+25C
OP1dB (dBm)
149
150
151
6
+85C
4
152
154
1500
1600
1700
2200
2300
0
1500
2400
04700-014
153
04700-011
NOISE (dBm/Hz)
148
1600
1700
2200
2300
2400
Rev. A | Page 7 of 20
AD8341
Data Sheet
20
25
15
20
+25C
OIP3 (dBm)
OIP3 (dBm)
10
15
+85C
10
0
GAIN SETPOINT = 0.1
5
1600
1700
2200
2300
04700-018
0
1500
04700-015
10
45
2400
90
180
135
315
360
10
1V p-p BB INPUT
RBW 30kHz
VBW 30kHz
SWT 100ms
REF LVL
0dBm
RF ATT
20dB
UNIT
dBm
A
15
30
60
110
160
210
260
FREQUENCY (MHz)
310
360
60
70
80
410
1SA
04700-019
35
10
50
40
UNDESIRED SIDEBAND
25
30
RF FEEDTHROUGH
20
20
DESIRED SIDEBAND
10
04700-016
270
225
90
100
CENTER 1.9GHz
500kHz/
SPAN 5MHz
FREQUENCY (MHz)
60
120
5
30
150
0
GAIN SETPOINT = 0.25
5
180
1500MHz
10
210
45
90
135
180
330
225
270
315
360
240
300
270
Rev. A | Page 8 of 20
04700-020
15
0
2400MHz
04700-017
OP1dB (dBm)
Data Sheet
AD8341
90
0
5
60
120
10
30
180
1500MHz
2400MHz
210
20
25
30
35
40
45
330
04700-024
150
15
50
55
0
240
300
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
270
SDD22 PORT DIFFERENTIAL
S22 WITH 1 TO 1 TRANSFORMER
20
3
PHASE SETPOINT = 0
VOLTS
30
40
RF OUTPUT
PHASE SETPOINT = 45
50
100mV/DIV
04700-022
60
PHASE SETPOINT = 90
70
0
0.1
0.2
0.3
04700-025
10
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
1.0
VPOS = 5.00V
125
VPOS = 5.25V
124
123
VPOS = 4.75V
122
121
40 30 20 10
04700-023
126
10 20 30 40
TEMPERATURE (C)
50
60
70
80
Rev. A | Page 9 of 20
1.84V
AD8341
Data Sheet
THEORY OF OPERATION
VBBI
I CHANNEL INPUT
LINEAR
ATTENUATOR
V-I
SINGLE-ENDED OR
DIFFERENTIAL
50 INPUT Z
GainSP =
SINGLE-ENDED OR
DIFFERENTIAL
50 OUTPUT
I-V
V-I
OUTPUT
DISABLE
LINEAR
ATTENUATOR
Q CHANNEL INPUT
VBBQ
0/90
04700-026
Vq
MAX GAIN
+0.5
A
|A|
0.5
+0.5
MIN GAIN
0.5
Vi
04700-027
RF QUADRATURE GENERATOR
The RF input is directly coupled differentially or single-ended
to the quadrature generator, which consists of a multistage RC
polyphase network tuned over the operating frequency range of
1.5 GHz to 2.4 GHz. The recycling nature of the polyphase network generates two replicas of the input signal, which are in
precise quadrature, i.e., 90, to each other. Since the passive
network is perfectly linear, the amplitude and phase information contained in the RF input is transmitted faithfully to
both channels. The quadrature outputs are then separately buffered to drive the respective attenuators. The characteristic impedance of the polyphase network is used to set the input impedance of the AD8341.
Rev. A | Page 10 of 20
Data Sheet
AD8341
OUTPUT AMPLIFIER
The output amplifier accepts the sum of the attenuator outputs
and delivers a differential output signal into the external load.
The output pins must be pulled up to an external supply,
preferably through RF chokes. When the 50 load is taken
differentially, an output P1dB and IP3 of 8.5 dBm and 17.5 dBm
is achieved, respectively, at 1.9 GHz. The output can be taken in
single-ended fashion, albeit at lower performance levels.
RF FREQUENCY RANGE
The frequency range on the RF input is limited by the internal
polyphase quadrature phase-splitter. The phase-splitter splits
the incoming RF input into two signals, 90 out of phase, as
previously described in the RF Quadrature Generator section.
This polyphase network has been designed to ensure robust
quadrature accuracy over standard fabrication process
parameter variations for the 1.5 GHz to 2.4 GHz specified RF
frequency range. Using the AD8341 as a single-sideband modulator and measuring the resulting sideband suppression is a
good gauge of how well the quadrature accuracy is maintained
over RF frequency. A typical plot of sideband suppression from
1.1 GHz to 2.7 GHz is shown in Figure 28. The level of sideband
suppression degradation outside the 1.5 GHz to 2.4 GHz specified range will be subject to manufacturing process variations.
20
25
30
35
40
45
0.7
04700-028
15
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
FREQUENCY (GHz)
Rev. A | Page 11 of 20
2.5
2.7
AD8341
Data Sheet
APPLICATIONS
loss of >10 dB over the operating frequency range. Different
matching inductors can improve matching over a narrower
frequency range. The single-ended and differential input
impedances are exactly the same.
100pF 1.2nH
RFIM
~1VDC
RC
PHASE
RF
04700-029
100pF 1.2nH
RFIP
50
The input impedance of the AD8341 is defined by the characteristics of the polyphase network. The capacitive component of
the network causes its impedance to roll-off with frequency
albeit at a rate slower than 6 dB/octave. By using matching
inductors on the order of 1.2 nH in series with each of the RF
inputs, RFIP and RFIM, a 50 match is achieved with a return
VP
C2
100pF
C1
0.1F
IBBM
VP
IBBP
C12
(SEE TEXT)
C6
100pF
VPS2
OUTPUT
DISABLE
DSOP
CMOP
CMRF
CMOP
RFIM
RFOM
C17
100pF
AD8341
RFOP
CMRF
CMOP
VPRF
C3
0.1F
C4
100pF
QFLP
VPS2
VP
RFIP
QBBM
L4
1.2nH
QBBP
C5
100pF
QFLM
RF
INPUT
L3
1.2nH
IFLP
VPRF
IBBM
VP
IBBP
C7
100pF
IFLM
C8
0.1F
L1
120nH
ETC1-1-13
RF
OUTPUT
C18
L2
100pF
120nH
CMOP
VPS2
C14
0.1F
VP
C10
0.1F
QBBP
QBBM
C9
100pF
Rev. A | Page 12 of 20
04700-030
C11
(SEE TEXT)
Data Sheet
AD8341
2.5
RL2 = SHORT
3.0
3.5
4.0
GAIN (dB)
4.5
5.0
RL2 = 50
5.5
6.0
6.5
VP
7.0
GM
100pF
1.0
1:1
100pF
RF
OUTPUT
04700-031
50
DIFFERENTIAL
1.2
1.4
1.6
1.8
2.0
2.2
2.4
FREQUENCY (GHz)
2.6
2.8
3.0
Figure 32. Gain of the AD8341 Using a Single-Ended Output with Different
Dummy Loads, RL2 , on the Unused Output
RFOP
RT
RL = 50
8.5
RFOM
ISIG
8.0
120nH
RT
04700-032
RL2 = OPEN
7.5
Rev. A | Page 13 of 20
Data Sheet
f3dB
45 kHz 10 nF
C FLT 0.5 pF
CDMA2000 APPLICATION
To test the compliance to the CDMA2000 base station standard,
a single-carrier CDMA2000 test model signal (forward pilot,
sync, paging, and six traffic as per 3GPP2 C.S0010-B, Table
6.5.2.1) was applied to the AD8341 at 1960 MHz. A cavity tuned
filter was used to reduce noise from the signal source being
applied to the device. The 6.8 MHz pass band of this filter is
apparent in the subsequent spectral plots.
Figure 35 shows a plot of the spectrum of the output signal
under nominal conditions. POUT is equal to 4 dBm and VBBI =
VBBQ = 0.353 V, i.e., VIBBP VIBBM = VQBBP VQBBM = 0.353 V.
Noise and distortion is measured in a 1 MHz bandwidth at
2.25 MHz carrier offset (30 kHz measurement bandwidth).
R2
2 I MAX R1 || R2 R3 1
R2
R3
AD9777
AD8341
IBBP
IOUTA1
R1
R2
OPTIONAL
LOW-PASS
FILTER
R3
IOUTB1
IBBM
IOUTA2
QBBP
R1
R2
OPTIONAL
LOW-PASS
FILTER
R3
IOUTB2
1.15
1.13
1.10
1.08
1.05
1.02
1.00
0.97
0.95
0.92
0.90
0.88
0.85
0.82
0.80
0.77
0.75
0.72
0.70
50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
()
04700-034
AD8341
04700-033
QBBM
Data Sheet
AD8341
RBW 30kHz
VBW 100kHz
SWT 500ms
1 [T1]
CH PWR
ACP UP
ACP LOW
30
60
65
10
70
15
75
20
80
25
85
UNIT dBm
18.47dBm
1.95999900GHz
4.06dBm
77.64dBm
76.66dBm
40
1AVG
1RM
50
60
70
80
C0
C0
90
C11
CU1
112
CU1
04700-035
100
CENTER 1.96Hz
1MHz/
30
0.2
0.3
0.4
IQ CONTROL VOLTAGE
72
74
76
78
80
Figure 37 shows that for a fixed input power, the ACP (measured in
dBm) tracks the output power as the gain is changed.
WCDMA APPLICATION
Figure 38 shows a plot of the output spectrum of the AD8341
transmitting a single-carrier WCDMA signal (Test Model 1-64
at 2140 MHz). The carrier power is approximately 9 dBm. The
differential I and Q control voltages are both equal to 0.353 V,
that is, the vector is sitting on the unit circle at 45. At this power level, an adjacent channel power ratio of 61 dBc is achieved.
The alternate channel power ratio of 72 dBc is dominated by
the noise floor of the AD8341.
REF LVL
MARKER 1 [T1 ]
28.39dBm
24dBm
2.14050000GHz
24
OFFSET 1dB
82
84
RBW 30kHz
VBW 300kHz
SWT 1s
1
86
16
14 12 10
8
6
OUTPUT POWER (dBm)
UNIT dBm
28.39dBm
2.14050000GHz
CH PWR
8.95dBm
ACP UP
60.78dB
ACP LOW
60.82dB
ALT1 UP
72.67dB
ALT1 LOW
72.66dB
40
88
RF ATT 0dB
1 [T1]
30
18
0.5
Figure 37. Output Power and ACP vs. I and Q Control Voltages,
CDMA2000 Test Model, VBBI = VBBQ, ACP Measured at
2.25 MHz Carrier Offset in 1 MHz BW
04700-036
0.1
SPAN 10MHz
90
20
90
0
50
1RM
60
70
80
90
C0
With a fixed input power of 2.4 dBm, the output power was
again swept by exercising the I and Q inputs. VBBI and VBBQ were
kept equal and were swept from 100 mV to 500 mV. The resulting output power and ACP are shown in Figure 37.
100
C12
C12
C0
CU2
C11
110
CU1
C11
120
124
04700-038
C11
0.3dB OFFSET
20
RF ATT 0dB
04700-037
12
12dBm
MARKER 1 [T1 ]
18.47dBm
1.95999900GHz
REF LVL
CU1
CENTER 2.14GHz
2.5MHz/
SPAN 25MHz
Figure 39 shows how ACPR and noise vary with varying input
power (differential I and Q control voltages are held at 0.353 V).
At high power levels, both adjacent and alternate channel power
ratios increase sharply. As output power drops, adjacent and
alternate channel power ratios both reach minimums before the
measurement becomes dominated by the noise floor of the
AD8341. At this point, adjacent and alternate channel power
ratios become approximately equal.
Rev. A | Page 15 of 20
AD8341
Data Sheet
40
60
45
65
ACPR 10MHz OFFSET
50
70
55
75
60
80
65
85
70
90
95
75
NOISE 50MHz OFFSET
80
30
100
25
20
15
10
5
OUTPUT POWER (dBm)
10
50
15
60
25
65
70
30
ACPR 10MHz OFFSET
35
75
40
80
45
50
Figure 40 shows how output power, ACPR, and noise vary with
the differential I and Q control voltages. VBBI and VBBQ are tied
together and are varied from 0.5 V to 50 mV.
55
20
85
90
0
0.1
0.2
0.3
0.4
IQ CONTROL VOLTAGE
04700-040
55
ACPR 5MHz OFFSET
45
ACPR (dBc)
NOISE dBm @ 50MHz OFFSET (1MHz BW)
35
40
OUTPUT POWER dBm
50
0
5
04700-039
30
0.5
Figure 40. AD8341 Output Power, ACPR and Noise vs. VIQ.
Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz)
Rev. A | Page 16 of 20
Data Sheet
AD8341
EVALUATION BOARD
The evaluation board circuit schematic for the AD8341 is
shown in Figure 41.
The evaluation board is configured to be driven from a
single-ended 50 source. Although the input of the AD8341 is
differential, it may be driven single-ended, with no loss of performance.
The low-pass corner frequency of the baseband I and Q channels can be reduced by installing capacitors in the C11 and C12
positions. The low-pass corner frequency for either channel is
approximated by
f3dB
45 kHz 10 nF
C FLT + 0.5 pF
The baseband input of the AD8341 requires a differential voltage drive. The evaluation board is set up to allow such a drive
by connecting the differential voltage source to QBBP and
QBBM. The common-mode voltage should be maintained at
approximately 0.5 V. For this configuration, Jumpers W1
through W4 should be removed.
The baseband input of the evaluation board may also be driven
with a single-ended voltage. In this case, a bias level is provided
to the unused input from Potentiometer R10 by installing either
W1 or W2.
Setting SW1 in Position B disables the AD8341 output amplifier. With SW1 set to Position A, the output amplifier is enabled.
With SW1 set to Position A, an external voltage signal, such as a
pulse, can be applied to the DSOP SMA connector to exercise
the output amplifier enable/disable function.
Function
I Channel Baseband Interface. Resistors R7 and R9 may be installed to accommodate a
baseband source that requires a specific terminating impedance. Capacitors C15 and C19
are bypass capacitors.
For single-ended baseband drive, the Potentiometer R11 can be used to provide a bias level
to the unused input (install either W3 or W4).
C11, C12
Baseband Low-Pass Filtering. By adding Capacitor C11 between QFLP and QFLM, and C12
between IFLP and IFLM, the 3 dB low-pass corner frequency of the baseband interface can
be reduced from 230 MHz (nominal). See equation in text.
Output Interface. The 1:1 balun transformer, T1, converts the 50 differential output to 50
single-ended. C17 and C18 are dc blocks. L1 and L2 provide dc bias for the output.
Input Interface. The input impedance of the AD8341 requires 1.2 nH inductors in series
with RFIP and RFIM for optimum return loss when driven by a single-ended 50 line. C5
and C6 are dc blocks.
Rev. A | Page 17 of 20
Default Conditions
R7, R9 = Not Installed
R11 = Potentiometer, 2 k,
10 Turn (Bourns)
R14 = 4 k (Size 0603)
R15 = 44 k (Size 0603)
R19, R20, R21 = 0
(Size 0603)
C15, C19 = 0.1 F
(Size 0603)
W3 = Jumper (Installed)
W4 = Jumper (Open)
R1, R3 = Not Installed
R10 = Potentiometer, 2 k,
10 Turn (Bourns)
R12 = 4 k (Size 0603)
R13 = 44 k (Size 0603)
R16, R17, R18 = 0
(Size 0603)
C16, C20 = 0.1 F
(Size 0603)
W1 = Jumper (Installed)
W2 = Jumper (Open)
C11, C12 = Not Installed
AD8341
Data Sheet
Components
C2, C4, C7,
C9, C14, C1,
C3, C8, C10,
R2, R4, R5, R6
Function
Supply Decoupling.
R8, SW1
Output Disable Interface. The output stage of the AD8341 is disabled by applying a high
voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving
SW1 to Position A. The output disable function can also be exercised by applying an external high or low voltage to the DSOP SMA connector with SW1 in Position A.
IBBP
Default Conditions
C2, C4, C7, C9, C14 = 0.1 F
(Size 0603)
C1, C3, C8, C10 = 100 pF
(Size 0603)
R2, R4, R5, R6 = 0
(Size 0603)
R8 = 10 k (Size 0603)
SW1 = SPDT (Position A,
Output Enabled)
IBBM
C19
R7
0.1F (OPEN)
R9
(OPEN)
C2
0.1F
R20
0
C15
0.1F
R2
0
VS
R14
4k
GND
TEST POINT
R19
0
3
4
R21
0
VP
TEST POINT
R11
2k
R15
44k
C1
100pF
C12
(OPEN)
C6
100pF
VPS2
IBBM
IFLP
VPRF
IBBP
VS
C8
100pF
R5
0
IFLM
C7
0.1F
S1
CMOP
CMRF
L3
1.2nH
R8
10k
DSOP
CMOP
B
A
DSOP
C18
100pF
T1
ETC1-1-13
M/A-COM
RFOM
RFIN
AD8341
C3
100pF
QFLP
C17
L1
100pF
120nH
CMOP
C14
0.1F
VPS2
VP
C11
(OPEN)
C10
100pF
R12
4k
R10
2k
R6
0
C9
0.1F
R13
44k
VS
C16
0.1F
2
R17
0
R1
(OPEN)
1
R16
0
R18
0
R3
C20 (OPEN)
0.1F
QBBP
QBBM
Rev. A | Page 18 of 20
04700-041
R4
0
VPS2
VPRF
C4
0.1F
L2
120nH
CMOP
QBBM
CMRF
VP
RFOP
RFOP
RFIP
L4
1.2nH
QBBP
C5
100pF
QFLM
RFIN
AD8341
04700-042
04700-043
Data Sheet
Rev. A | Page 19 of 20
AD8341
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.60 MAX
2.50 REF
0.60 MAX
3.75 BSC
SQ
0.50
BSC
2.25
2.10 SQ
1.95
EXPOSED
PAD
13
TOP VIEW
1.00
0.85
0.80
12 MAX
0.80 MAX
0.65 TYP
0.30
0.23
0.18
SEATING
PLANE
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
12
BOTTOM VIEW
0.25 MIN
04-09-2012-A
PIN 1
INDICATOR
PIN 1
INDICATOR
24
19
18
ORDERING GUIDE
Model 1, 2
AD8341ACPZ-WP
AD8341ACPZ-REEL7
AD8341-EVALZ
1
2
Temperature Range
40C to +85C
40C to +85C
Package Description
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
WP = Waffle pack.
Z = RoHS Compliant Part.
Rev. A | Page 20 of 20
Package Option
CP-24-1
CP-24-1
Ordering Quantity
64
1,500
1