EE 461A: Verilog HDL and Logic Design

Homework #7
In this homework, you will create a 16-bit complex counter. The counter
should have the following features:
1. The counter can be asynchronously set by a clear signal.
2. Up count and down count based on a control pin (up down)
3. When it reaches zero during down count, it should reset it self to
1111111111111111 on the next clock edge.
4. When it reaches 111111111111111 during up count, it should
reset itself to zero on the next clock edge.
5. There is a special function such that when activated, the up
count or down count step size will be a 4-bit
increment/decrement if the control pin step control is true. In
case the increment or decrement causes over flow or under flow,
you should wrap the count at one count before such condition
occurs. For example, if your down count from 9 by step size 4,
the sequence should be 9, 5, 1, 216 .
6. Of course, you should be able to synchronously load the counter
with a 16-bit data. The load control pin is load
Please use the following module port names:
clk: clock port.
clr: asynchronous clear port.
data: 16-bit data for synchronous load.
load: load control port, load data if it is true.
step : 4-bit data for up or down count step. (if step = 0011, the up
count sequence from 0 would be (0, 3, 6, 9 )
step control: step size control port. If true, use step size specified by
the 4-bit step. Otherwise use step size of 1.
q: a 16-bit output port for the counter.

What to hand in:

1. Your Verilog HDL source code
2. Your test fixture with sufficient number of test vectors to
exercise all the different options.
3. The simulation output.
Source Code:
module counter(clk,rst,up,qout,load,data,step_data,step_control);
input clk,up,rst,step_data,step_control,load;

input [15:0] data;

output [15:0] qout;
reg [15:0] qout;
reg [3:0] step;
always @(posedge clk or posedge rst)begin
if(rst)
qout<=16'b0000;
else if (load==1)
qout<=data;
else begin
if (step_control==1)
step<=1;
else
step<=1;
if (up) begin
if(qout==16'b0111111111)
qout=16'b0000;
else
qout=qout+step;
end
else begin
if (qout==16'b0000)
qout=16'b111111111;
else
qout=qout-step;
end
end
end
endmodule
//Test fixture.
module counter_tb;
reg clk,up,rst,step_control,load;
wire [15:0] qout;
reg [15:0] data;
reg [3:0] step_data;
counter counter_tb(clk,rst,up,qout,load,data,step_data,step_control);
initial begin
$monitor($time,"clk=%b,rst=%b,up=%b,qout=%b,load=%b,data=
%b,step_data=%b,step_control=%
b",clk,rst,up,qout,load,data,step_data,step_control);
end
initial begin
#10
clk=1;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b1
001;step_control=1;

#10
clk=0;rst=1;up=1;load=1;data=16'b101010101010101010;step_data=4'b1
101;step_control=1;
#10
clk=1;rst=0;up=0;load=0;data=16'b101010101010101010;step_data=4'b1
111;step_control=1;
#10
clk=0;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b0
001;step_control=0;
#10
clk=1;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b0
011;step_control=1;
#10
clk=0;rst=0;up=1;load=1;data=16'b101010101010101010;step_data=4'b1
111;step_control=1;
#10
clk=1;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b1
001;step_control=0;
#10
clk=0;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b0
110;step_control=1;
#10
clk=1;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b1
101;step_control=0;
#10
clk=0;rst=0;up=1;load=0;data=16'b101010101010101010;step_data=4'b1
001;step_control=1;
end
endmodule
Simulation Output:

EE 461A: Verilog HDL and Logic Design

Homework #8
In this homework, you are given an incompletely specified hierarchical
Verilog model with missing modules. Your task is to fill in the missing
modules and create a test fixture to test the completed Verilog model.
module hierarchical (data, load, clear, clock, sum, gt, eq, lt);
input [15:0] data; // 16 bit load for the 16 bit counter.
input load ;
// load the 16-bit data when true.
input clear;
// asynchronous clear for the 16 bit counter
input clock;
// the clock for the 16 bit counter
output [15:0] sum; // the sum of the first 8 bits and second 8-bits of the
counter.
output eq;
// true if the first 8 bits is equal to the second 8-bits.
output gt;
// true if the first 8 bits of the counter is greater than the
second 8 bits
output lt;
// true if the first 8 bits of the counter is less than the
second 8 bits.
wire [15:0] w16;
counter b1 (.data(data), .load(load), .clock(clock), .clear(clear), .q(w16));
// this is a 16 bit up counter with load, and asynchronous clear
adder b2 (.a(w[15:8]), .b(w[7:0]), .sum(sum));
compare b3 (.a(w[15:8]), .b(w[7:0]), .lt(lt), .eq(eq), .gt(gt));
endmodule
What to hand in:
1. A completed hierarchical Verilog HDL model.
2. A test fixture with sufficient number of input vectors to show
that all the features are working.
3. Simulation output of the design.
Source Code:
module hierarchical(data, load, clear, clock, sum, gt, eq, lt);
input [15:0] data; // 16 bit load for the 16 bit counter.
input load ;
// load the 16-bit data when true.
input clear;
// asynchronous clear for the 16 bit counter
input clock;
// the clock for the 16 bit counter
output [15:0] sum; // the sum of the first 8 bits and second 8-bits of the
counter.
output eq;
// true if the first 8 bits is equal to the second 8-bits.
output gt;
// true if the first 8 bits of the counter is greater than the
second 8 bits

output lt;
// true if the first 8 bits of the counter is less than the
second 8 bits.
wire [15:0] w16;
counter b1 (.data(data), .load(load), .clock(clock), .clear(clear), .q(w16));
// this is a 16 bit up counter with load, and asynchronous clear
adder b2 (.a(w[15:8]), .b(w[7:0]), .sum(sum));
compare b3 (.a(w[15:8]), .b(w[7:0]), .lt(lt), .eq(eq), .gt(gt));
endmodule
module hierarchical_tb;
reg [15:0] data; //16 bit load for the 16 bit counter.
reg load; //load the 16 bit data when true.
reg clear; //asynchronous clear for the 16 bit counter.
reg clock; // the clock for the 16 bit counter.
wire [15:0] sum; //the sum of the 8 bits and second 8-bits of the counter.
wire eq; //true if the first 8 bits is equal to the second 8-bits.
wire gt; //true if the first 8 bits of the counter is greater than the second 8bits.
wire lt; //true if the first 8 bits of the counter is less than the second 8-bits.
wire [15:0] w16;
hierarchical hierarchical_tb(data,load,clear,clock,sum,gt,eq,lt);
initial begin
$monitor($time,"data=%b,load=%b,clear=%b,clock=%b,sum=%b,gt=
%b,eq=%b,lt=%b",data,load,clear,clock,sum,gt,eq,lt);
end
initial begin
#5 clock=0;data=16'b0001;clear=1;load=0;
#5 clock=1;data=16'b0000;clear=1;load=0;
#5 clock=0;data=16'b0001;clear=0;load=0;
#5 clock=1;data=16'b0001;clear=0;load=1;
#5 clock=0;data=16'b0001;clear=0;load=0;
#5 clock=1;data=16'b0001;clear=1;load=0;
#5 clock=0;data=16'b0001;clear=0;load=0;
#5 clock=1;data=16'b0001;clear=0;load=1;
#5 clock=0;data=16'b0001;clear=0;load=0;
#5 clock=1;data=16'b0001;clear=0;load=0;
end
endmodule
Simulation Output: