MCS-012 Soved Assignment 2015-16 PDF

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Evaluate 2s complement of 8 bits including sign bit.
i) Add 128 and 120 IGNOU MCA Assignment
2015 16
MASTER OF COMPUTER APPLICATIONS
Course Code : MCS-012
Course Title : Computer Organisation and Assembly Language Programming
Assignment Number : MCA(I)/012/Assignment/15-16
Maximum Marks : 100
Weightage : 25%
Perform the following arithmetic operations using binary signed 2s complement notation
for integers.
You may assume that the maximum size of integers is of 8 bits including the sign bit. (Please
note that the numbers given here are in decimal notation)
i) Add 128 and 120
ii) Subtract 124 from 99
iii) Add 64 and 61
Please indicate the overflow if it is occurs. Also write how you have identified the overflow.
i) Add 128 and 120
First, we have to represent the number in binary notation
The sign of a binary number is represented by 0 as plus and 1 as minus
Sign bit
7 -bits
0/1
Now, Binary value of the given number

128 10000000
120 01111000
This number value is of more than 8-bits (i.e.8-bits) in signed 2s complement notation also the
value remains the same. Hence this number cannot fit inside it.
To add this numbers we will need one more bit, hence Addition not possible.
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Page 1
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ii) Subtract 124 from 99 IGNOU MCA
Assignment 2015 16
By GangadharKopella | September 1, 2015
0 Comment
Maximum Marks : 100
Weightage : 25%
for integers.
i) Add 128 and 120
iii) Add 64 and 61
Sign bit
7 -bits
0/1

99 1100011
124 1111100
-99 :Sign bit
NA
+124 :Sign bit
7 -bits
1
7 -bits
Page 2
NA
In Binary, Subtraction is not done directly it is done by taking a MINUS sign for a positive
number.
For subtraction changing +224 to -224:-124 :Sign bit
NA
7 -bits
1
Now, covert it to signed 2s complement notation:-99 :Sign bit

NA
7 -bits
1
-124 :Sign bit

NA
7 -bits
1
Simple trick to convert any binary value to its signed 2s complement notation is Check for the
first one (i.e. 1) in the magnitude of the number from Right to Left when you find it, Keep the
number unchanged till one (i.e. 1) and remaining number reverse it by changing value from 0 to 1
and vice-verse.
-99 :Sign bit
7 -bits
NA
-124 :NA
-223 :Carry bit

NA
Overflow condition occured.
Page 3
The magnitude has been overflowed into carry the given 8-bits are not sufficient for the result of
the magnitude.

iii) Add 64 and 61- IGNOU MCA Assignment 2015
16
0 Comment
Maximum Marks : 100
Weightage : 25%
for integers.
i) Add 128 and 120
iii) Add 64 and 61
iii) Add 64 and 61
Sign bit
7 -bits
0/1

+64 1000000
+61 0111101
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Page 4
Sign bit
NA
7 -bits
0
+61:Sign bit
NA
7 -bits
0
Sign bit
+64:NA
7 -bits
0
+61:NA
+256 :Carry bit

NA
Overflow condition occurred.

The magnitude has been overflowed into sign bit and sign into carry the given 8-bits are not
sufficient for the result of the magnitude.
ANS 2
Maximum Marks : 100
Weightage : 25%
(b)Convert the hexadecimal number: (ABCD01)16 into equivalent binary, octal and
decimal.
The Base Value of Hexadecimal number is 16. The Table represents the value in decimal.
0
Page 5
1
10
11
12
13
14
15
Any Hexadecimal number can be represented in the following format for converting to Decimal.
FAEBDC
F*165 + A*164 + E*163 + B*162 + D*161 + C*160
=15*165 + 10*164 + 14*163 + 11*162 + 13*161 + 12*160
=15*1048576 + 10*65536 + 14*4096 + 11*256 + 13*16 + 12*1
=15728640 + 655360 + 57344 + 2816 + 208 + 12
Page 6
=16444380
Decimal-to-Binary:
Converting can be found on this link http://www.wikihow.com/Convert-from-Decimal-to-Binary
Decimal-to-Octal:
Converting can be found on this link http://www.wikihow.com/Convert-from-Decimal-to-Octal
(c)Convert string into UTF 16 code You may

assume that Hindi swar starts with . IGNOU
MCA Assignment 2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
Convert the following string into equivalent UTF 16 code You may assume that Hindi
swar starts with Are these UTF 16 codes similar as that used in ASCII?
UTF 16
Stands for U Universal Character Set
T Transformation
F Format
16 16-bits (216 =512 characters)
ASCII CODE table:-
Page 7
And Extended list is from 256 511.

Table not found
To Convert:
You may assume that Hindi swar starts with
UTF 16 Codes:
Y=087 o=079 u=085 (space) =032 m=109 a=097 y=121 (space) =032 (space) =032 t=116
h=104 a=097 t=116 (space) =032 H=072 i=105 n=110 d=100 i=105 (space) =032 s=115 w=119
a=097 r=114 (space) =032 s=115 t=116 a=097 r=114 t=116 s=115 (space) =032 w=119 i=105
t=116 h=104 (space) =032(hindiswar)= < 255 (will be in the Extended list between 256
511)
(d)Use a Karnaughs map to design if the output bit

is 0 if the first and fourth input are same else it is 1
for 4 input bits IGNOU MCA Assignment 2015
16
By GangadharKopella | August 31, 2015
0 Comment
Page 8
Maximum Marks : 100
Weightage : 25%
Use a Karnaughs map to design a circuit that takes four input bits and produces one
output bit. The output bit is 0 if the first and fourth input are same else it is 1.
Before Designing we should know inputs which is 4

That means 24 = 16 Combinations of outputs
Inputs are represented as ABCD
Output is represented by F and some times termed as Function
Decimal
10
11
12
F (Function)
Page 9
13
14
15
Before proceeding we should know what odd parity is for ABCD inputs?
There are two types of parity even parity and odd parity
The parity is 0 or 1 depending upon total numbers of 1s
If count of 1s is even number then even parity = 0 and odd parity = 1
Similarly If count of 1s is odd number then even parity = 1 and odd parity = 0
After Finding out odd parity for ABCD inputs
We have Table as:-
Decimal
F (Function)
10
11
12
13
14
15
Its can also be written as F = (1, 3, 5, 7, 8, 10, 12, 14)

Only the decimal number where we find 1s is shown in the Bracket.
Page 10
Final Equation:-
(e)An 8 bit data 01101101 after transmission is

received as 01001101. Explain how SEC code will
detect and correct IGNOU MCA Assignment 2015
16
0 Comment
Page 11
Maximum Marks : 100
Weightage : 25%
An 8 bit data 01101101 after transmission is received as 01001101. Explain how SEC code
will detect and correct this problem.
SEC means Single Error Correction

This if found in Hamming Error Correction Code
First find out the number parity bits in SEC Code
Formula:
2i 1 >= N + i
where
i = number of parity bits in SEC Code
N = number of bits in Data Word
In this case
N=8
i=?
So,
2i 1 >= N + I
at i=3
23 1 >= 8 + 3
7 >= 11 (Not True)
So,
2i 1 >= N + I
at i=4
24 1 >= 8 + 4
15 >= 12 (True)
Condition Satisfied.
Page 12
Coorection bits (parity bits) are 4.
Parity bits are placed at 20 21 22 23
i.e. 1 2 4 8
respectively
P1
P2
D1
P3
D2
D3
D4
P4
D5
D6
D7
D8
10
11
12
D1 D2 D3 D4 D5 D6 D7 D8 are the data sent and recd.
Before sending calculate Parity of Data to be sent.
P1
P2
D1
P3
D2
D3
D4
P4
D5
D6
D7
D8
10
11
12
P1
(Positions) 1
0
3
1
5
0
7
1
9
0
11
Starting Point will be after Parity position P1 i.e 2 and Take 1 Skip 1 till the end of table data.
We get 01010
Its even parity will be 0
P2
(Positions) 2
0
3
1
6
0
7
1
10
0
11
Page 13
We get 01010
P3
(Positions) 4
12
We get 1101
P3
(Positions) 8
10
11
12
(Note:- data ends before taking 8 elements.)
We get 1101
We found all parity bits, we will fill in the table:-
P1
P2
D1
P3
D2
D3
D4
P4
D5
D6
D7
D8
10
11
12
Assuming all parity sent correctly
Page 14
The 8-bit Sent Data = 0110 1101
The 8-bit Sent Data = 0100 1101
Check with parity bits, before that Create a new parity bit with new data
P1=
P2=
P3=
P4=
D1
D1
D2
D5
D2
D3
D3
D6
D4
D4
D4
D7
D5
D6
D8
D8
D7 = 01010
D7= 00010
= 1001
= 1101
even parity will be 0

correct
- incorrect
- incorrect
correct
After Checking
We find that common data bit numbers are D3 & D4
But D4 is also present in P1that means error has been occurred in D3 only.
By this we dectect error in D3 and Correct it by replacing it by 0 to 1.
(f)Design a two bit counter (a sequential circuit) that

counts from 00 to 10 only IGNOU MCA
Assignment 2015 16
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Maximum Marks : 100
Weightage : 25%
Design a two bit counter (a sequential circuit) that counts from 00 to 10 only. Thus, the
counter states are 00, 01, 10, 00, 01,. You should show the state table, state diagram, the
k-map for circuit design and logic diagram of the resultant design using D flip-flop or J-K
flip flop.
Solution :
A sequential circuit is specified by a time sequence of external inputs, external outputs and
internal flip-flop binary states. Thus firstly, a state table and state diagram is used to describe
behaviour of the circuit.
Page 15
Present State
Input
A
Next State
Flip-Flops Inputs
A
B
0
0
0
0
1
1
1
1
1
1
DB
0
0
DA
There are 2 flip-flop inputs for counter i.e. A, B. The next state of flip-flop is given in the table. DA
indicates the flip flop input corresponding to flip-flop-A. This counter requires 2-flip-flops.
From this the flip flop input equations are simplified using K-Maps as shown below.
K-Map for DA is:
Page 16
K-Map for DB is:
Page 17
Thus, the simplified input equations for Counter are:

DA = |ABX + A|B|X
DB = |A|BX + |AB|X + ABX
Page 18
The logic circuit can be made with 2 D flip flops, 2 OR gates & 4 AND gates.
(g)Represent (124.0625)10 using IEEE 754 single

and double precision representations IGNOU MCA
Assignment 2015 16
0 Comment
Assignment Number : MCA (2)/012/Assign /2015-16
Maximum Marks : 100
Weightage : 25%
Page 19
Explain the double precision floating point IEEE 754 representation. Represent the
number (124.0625)10 using IEEE 754 single precision and double precision
representations.
Single Precision
S stands for Sign (white color)

E stands for Exponent (yellow color)
N stands for Number (also called Mantissa or Significand) (green color)
0this Sign bit (1 bit)

1st to 8this Exponent bits (7 bits)
9thto 31this Exponent bits (24 bits)
Double Precision
S stands for Sign (white color)

E stands for Exponent (yellow color)
N stands for Number (also called Mantissa or Significand) (green color)
0this Sign bit (1 bit)

1st to 11this Exponent bits (10 bits)
12thto 63this Exponent bits (53 bits)
First of all to represent we have (63.125)10 using IEEE 754

Since number is a positive number
Sign bit is: 0
Page 20
0
Now lets work on Mantissa part

Convert 124 into binary form i.e 1111100
Remaining is fraction part 0.0625
Now we multiply fraction value with 2 till we get whole number 1 at the end.
We reach 1 so we stop
Write number from top to bottom
We get 0.0625 = 0001
Number (124.0625)10 = (1111100.0001)2
Convert Binary number to Exponent Form
1111100.0001 Will be 1.1111000001 * 26
Discard 1.
Take 1111000001 as Significand
Significand number = (1111000001)2
Significand bits are:
1
Fill the Significand in the beginning

Rest all fills it with 0s
We will have
Page 21
1
+6 is the Exponent
So we have to subtract it with 127
Exponent = 127+6=132
Exponent number (132)10 = (10000100)2
Discard overflow bit
Exponent bits are:
0
Note: we have to discard overflow bit since we have only 7 bits
For Double Precision Only Exponent

+6 is the Exponent
So we have to subtract it with 1023
Exponent = 1023+6=1029
Exponent number (1029)10 = (10000000101)2
Discard overflow bit
Exponent bits are:
0
Note: we have to discard overflow bit since we have only 11 bits

1
Significand will only have a change in terms of Zeros which are added at the end.
For single precision 23-10=13 Zeros
For double precision 53-10=43 Zeros
Page 22
BLOCK 2
A RAM HAS A CAPACITY OF 8192K HAVING THE
WORD SIZE OF 16 BITS AND SUPPORTS BYTE
ADDRESSES ONLY IGNOU MCA ASSIGNMENT
2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
A RAM has a capacity of 8192K having the word size of 16 bits and supports byte
addresses only IGNOU MCA Assignment 2015 16
Explanation of Concept:
Page 23
A 32 4 RAM means that RAM has 32 words,

5 address lines (25 = 32), and 4 bit data word size.
We can represent a RAM using 2AD,
Where
A-> Number of address lines
D -> Number of Data lines
The 32 4 RAM circuit where 5 32 bit decoder is used
The 4 bit data input come from input buffer
The 4-bit data output is stored in output buffer
A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses
only IGNOU MCA Assignment 2015 16
Page 24
A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses
only.
(i)
How many data input and output lines does this RAM need? Explain your answer.
Ans: Data input and Data output lines are equal and of word size, Hence Ram will need 16 Data
lines
(ii)
How many address lines will be needed for this RAM? Explain.
Ans: Convert 8192K to 2A (D/2) format supports byte addresses only

8192K/8
= (8192 * 1024) / 8
= (213 * 210) / 23
=223-3
= 13
2
A
13
We can represent a RAM using 2 (D/2) = 2 (16/2) RAM Hence Address lines are 13
Address lines.
DRAW A DIAGRAM ADDRESS MAPPING OF RAM &

CACHE IGNOU MCA ASSIGNMENT 2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
A computer has 1MB RAM and has word size of 16 bits. It has cache memory having 16
blocks with a block size of 32 bits. Explain how a main memory address will be mapped to
a cache address, if
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii) Two way set associative mapping scheme is used.
Page 25
Given:
Main memory Size = 1 MB (RAM)
Convert it to Words if word size is 16 bits
Main memory Size = 65536 Words
Main Memory word size = 16 bits
Cache Memory Size = 16 Blocks
Cache Memory Block size = 32 bits
1 Block of Cache = 2 Words of RAM
Assume Memory location address 520 is equivalent to Block address 260.

Total number of possible Blocks in Main Memory = 65536 /2 = 32768 blocks
Page 26
Associative Mapping:
The block can be anywhere in the cache.
Direct Mapping:
Size of Cache = 16 blocks
Location of Block 260 in Cache = 260 modulo 16 = 4
2 Way set associative mapping:
Number of blocks in a set = 2
Number of sets = Size of Cache in blocks / Number of blocks in a set
= 32768 / 2 = 16384
Block 260 will be located anywhere in (260 modulo 8) set, that is set 4.
Page 27
EXPLAIN THE TERM FAT IN THE CONTEXT OF DISK
OPERATING SYSTEM. WHAT WILL BE THE SIZE OF A
DISK AND ITS FAT? IGNOU MCA ASSIGNMENT
2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
Explain the term FAT in the context of disk operating system. What will be the size of a
disk and its FAT, if a disk has 64 tracks with each track having 16 sectors and size of
each sector is 512 byte? You may take the cluster size as 4 sectors.
Given:
Disk has 64 tracks
Track has 16 sectors
Sector is 512 byte (0.5 KB)
Cluster size as 4 sectors
Find:
Disk Size (or Disk Capacity)?
Its FAT (or FAT entries)?
Track Size (in KB) = No. of Sector x No. of Btyes
= 16 * 0.5 KB
= 8 KB
Cluster Size (in KB) = No. of Track x No. of Sector
= 64 * 8 KB
= 512 KB
Disk Size (in KB) = No. of Cluster x No. of Track
= 4 * 512 KB
= 2048 KB
=2MB
Page 28
Disk Size (or Disk Capacity) = 2 MB
Note: FAT contains vital information; two copies of FAT are stored on the disk, so that in case
one gets destroyed, the other can be used
Its FAT (or FAT entries) = Disk Size (or Disk Capacity) / Cluster Size
= (2 * 1024 * 1024) / (2 * 1024)
= (2 * 1024 * 1024) / (2 * 1024)
= 1024 No. of entries
Note: FAT contains vital information; two copies of FAT are stored on the disk, so that in case
one gets destroyed, the other can be used (Acutual entries = 1024 entries / 2 = 512 entries).
Block 3
ASSUME THAT A NEW MACHINE HAS BEEN
DEVELOPED. GIVE JUSTIFICATION OF THE
SELECTION OF EVERY ADDRESSING MODE?
IGNOU MCA ASSIGNMENT 2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
A hypothetical machine has 22 registers. Out of these 6 registers are used as segment
registers. Assume that the machine uses segment registers to find physical address in
the similar way as is done in 8086 processor. Remaining 16 registers are general purpose
registers. All the registers and memory word for the machine are of 16 bits. The machine
has 1 M Word RAM. An instruction of the machine is of 32 bits which includes opcode 5
bits, addressing mode specification 3 bits and remaining bits for specifying the operand
addresses.
Each instruction contains at most two operand addresses at most one memory operand
and remaining register operand(s). What would be the size of memory address, if direct
addressing is used? What would be the size of the direct register operand? The machine
is to be used for calculations involving arrays and floating point numbers. Design five
Page 29
different types of addressing modes for this machine. Give justification of the selection of
every addressing mode.
Total general purpose registers = 32
All Register equal size = 16 bits
Registers used as stack for subroutine calls = 16
Main memory = 1 M Word
Memory word size = 16 bits
Instructions size = one memory word = 16 bits
Opcode = 5 bits
Addressing mode = 3 bits
Remaining bits = operand addresses
Please note the following points:
The opcode size is 5 bits. So, in general it will have 25 = 16 operations.

There is three operand address machine.
There are two bits for addressing modes. Therefore, there are 23 = 6 different addressing
modes possible for this machine.
The last field (8 32 bits = 24 bits) here is the operands or the addresses of operands field.
Each instruction contains at most two operand addresses at most one memory operand and
remaining register operand(s). Hence one register operand has to be involved in all Addressing
modes, so we have to use first operand as Register for all modes and this will be common for
all.
Page 30
IMMEDIATE addressing mode:
ADD R 12 13
R = 12 + 13
In case of immediate operand the maximum size of the unsigned operand would be 210
DIRECT addressing mode:
ADD R A B
R=A+B
In case it is an address of operand in memory, then the maximum physical memory size
supported by this machine is 210 = 1 KB.
Page 31
REGISTER addressing mode:
ADD R1 R2 R3
R1 = R2 + R3
There are 64 general purpose registers. Therefore, there is 64 = 26 (6-bits for Register address)
REGISTER INDIRECT addressing mode:
ADD R1 R2 R3
ADD R1 (R2 ) (R3 )
ADD R A B
R1 = R2 + R3
R1 = (R2 ) + (R3 )
R=A+B
There are 64 general purpose registers. Therefore, there is 64 = 26(6-bits for Register address).
Page 32
WRITE AND EXPLAIN THE SEQUENCE OF MICROOPERATIONS THAT ARE REQUIRED TO FETCH AND
EXECUTE THIS INSTRUCTION? IGNOU MCA
ASSIGNMENT 2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
Assume that the machine as stated in part (a) has named 5 of its general purpose
registers based on their possible role in instruction execution as Program Counter (PC),
Accumulator (AC), Memory Address Register (MAR), Instruction Register (IR) , Data
Register (DR) and Flag registers (FR). To execute an instruction of the machine that has a
direct memory operand and a register operand, the memory operand is first brought into
the DR register and the register operand is transferred to AC register. The result of the
operation is stored in the AC register. One of the instructions of the machine is given
below:
ADD R1, X // this instruction adds the operand stored in
Register R1 and memory location X. The result is stored in the AC register.
Write and explain the sequence of micro-operations that are required to fetch and execute
this instruction. Make and state suitable assumptions, if any.
STORE memAddress // this instruction result in storage of the content of AC register into the
memory location specified by memAddress.
Write and explain the sequence of micro-operations that are required to fetch and execute
this instruction Make and state suitable assumptions, if any.
The instruction execution using the micro-operations requires:
Instruction fetch: fetching the instruction from the memory.

Instruction decode: decode the instruction.
Operand address calculation: find out the effective address of the operands.
Execution: execute the instruction.
Interrupt Acknowledge: perform an interrupt acknowledge cycle if an interrupt request is
pending.
Page 33
Instruction fetch:
Page 34
Transfer the address of PC to MAR. (Register Transfer)
MAR PC
MAR puts its contents on the address bus for main and issues a memory read signal. The
word so read is placed on the data bus where it is accepted by the Data register.The PC is
DR (MAR),
incremented by one memory word length to point to the next instruction in sequence.
PC PC +1
The instruction is transferred from data register to the Instruction register processing.
IR DR
Instruction Decode: The Control Unit determines the operation that is to be performed
and the addressing mode of the data.
Operand Address Calculation: (In case of direct addressing)

Transfer the address portion of instruction is the direct address
IR (Address) and DR (Address) contain the
so no further calculation needed.
Effective address.
Operand Address Calculation: (In case of indirect addressing)

Transfer the address bits of instruction to the MAR. This transfer can be
achieved using DR, as DR and IR at this point of time contain the same
value. (Register Transfer)
MAR DR (Address)
Perform a memory read operation as done in fetch cycle and the desired
address of the operand is obtained in the DR. (Memory Read)
DR (MAR)
Transfer the address part so obtained in DR as the address part of

instruction. (Register Transfer) Thus, the indirect address is now
converted to direct address or effective address.
IR (Address) DR (Address)
Execution:
Transfer the address portion of the instruction to the MAR.
(MemAddress transfer)
MAR MemAddress
Page 35
Store the AC register to Memory Address in MAR.
(MAR) AC
Interrupt Processing:
Transfer the contents of PC to DR
DR PC
Place the address of location, where the return address is to be saved,
MAR Address of location for saving
into MAR.
return address.
Store the contents of PC in the memory using DR and MAR. (Memory

write) Transfer the address of the first instruction of interrupt servicing
(MAR) DRPC address of the first
routine to the PC.
instruction interrupt service programs
WHAT WILL BE THE VALUES OF SELECT INPUTS,

CARRY-IN INPUT AND RESULT OF OPERATION IF
THE FOLLOWING MICRO-OPERATIONS ARE
PERFORMED? IGNOU MCA ASSIGNMENT 2015
16
0 Comment
Maximum Marks : 100
Weightage : 25%
Assume that you have a machine as shown in section 3.2.2 of Block 3 having the microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are
8 bit registers and contains 1010 0011 and 1100 1011 respectively. What will be the values
of select inputs, carry-in input and result of operation (including carry out bit) if the
following micro-operations are performed? (For each micro-operation you may assume
the initial value of R1 and R2 as given above).
(i) Subtraction of R1 and R2
(ii) AND of R1 and R2
Page 36
(iii) Shift right R2 twice
(iv) Add of R1 and R2 with carry
(i) Subtraction of R1 and R2
S3
S2
S1
S0
Ci
F=x+( |y+1)
Micro-operation
Name
Subtraction
R R1 R2
R2=
0
|R2=
Page 37
S3
S2
S1
S0
Ci
Micro-operation
F=x+( |y+1)
Name
Value of Result R
Subtraction
1101 1000
R R1 R2
No Carry Out Occurred.
(ii) AND of R1 and R2

S3
S2
S1
S0
Ci
F=x.y
Micro-operation
Name
AND
R R1 ^ R2
Page 38
S3
S2
S1
S0
Ci
F=x.y
Micro-operation
Name
Value of Result R
AND
1000 0011
R R1 ^ R2
(iii) Shift right R1 twice

S3
S2
S1
S0
Ci
F=Shr(y)
Micro-operation
Name
Shift right
R Shr(R1)
Shr(y) Function applied Twice on R1

1
Micro-operation
S3
S2
S1
S0
Ci
F=Shr(y)
Name
Value of Result R
Shift right
1110 1000
R Shr(R1)
Page 39
(iv) Add of R1 and R2 with carry

S3
S2
S1
S0
Ci
F=x+y+1
Micro-operation
Name
Add with carry

R R1 + R2+1
Cout =
S3
S2
S1
S0
Ci
F=x+y+1
Micro-operation
Name
Value of Result R
Add with carry
1 0110 1111
R R1 + R2+1
Carry Out has occurred.
Page 40
EXPLAIN HOW OVERLAPPED REGISTER WINDOW

CAN BE IMPLEMENTED FOR PROCEDURE CALLS.
EXPLAIN THE PROCESS OF PARAMETER PASSING
FOR THE SUBROUTINE CALL ON THIS MACHINE?
IGNOU MCA ASSIGNMENT 2015 16
0 Comment
Maximum Marks : 100
Weightage : 25%
Assume that a RISC machine has 128 registers out of which 16 registers are reserved for
the Global variables and 16 for Instruction related tasks. This machine has been designed
to have 12 registers for storing four input parameters, four output parameters and four
local variables for a subroutine call. Explain with the help of a diagram, how the
overlapped register window can be implemented in this machine for procedure calls. You
must explain how the parameters will be passed, if a subroutine calls another subroutine.
Page 41
Assumptions:
Register file contains 128 registers. Let them be called by register number 0 127.
The table shows the use of registers: when there is call to function A (fA) which calls function B
(fB) and function B calls function C (fC).
Registers Nos.
0 15
Used for
Global variables required by fA,
(16 Registers)
fB, and fC
16-31
Unused
Function A
Function B
Function C
Temporary
32 43
(12 Registers)
Used by parameters of fCthat
variables of
may be passed to next call
function C
Local variables
44 59
(16 Registers)
Used for local variable of fC
offunction C
Temporary
60 71
(12 Registers)
Used by parameters that were
variables of
Parameters of
passed from fB fC
function B
function C
Local variables of
72 87
(16 Registers)
Local variables of fB
function B
Temporary
88 99
(12 Registers)
100 115
Parameters that were passed
variables of
Parameters of
from fA to fB
function A
function B
Local variable of fA
Local variables of
Page 42
function A
(16 Registers)
Parameters of
116 127
(12 Registers)
Parameter passed to fA
function A
This window consists of:
Page 43
Global registers which are shareable by all functions.

Parameters registers for holding parameters passed from the previous function to the
current function. They also hold the results that are to be passed back.
Local registers that hold the local variables, as assigned by the compiler.
Temporary registers: They are physically the same as the parameter registers at the next
level. This overlap permits parameter passing without the actual movement of data.
The register buffer is filled as function A called function B, function B called function C, function C
called function D. The function D is the current function. The current window pointer (CWP)
points to the register window of the most recent function (i.e. D). Any register references by a
machine instruction is added with the contents of this pointer to determine the actual physical
registers. On the other hand the saved window pointer identifies the window most recently saved
in memory. This action will be needed if a further call is made and there is no space for that call.
If function D now calls function E arguments for function E are placed in Ds temporary registers
indicated by D temp and the CWP is advanced by one window.
Figure:- circular overlapping windows

If function E now makes a call to function F, the call cannot be made with the current status of
the buffer, unless we free space equivalent to exactly one window. This condition can easily be
determined as current window pointer on incrementing will be equal to saved window pointer.
Now, we need to create space. The simplest way will be to swap FA register to memory and use
that space. Thus, an N window register file can support N 1 level of function calls.
Page 44
WHAT WILL BE THE VALUES OF SELECT INPUTS,
CARRY-IN INPUT AND RESULT OF OPERATION IF
THE FOLLOWING MICRO-OPERATIONS ARE
PERFORMED? IGNOU MCA ASSIGNMENT 2014
15
By GangadharKopella | October 14, 2014
0 Comment
Maximum Marks : 100
Weightage : 25%
Assume that you have a machine as shown in section 3.2.2 of Block 3 having the microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are
8 bit registers and contains 0001 1100 and 0111 1110 respectively. What will be the values
of select inputs, carry-in input and result of operation (including carry out bit) if the
following micro-operations are performed? (For each micro-operation you may assume
the initial value of R1 and R2 as given above).
(i) Addition of R1 and R2
(ii) Exclusive OR of R1 and R2
(iii)Shift left R2 once
(iv) Decrement R1
(i) Addition of R1 and R2
S3
S2
S1
S0
Ci
F=x+y
Micro-operation
Name
Addition
R R 1 + R2
Page 45
S3
S2
S1
S0
Ci
Micro-operation
F=x+y
Name
Value of Result R
Addition
1001 1010
R R 1 + R2
(ii) Exclusive OR of R1 and R2

S3
S2
S1
S0
Ci
F=x+y
Micro-operation
Name
Exclusive OR
R R 1 + R2
S3
S2
S1
S0
Ci
Micro-operation
Name
Value of Result R
Page 46
0
F=x+y
Exclusive OR
0110 0010
R R 1 + R2
(iii)Shift left R2 once

S3
S2
S1
S0
Ci
F=Shl(x)
Micro-operation
Name
Shift left
R Shl(R2)
Micro-operation
S3
S2
S1
S0
Ci
F=Shl(x)
Name
Value of Result R
Shift left
1111 1100
R Shl(R2)
Page 47
(iv) Decrement R1
S3
S2
S1
S0
Ci
F=x-1
Micro-operation
Name
Decrement
R R1 - 1
S3
S2
S1
S0
Ci
F=x-1
Micro-operation
Name
Value of Result R
Decrement
0001 1011
R R1 - 1
Page 48
EXPLAIN THE WORKING OF THE INSTRUCTION

PIPELINING, WITH THE HELP OF A DIAGRAM 5M
DEC2005
By GangadharKopella | November 7, 2014
0 Comment
Explain the working of the instruction pipelining, with the help of a diagram 5m Dec2005
INSTRUCTION PIPELINING
To extract better performance instruction execution can be done through instruction pipeline. The
instruction pipelining involves decomposing of an instruction execution to a number of pipeline
stages.
Some of the common pipeline stages can be instruction fetch (IF), instruction decode (ID),
operand fetch (OF), execute (EX), store results (SR).
An instruction pipe may involve any combination of such stages. A major design decision here is
that the instruction stages should be of equal execution time. The reason why it should be is,
A pipeline allows overlapped execution of instructions. Thus, during the course of execution of an
instruction the following may be a scenario of execution.
A pipeline allows overlapped execution of instructions. Thus, during the course of execution of an
instruction the following may be a scenario of execution.
Page 49
Please note the following observations about the above figure:
The pipeline stages are like steps. Thus, a step of the pipeline is to be complete in a time
slot. The size of the time slot will be governed by the stage taking maximum time. Thus, if
the time taken in various stages is almost similar, we get the best results.
The first instruction execution is completed on completion of 5th time slot, but afterwards, in
each time slot the next instruction gets executed. So, in ideal conditions one instruction is
executed in the pipeline in each time slot.
After the 5th time slot and afterwards the pipe is full. In the 5th time slot the stages of
execution of five instructions are:
SR (instruction 1) (Requires memory reference)
EX (instruction 2)
(No memory reference)
OF (instruction 3) (Requires memory reference)

ID (instruction 4)
(No memory reference)
IF (instruction 5) (Requires memory reference)
Exception
Page 50
DESIGN A TWO BIT DOWN COUNTER CIRCUIT THAT
COUNT FROM 11 TO 00 IGNOU MCA
ASSIGNMENT 2015 16
0 Comment
Design a two bit down counter circuit that count from 11 to 00. The initial state of the
counter may be assumed to be 11. The counter will be in following successive states: 11,
10, 01, 00, 11, 10, 01, 00, 11 Use any flip flop to design the circuit. You must design
them using state transition diagram and Karnaughs map.
Course
Code
:
BCSL-022
Course
Title
:
Assembly
Language
Programming
Lab
Assignment
Number
:
BCA(II)/L-022/Assignment/2015
Maximum
Marks
:
50
Weightage : 25%
Solution :
A sequential circuit is specified by a time sequence of external inputs, external outputs and
internal flip-flop binary states. Thus firstly, a state table and state diagram is used to describe
behaviour of the circuit.
Present State
Input
A
Next State
Flip-Flops Inputs
A
B
0
0
DB
0
0
DA
Page 51
0
1
1
1
1
1
0
0
0
1
0
1
There are 2 flip-flop inputs for counter i.e. A, B. The next state of flip-flop is given in the table. DA
indicates the flip flop input corresponding to flip-flop-A. This counter requires 2-flip-flops.
From this the flip flop input equations are simplified using K-Maps as shown below.
K-Map for DA is:
Page 52
K-Map for DB is:
Page 53
Thus, the simplified input equations for BCD counter are:

DA = ABC + |A|B + |A|C
DB = |B|C + BC
Page 54
The logic circuit can be made with 2 D flip flops, 2 OR gates & 4 AND gates.
WRITE A PROGRAM IN 8086 ASSEMBLY LANGUAGE

TO COUNT THE NUMBER OF ALPHABETS A, E
AND O (IRRESPECTIVE OF LOWER OR UPPER CASE)
IN A STRINGS IGNOU MCA ASSIGNMENT 2015
16
0 Comment
Page 55
Assignment Number : MCA(1)/012/Assign/2015-16
Maximum Marks : 100
Weightage : 25%
Write a program in 8086 assembly Language (with proper comments) to count the number
of alphabets a, e and o (irrespective of lower or upper case) in a strings. For example,
in case the strings is: ABaDEFeHIO the count of a will be 2, e is 2 and o is 1. You
may assume that string is available in the memory and is of length 10. Make suitable
assumptions, if any.
DATA SEGMENT
STR1 DB ABaDEFeHIO
A DB 0H
E DB 0H
O DB 0H
MSG1 DB 10,13,COUNT OF As IS : $
MSG2 DB 10,13,COUNT OF Es IS : $
MSG3 DB 10,13,COUNT OF Os IS : $
DATA ENDS
DISPLAY MACRO MSG
MOV AH,9
LEA DX,MSG
INT 21H
ENDM
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START:
MOV AX,DATA
MOV DS,AX
LEA SI,STR1
MOV CX,10
CHECK:
MOV AL,[SI]
CMP AL,A
JNE N1
INC A
N1:
CMP AL,a
JNE N2
INC A
N2: CMP AL,E
JNE N3
INC E
Page 56
N3: CMP AL,e
JNE N4
INC E
N4: CMP AL,O
JNE N5
INC O
N5: CMP AL,o
JNE N6
INC O
N6: INC SI
LOOP CHECK
DISPLAY MSG1
MOV DL,A
ADD DL,30H
MOV AH,2
INT 21H
DISPLAY MSG2
MOV DL,E
ADD DL,30H
MOV AH,2
INT 21H
DISPLAY MSG3
MOV DL,O
ADD DL,30H
MOV AH,2
INT 21H
MOV AH,4CH
INT 21H
CODE ENDS
END START
1. DATA SEGMENT
2. STR1 DB "ABaDEFeHIO"
3. A DB 0H
4. E DB 0H
5. O DB 0H
6. MSG1 DB 10,13,"COUNT OF A's IS : $"
7. MSG2 DB 10,13,"COUNT OF E's IS : $"
8. MSG3 DB 10,13,"COUNT OF O's IS : $"
9. DATA ENDS
10.
DISPLAY MACRO MSG
11.
MOV AH,9
Page 57
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
LEA DX,MSG
INT 21H
ENDM
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START:
MOV AX,DATA
MOV DS,AX
LEA SI,STR1
MOV CX,10
CHECK:
MOV AL,[SI]
CMP AL,'A'
JNE N1
INC A
N1:
CMP AL,'a'
JNE N2
INC A
N2: CMP AL,'E'
JNE N3
INC E
N3: CMP AL,'e'
JNE N4
INC E
N4: CMP AL,'O'
JNE N5
INC O
N5: CMP AL,'o'
JNE N6
INC O
N6: INC SI
LOOP CHECK
DISPLAY MSG1
MOV DL,A
ADD DL,30H
MOV AH,2
INT 21H
DISPLAY MSG2
MOV DL,E
ADD DL,30H
MOV AH,2
INT 21H
DISPLAY MSG3
MOV DL,O
Page 58
57.
58.
59.
60.
61.
62.
63.
ADD DL,30H
MOV AH,2
INT 21H
MOV AH,4CH
INT 21H
CODE ENDS
END START
64. Screen shots :-
Page 59
Page 60
66. After Execution :
67.
68.
A PROCEDURE IN ASSEMBLY LANGUAGE THAT

ACCEPTS A 2 DIGIT INPUT FROM THE KEYBOARD TO
PACKED BCD IGNOU MCA ASSIGNMENT 2014-15
0 Comment
Maximum Marks : 100
Weightage : 25%
Write a program in 8086 assembly language that accepts a 2 digit input from the keyboard
(as ASCII input) into packed BCD number. The packed BCD number may be stored in
memory.
DATA SEGMENT
MSG1 DB ENTER NUMBER : $
DIGIT1 DB ?
DIGIT2 DB ?
BCD DB ?
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA,CS:CODE
START:
Page 61
MOV AX,DATA
MOV DS,AX
LEA DX,MSG1
MOV AH,9
INT 21H
MOV AH,1
INT 21H
SUB AL,30H
MOV DIGIT1,AL
MOV AH,1
INT 21H
SUB AL,30H
MOV DIGIT2,AL
MOV AH,DIGIT1
MOV AL,DIGIT2
MOV CL,4
ROL AH,CL
ADD AL,AH
MOV BCD,AL
CODE ENDS
END START
Program Code :
1. DATA SEGMENT
2. MSG1 DB "ENTER NUMBER : $"
3. DIGIT1 DB ?
4. DIGIT2 DB ?
5. BCD DB ?
6. DATA ENDS
7. CODE SEGMENT
8. ASSUME DS:DATA,CS:CODE
9. START:
10.
MOV AX,DATA
11.
MOV DS,AX
12.
LEA DX,MSG1
13.
MOV AH,9
14.
INT 21H
15.
MOV AH,1
16.
INT 21H
17.
SUB AL,30H
Page 62
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
MOV DIGIT1,AL
MOV AH,1
INT 21H
SUB AL,30H
MOV DIGIT2,AL
MOV AH,DIGIT1
MOV AL,DIGIT2
MOV CL,4
ROL AH,CL
ADD AL,AH
MOV BCD,AL
CODE ENDS
END START
31. Screen shots :-
32.
33. Before Execution :-
Page 63
34.
35. After Execution :
36. -
37.
A PROCEDURE IN ASSEMBLY LANGUAGE PROGRAM

THAT RECEIVES ALPHABET Z RETURNS 1 OR 0
IGNOU MCA ASSIGNMENT 2015-16
0 Comment
Page 64
Maximum Marks : 100
Weightage : 25%
Write a simple near procedure in 8086 assembly language that receives an ASCII digit as
parameter. It returns 1 if the ASCII digit is Z else it returns 0. Make suitable assumptions,
if any.
DATA SEGMENT
MSG1 DB ENTER ALPHABET Z : $
MSG2 DB 10,13,BIT RETURNED IS : $
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA,CS:CODE
START:
MOV AX,DATA
MOV DS,AX
LEA DX,MSG1
MOV AH,9
INT 21H
MOV AH,1
INT 21H
MOV BL,AL
LEA DX,MSG2
MOV AH,9
INT 21H
CALL CHECK
ADD DL,30H
MOV AH,2
INT 21H
MOV AH,4CH
INT 21H
CODE ENDS
CHECK PROC NEAR
CMP BL,Z
JNE SKIP
MOV DL,1
JMP DONE
SKIP:
MOV DL,0
DONE:
Page 65
RET
CHECK ENDP
END START
program code :
1. DATA SEGMENT
2. MSG1 DB "ENTER ALPHABET 'Z' : $"
3. MSG2 DB 10,13,"BIT RETURNED IS : $"
4. DATA ENDS
5. CODE SEGMENT
6. ASSUME DS:DATA,CS:CODE
7. START:
8. MOV AX,DATA
9. MOV DS,AX
10.
LEA DX,MSG1
11.
MOV AH,9
12.
INT 21H
13.
MOV AH,1
14.
INT 21H
15.
MOV BL,AL
16.
LEA DX,MSG2
17.
MOV AH,9
18.
INT 21H
19.
CALL CHECK
20.
ADD DL,30H
21.
MOV AH,2
22.
INT 21H
23.
MOV AH,4CH
24.
INT 21H
25.
CODE ENDS
26.
CHECK PROC NEAR
27.
CMP BL,'Z'
28.
JNE SKIP
29.
MOV DL,1
30.
JMP DONE
31.
SKIP:
32.
MOV DL,0
33.
DONE:
34.
RET
35.
CHECK ENDP
36.
END START
37. Screen shots :-
Page 66
38.
39. After Execution :-
Page 67
40.
Page 68

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Ignousolvedassignments.

Now, Binary value of the given number

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Now, Binary value of the given number

+124 :Sign bit

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Now, covert it to signed 2s complement notation:-99 :Sign bit

-124 :Sign bit

-223 :Carry bit

Overflow condition occured.

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Evaluate 2s complement of 8 bits including sign bit.

Now, Binary value of the given number

+256 :Carry bit

Overflow condition occurred.

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(c)Convert string into UTF 16 code You may

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And Extended list is from 256 511.

(d)Use a Karnaughs map to design if the output bit

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Before Designing we should know inputs which is 4

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Its can also be written as F = (1, 3, 5, 7, 8, 10, 12, 14)

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(e)An 8 bit data 01101101 after transmission is

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SEC means Single Error Correction

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Parity bits are placed at 20 21 22 23

D1 D2 D3 D4 D5 D6 D7 D8 are the data sent and recd.

Before sending calculate Parity of Data to be sent.

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We found all parity bits, we will fill in the table:-

Assuming all parity sent correctly

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even parity will be 0

(f)Design a two bit counter (a sequential circuit) that

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K-Map for DA is:

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K-Map for DB is:

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Thus, the simplified input equations for Counter are:

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(g)Represent (124.0625)10 using IEEE 754 single

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S stands for Sign (white color)

0this Sign bit (1 bit)

S stands for Sign (white color)

0this Sign bit (1 bit)

First of all to represent we have (63.125)10 using IEEE 754

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Now lets work on Mantissa part

Fill the Significand in the beginning

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Note: we have to discard overflow bit since we have only 7 bits

For Double Precision Only Exponent

Note: we have to discard overflow bit since we have only 11 bits

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