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VIPer20A/ASP/ADIP
In
R D S(on)
VIPer20/SP/DIP
TYPE
620V
0.5 A
16
VIPer20A/ASP/ADIP
700V
0.5 A
18
PENTAWATT HV
FEATURE
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
CURRENT MODE CONTROL
SOFT START AND SHUT DOWN CONTROL
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
BLUE ANGEL NORM (<1W TOTAL POWER
CONSUMPTION)
INTERNALLY TRIMMED ZENER
REFERENCE
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
INTEGRATED START-UP SUPPLY
AVALANCHE RUGGED
OVERTEMPERATURE PROTECTION
LOW STAND-BY CURRENT
ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer20/20A, made
using
VIPower
M0
PENTAWATT HV (022Y)
10
PowerSO-10
DIP-8
BLOCK DIAGRAM
OSC
DRAIN
ON/OFF
OSCILLATOR
SECURITY
LATCH
UVLO
LOGIC
VDD
R/S
PWM
LATCH
FF
R1
S
FF
R2 R3
OVERTEMP.
DETECTOR
0.5 V
+
_
_
13 V
1.7
s
delay
250 n s
Blanking
0.5V
_
6 V/A
_
CURRENT
AMPLIFIER
ERROR
AMPLIFIER
COMP
February 2001
SOURCE
FC00491
4.5 V
1/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ABSOLUTE MAXIMUM RATING
Symbol
V DS
ID
V DD
V OS C
V COMP
I COMP
Vesd
I D(AR)
Ptot
Tj
T stg
Parameter
Continuous Drain-Source Voltage (Tj = 25 to 125 o C)
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
Maximum Current
Supply Voltage
Voltage Range Input
Voltage Range Input
Maximum Continuous Current
Value
Unit
-0.3 to 620
-0.3 to 700
Internally Limited
0 to 15
0 to VDD
0 to 5
2
4000
V
V
A
V
V
V
mA
V
0.5
0.4
57
Internally Limited
-65 to 150
A
A
W
o
C
o
C
THERMAL DATA
PE NTAWATT
PowerSO-10
DIP-8
o
C/W
2.0
C/W
60
C/W
R t hj -pin
R th j-case
Rt hj -amb.
20
Thermal Resistance Junction-c ase
Max
2.0
Max
70
35 #
(*) When mounted using the minimum recommended pad size on FR-4 board.
# On multylayer PCB
PENTAWATT HV (022Y)
PowerSO-10
DIP-8
OS C
Vdd
DR AIN
DR AIN
S OUR CE
COMP
5
S C10540
ID
VDD
IOSC
DRAIN
OSC
13V
+
COMP SOURC E
VDD
VDS
ICOMP
VO SC
VCOMP
FC00020
2/21
DR AIN
DR AIN
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ORDERING NUMBERS
PENTAWATT HV
PENTAWATT HV (022Y)
PowerSO-10
DIP-8
VIPer20
VIPer20A
VIPer20 (022Y)
VIPer20A (022Y)
VIPer20SP
VIPer20ASP
VIPer20DIP
VIPer20ADIP
COMP PIN :
This pin provides two functions :
SOURCE PIN:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD PIN :
This pin provides two functions :
OSC PIN :
An RT-CT network must be connected on that pin
to define the switching frequency. Note that
despite the connection of RT to VDD, no significant
frequency change occurs for V DD varying from 8V
to 15V. It provides also a synchronisation
capability, when connected to an external
frequency source.
3/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
AVALANCHE CHARACTERISTICS
Symbol
I D(a r)
E(a r)
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T j max, < 1%)
for VIPer20/SP/DIP
for VIPer20A/ASPA /DIP
(see fig.12)
Single Pulse Avalanche Energy
(starting Tj = 25 o C, ID = ID(ar))
Max Value
Unit
0.5
0.4
A
A
10
mJ
(see fig.12)
IDSS
R DS(o n)
Pa rameter
Drain-Source Voltage
Test Conditions
Min.
I D = 1 mA
VC OMP = 0 V
for VIPer20/SP/DIP
for VIPer20A/ASP/DIP (see fig.5)
620
700
Typ.
Unit
V
V
V COMP = 0 V T J= 125 o C
V DS = 620 V
for VIPer20/SP/DIP
V DS = 700 V
for VIPer20A/ASP/ADIP
I D = 0.4 A
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
I D = 0.4 A
T J = 100 o C
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
Max.
13.5
15.5
1.0
mA
1.0
mA
16
18
29
32
tf
Fall Time
ID = 0.2 A
(see fig.3)
100
ns
tr
Rise Time
I D = 0.4 A
(see fig. 3)
V in = 300 V (1)
50
ns
Output Capacitance
V DS = 25 V
90
pF
C OSS
SUPPLY SECTION
Symbol
Pa rameter
Test Conditions
Min.
Typ.
Max.
Unit
I DDch
Start-up Charging
Current
I DD 0
F SW = 0 KHz
12
I DD 1
F SW = 100 KHz
13
mA
I DD 2
F SW = 200 KHz
14
mA
V DD = 5 V
V DS = 70 V
(see fig. 2 and fig. 15)
-2
mA
16
mA
VDDoff
Undervoltage Shutdown
(see fig. 2)
V DDon
Undervoltage Reset
(see fig. 2)
11
12
V DDhyst
Hy steresis S tart-up
(see fig. 2)
4/21
2.4
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATOR SECTION
Symbol
FS W
Pa rameter
Oscillator Frequency
Total Variation
Test Conditions
C T =2.4 nF
R T = 8.2 K
V DD = 9 to15 V
CT 5%
with R T 1%
(see fig. 6 and fig. 9)
Min.
Typ.
Max.
Unit
90
100
110
KHz
V OSCih
7.1
VOSCil
3.7
Pa rameter
Test Conditions
ICOMP = 0 mA
Total Variation
T J = 0 to 100 o C
G BW
AVOL
DC Transconductance
VCOMP = 2.5 V
V DDre g
Gm
(see fig.1)
ICOMP = -400 A
V COMPHI
IC OMPLO
ICOMPHI
V COMPLO
(see fig. 1)
Min.
Typ.
Max.
12.6
13
13.4
Unit
V
150
KHz
45
52
dB
1.1
1.5
1.9
mA/V
VDD = 14 V
0.2
ICOMP = 400 A
V DD = 12 V
4.5
VCOMP = 2.5 V
V DD = 14 V
-600
VCOMP = 2.5 V
V DD = 12 V
600
Pa rameter
Test Conditions
VCOMP = 1 to 3 V
VC OMP offset
IDpeak = 10 mA
Min.
Typ.
Max.
Unit
4.2
7.8
V/A
0.5
0.67
0.5
td
tb
Blanking Time
250
Minimum on Time
350
t on(min)
ID = 1 A
V
0.9
250
A
ns
360
ns
ns
Pa rameter
VCOMPth
Restart threshold
(see fig. 4)
0.5
(see fig. 4)
T tsd
Thermal Shutdown
Temperature
(see fig. 8)
T hyst
Thermal Shutdown
Hy steresis
(see fig. 8)
tD IS su
Test Conditions
Min.
140
Typ.
Max.
Unit
1.7
170
190
40
V
o
5/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 1: VDD Regulation Point
ICOMP
IDD
Slope =
Gm in mA/V
ICOMPHI
I DD0
VDD
VDS = 70 V
Fsw = 0
VDDhyst
VDDoff
ICOMPLO
VDD
VDDon
IDDch
VDDreg
FC001 50
FC00170
ID
t
VCOMP
tDIS s u
10% Ipeak
VDS
VCOMPth
90% VD
ID
10% VD
t
tf
tr
E NABL E
FC00160
E NABL E
DIS ABL E
F C00060
F C00180
1.15
F C00190
(% )
B VDS S
(Normaliz ed)
1
0
1.1
-1
-2
1.05
-3
1
-4
0.95
6/21
-5
0
20
40 60 80 100 120
T emperature(C)
20
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 7: Start-up Waveforms
t
Vdd
Vddon
Vddoff
t
Id
t
Vcomp
t
S C10191
7/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 9: Oscillator
VDD
Rt
OSC
CLK
~360
Ct
DMAX = 1
550
RT 150
FC00040
0.9
Dmax
0.8
0.7
0.6
0.5
10
20
30
50
Rt (k)
Oscillator frequency vs Rt and Ct
FC00030
1,000
Ct = 1.5 nF
500
Frequency (kHz)
Ct = 2.7 nF
300
Ct = 4.7 nF
200
Ct = 10 nF
100
50
30
Rt (k)
8/21
10
20
30
50
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 10: Error Amplifier Frequency Response
FC00200
60
RCOMP = +
RCOMP = 270k
40
RCOMP = 82k
RCOMP = 27k
20
RCOMP = 12k
(20)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
200
RCOMP = +
150
RCOMP = 270k
Phase ()
RCOMP = 82k
RCOMP = 27k
100
RCOMP = 12k
50
0
(50)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
9/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 12: Avalance Test Circuit
L1
1mH
2
VDD
1
3
DRAIN
OSC
13V
BT1
0 to 20V
+
COMP
BT2
12V
C1
47uF
16V
Q1
2 x STHV102FI in parallel
R1
SOURCE
5
4
47
GENERATOR INPUT
500us PULSE
U1
VIPer20
R2
R3
1k
100
F C00196
10/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 13: Off Line Power Supply With Auxliary Supply Feedback
F1
BR1
TR2
C1
TR1
D2
AC IN
L2
+Vcc
D1
R9
C2
C7
C9
R1
C3
GND
D3
C10
R7
C4
R2
VDD
DRAIN
OSC
13V
VIPer20
+
COMP SOURCE
C5
C6
C11
R3
FC00401
TR2
C1
TR1
D2
AC IN
L2
+Vcc
D1
R9
C2
C7
C9
R1
C3
GND
D3
C10
R7
C4
R2
VDD
DRAIN
OSC
13V
VIPer20
+
COMP SOURCE
C5
C11
C6
R3
R6
ISO1
R4
C8
U2
R5
FC00411
11/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
OPERATION DESCRIPTION :
CURRENT MODE TOPOLOGY:
The current mode control method, like the one
integrated in the VIPer20/20A uses two control
loops - an inner current control loop and an outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified
output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
winding of the transformer.
Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
following the dynamic of the regulation loop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side
capacitance or secondary side rectifier reverse
recovery time.
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary side.
The transition from normal operation to burst
mode operation happens for a power PSTBY given
by :
1
2
PSTBY = LP ISTBY FSW
2
12/21
Where:
LP is the primary inductance of the transformer.
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as :
(tb + td) VIN
ISTBY =
LP
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
short circuit.
The external capacitor CVDD on the VDD pin must
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time tSS depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the
COMP pin. The following formula can be used for
defining the minimum capacitor needed:
IDD tSS
CVDD >
VDDhyst
where:
IDD is the consumption current on the VDD pin
when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the
device begins to switch. Worst case is generally
at full load.
VDDhyst is the voltage hysteresis of the UVLO
logic. Refer to the minimum specified value.
Soft start feature can be implemented on the
COMP pin through a simple capacitor which will
be also used as the compensation network. In
this case, the regulation loop bandwidth is rather
low, because of the large value of this capacitor.
In case a large regulation loop bandwidth is
mandatory, the schematics of figure 16 can be
VDD
2 mA
VDDon
VDDoff
15 mA
3 mA
VDD
1 mA
DR AIN
15 mA
CVDD
R ef.
t
Auxil i ary pri mary
winding
VIP er20
S OU R CE
F C00101A
13/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjusted separately.
If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is
oscillating between VDDon and VDDoff. This voltage
can be used for supplying external functions,
provided that their consumption doesnt exceed
0.5mA. Figure 17 shows a typical application of
this function, with a latched shut down. Once the
Shutdown signal has been activated, the device
remains in the off state until the input voltage is
removed.
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer20/20A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (ICOMP) versus change in
input voltage (VDD). Thus:
ICOMP
Gm =
VDD
The output impedance ZCOMP at the output of this
amplifier (COMP pin) can be defined as:
VCOMP 1 VCOMP
ZCOMP =
=
x
ICOMP Gm
VDD
This last equation shows that the open loop gain
AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer20/20A is 1.5 mA/V
typically.
D2
D3
VIPer20
VDD
VDD
O SC
13V
Q2
R3
13V
D1
C4
+
COMP
AUXILIARY
WINDING
R3
SOURCE
R2
R1
R2
C1
R4
Shutdown
+ C2
FC00431
14/21
DRAIN
OSC
COMP SOURCE
+ C3
VIPer20
R1
DRAIN
Q1
D1
FC00440
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
frequency source. Figure 20 shows one possible
schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be kept at a low value (500ns
is sufficient) for minimizing consumption. The
optocoupler must be able to provide 20mA
through the optotransistor.
PRIMARY PEAK CURRENT LIMITATION
The primary IDPEAK current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit
based on Q1, R1 and R2 clamps the voltage on
the COMP pin in order to limit the primary peak
current of the device to a value:
IDPEAK =
VCOMP 0.5
HID
where:
VCOMP = 0.6 x
R1 + R2
R2
VIPer20
VDD
R2
DRAIN
R1
VIPer20
OSC
13V
VDD
+
COMP
DRAIN
OSC
SOURCE
13V
+
COMP SOURCE
C2
R1
C2
C1
Q1
C1
C3
R3
FC00451
FC00461
VIPer20
VDD
OSC
13V
VIPer20
VDD
DRAIN
+
COMP SOURCE
DRAIN
OSC
13V
+
COMP SOURCE
R1
10 k
Q1
R2
FC00470
FC00480
15/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 22: Recommended layout
T1
D1
C7
D2
R1
VDD
C1
To second ary
filtering and loa d
DRAIN
1 OSC
13 V
From input
d iode s b ridge
C5
+
COMP
SOURCE
U1
VIPerXX0
R2
C6
C2
C3
ISO1
C4
FC00500
LAYOUT CONSIDERATIONS
Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:
16/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
mm.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
4.30
4.80
0.169
0.189
1.17
1.37
0.046
0.054
2.40
2.80
0.094
0.11
0.35
0.55
0.014
0.022
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
H2
0.382
10.40
10.05
H3
0.409
10.40
0.396
0.409
15.60
17.30
6.14
0.681
L1
14.60
15.22
0.575
0.599
L2
21.20
21.85
0.835
0.860
L3
22.20
22.82
0.874
0.898
L5
2.60
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6.60
0.236
0.260
2.50
3.10
0.098
0.122
M1
4.50
5.60
0.177
0.220
0.50
0.02
V4
Diam
90 (typ)
3.65
3.85
0.144
0.152
P023H3
17/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
mm.
MIN.
TYP
MAX.
MIN.
4.30
4.80
0.169
0.189
1.17
1.37
0.046
0.054
2.40
2.80
0.094
0.110
0.35
0.55
0.014
0.022
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
TYP.
MAX.
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H3
10.05
10.40
0.396
0.409
16.42
17.42
0.646
0.686
L1
14.60
15.22
0.575
0.599
L3
20.52
21.52
0.808
0.847
L5
2.60
3.00
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6.00
6.60
0.236
0.260
2.50
3.10
0.098
0.122
M1
5.00
5.70
0.197
H2
10.40
0.409
0.224
0.50
0.020
V4
90
90
Diam.
18/21
inch
3.70
3.90
0.146
0.154
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
DIM.
MIN.
A
A (*)
A1
B
B (*)
C
C (*)
D
D1
E
E2
E2 (*)
E4
E4 (*)
e
F
F (*)
H
H (*)
h
L
L (*)
(*)
inch
TYP
3.35
3.4
0.00
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
MAX.
MIN.
3.65
3.6
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
0.132
0.134
0.000
0.016
0.014
0.013
0.009
0.370
0.291
0.366
0.283
0.287
0.232
0.232
1.35
1.40
14.40
14.35
0.049
0.047
0.543
0.545
1.80
1.10
8
8
0.047
0.031
0
2
1.27
TYP.
MAX.
0.144
0.142
0.004
0.024
0.021
0.022
0.0126
0.378
0.300
0.374
300
0.295
0.240
0.248
0.050
1.25
1.20
13.80
13.85
0.50
0.053
0.055
0.567
0.565
0.002
1.20
0.80
0
2
0.070
0.043
8
8
0.10 A B
10
E2
SEATING
PLANE
e
DETAIL A
0.25
E4
D
= D1 =
=
=
SEATING
PLANE
A
F
A1
A1
L
DETAIL A
P095A
19/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
mm.
MIN.
TYP
inch
MAX.
MIN.
3.3
TYP.
MAX.
0.130
a1
0.7
1.39
1.65
0.055
0.065
B1
0.91
1.04
0.036
0.041
0.5
0.015
b
b1
0.028
0.5
0.38
0.020
0.020
9.8
0.386
8.8
0.346
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
7.1
0.280
4.8
0.189
L
Z
3.3
0.44
0.130
1.6
0.017
0.063
20/21
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
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