ASTRO Userguide

Astro
User Guide
Version Z-2007.03, March 2007
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Copyright 2007 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary
information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and
may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may
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without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
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This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of
__________________________________________ and its employees. This is copy number __________.
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Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to
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SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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Registered Trademarks ()
Synopsys, AMPS, Cadabra, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM,
HSPICE, iN-Phase, in-Sync, Leda, MAST, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler,
PrimeTime, SiVL, SNUG, SolvNet, System Compiler, TetraMAX, VCS, Vera, and YIELDirector are registered trademarks
of Synopsys, Inc.
Trademarks ()
AFGen, Apollo, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, Columbia, Columbia-CE, Cosmos,
CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, DC Expert, DC Professional, DC Ultra, Design Analyzer,
Design Vision, DesignerHDL, Direct Silicon Access, Discovery, Encore, Galaxy, HANEX, HDL Compiler, Hercules,
plus
Hierarchical Optimization Technology, HSIM
, HSPICE-Link, i-Virtual Stepper, iN-Tandem, Jupiter, Jupiter-DP,
JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Magellan, Mars, Mars-Xtalk, Milkyway,
ModelSource, Module Compiler, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Raphael-NES, Saturn, Scirocco,
Scirocco-i, Star-RCXT, Star-SimXT, Taurus, TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are
trademarks of Synopsys, Inc.
Service Marks (SM)

MAP-in, SVP Caf, and TAP-in are service marks of Synopsys, Inc.
SystemC is a trademark of the Open SystemC Initiative and is used under license.
ARM and AMBA are registered trademarks of ARM Limited.
Saber is a registered trademark of SabreMark Limited Partnership and is used under license.
All other product or company names may be trademarks of their respective owners.
Astro User Guide, version Z-2007.03
ii
Contents
Whats New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xlviii
About This Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xlviii
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
lii
1. Introduction to Astro
Benefits of Using Astro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
Astro Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
Astro Licensing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6
Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6
Astro Place and Route Flow and Documentation Set . . . . . . . . . .
1-7
Astro Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-9
Recommended Astro Script-Based Methodology . . . . . . . . .
1-10
Power and Reliability Analysis . . . . . . . . . . . . . . . . . . . . . . . .

Astro-Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PrimeRail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-11
1-11
1-12
1-13
iii
2. Using the Astro GUI and Command Files

User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
Scheme and Tool Command Language (Tcl) . . . . . . . . . . . . . . . .
2-3
Starting an Astro Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4
Using Startup Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupting or Terminating a Job. . . . . . . . . . . . . . . . . . . . . . . . . .
2-9
Using Menu Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-10
The Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-10
Detaching Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-12
Types of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-12
Using the Command Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-13
Finding Commands in Scheme Mode . . . . . . . . . . . . . . . . . .
2-13
Finding Commands in Tcl Mode . . . . . . . . . . . . . . . . . . . . . .
2-15
Determining License Availability . . . . . . . . . . . . . . . . . . . . . .
2-16
Working With and Without the GUI . . . . . . . . . . . . . . . . . . . .
2-17
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-17
Online Documentation System . . . . . . . . . . . . . . . . . . . . . . .

Using the Web Browser . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-17
2-18
Displaying Help in Tcl Mode . . . . . . . . . . . . . . . . . . . . . . . . .
2-21
Tcl Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-22
Opening and Creating Libraries and Cells . . . . . . . . . . . . . . . . . .
iv
2-8
2-22
Opening an Existing Library. . . . . . . . . . . . . . . . . . . . . . . . . .
2-22
Opening an Existing Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-23
Creating Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-26
Working With Layout Windows . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-27
Navigating Inside a Layout Window . . . . . . . . . . . . . . . . . . . .

Navigation Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command History Buttons . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting and Editing Buttons . . . . . . . . . . . . . . . . . . . . . .
2-28
2-28
2-30
2-31
Using the Context View and Information Bar . . . . . . . . . . . . .
2-33
Opening Multiple Layout Windows. . . . . . . . . . . . . . . . . . . . .
2-34
Making a Layout Window Current . . . . . . . . . . . . . . . . . . . . .
2-34
Opening the Same Cell in Multiple Layout Windows . . . . . . .
2-35
Creating and Running Command Files . . . . . . . . . . . . . . . . . . . . .
2-35
Replay Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-36
Startup Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tool Startup Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Startup Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-37
2-37
2-38
Load Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-38
Script Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-39
Exiting an Astro Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-39
Defining and Using Stroke Command Sequences . . . . . . . . . . . .
2-41
Using Integer and Real Parameters for Astro Operations . . . . . . .
2-43
3. Creating Milkyway Reference Libraries

Using the Milkyway Database . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
Milkyway File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technology Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Library Format Files . . . . . . . . . . . . . . . . . . . . . . . . . .
Top Design Format Files . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3-2
3-2
3-3
GDSII Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Netlist Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synopsys Design Constraints File . . . . . . . . . . . . . . . . . . .
Design Database File . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis Library File . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Input Requirements for Astro . . . . . . . . . . . . . . . . . . . .
3-4
Data Output From Astro . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
Milkyway Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
Milkyway Library Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
Creating a Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
3-3
3-3
3-3
3-3
3-4
3-9
Creating the Library With the read_lib Command . . . . . . . . .
3-11
Creating the Library With the Individual Commands . . . . . . .
3-15
Creating a Macro Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-24
Creating LM Views for Timing and Power Analysis . . . . . . . . . . . .
3-29
Creating Logical Equivalent Cell Information. . . . . . . . . . . . . . . . .
3-35
Extracting and Loading Logical Equivalent Cell

Information From Boolean Information . . . . . . . . . . . . . . .
3-36
Using Design LEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-37
Specifying Design LEQ From Multiple Reference

Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-38
Clearing Design LEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-39
Verifying Design LEQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-39
Loading Pad Orientation, Diode Protections, and

Gate Size Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-40
Defining Multiple Tiles for Placement . . . . . . . . . . . . . . . . . . . . . .
3-42
4. Creating a Design Library and Adding Data

Creating a Design Library With a Verilog Netlist . . . . . . . . . . . . . .
4-2
Creating a Design Library With a VHDL or EDIF Netlist . . . . . . . .
4-8
Adding TLU or TLUPlus Capacitance Tables to a

Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8
Preserving Hierarchy and Generating Hierarchical

Verilog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11
Initializing Hierarchy Preservation . . . . . . . . . . . . . . . . . . . . .
4-16
Marking Module Instances As Preserved . . . . . . . . . . . . . . .
4-18
Generating Hierarchical Verilog . . . . . . . . . . . . . . . . . . . . . . .
4-19
Repairing Hierarchy Preservation and Deleting

Hiconn Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-23
Deleting Hierarchical Preservation. . . . . . . . . . . . . . . . . . . . .
4-28
Hierarchical Preservation Information . . . . . . . . . . . . . . . . . .
4-28
Checking Hierarchy Preservation Consistency . . . . . . . . . . .
4-28
Hierarchical Inout Port Direction . . . . . . . . . . . . . . . . . . . . . .
4-29
Dangling Ports Connected to Hierarchy Inout Ports . . . . . . .
4-29
Loading Power Supply Information . . . . . . . . . . . . . . . . . . . . . . . .
4-29
Creating LOGIC Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-30
5. Floorplanning and Connecting Power and

Ground
Connecting Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
Floorplanning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
Adding Power and Ground Rings . . . . . . . . . . . . . . . . . . . . . . . . .
5-10
vii
Adding Power and Ground Straps . . . . . . . . . . . . . . . . . . . . . . . . .
5-14
Prerouting Standard Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18
6. Setting Up the Design Timing

Checking Design Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3
Loading Timing Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-6
Loading Synopsys Design Constraints . . . . . . . . . . . . . . . . .
6-9
Writing Timing Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . .
6-11
Modifying SDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . .
6-12
Backward Compatibility of SDC Commands . . . . . . . . . . . . .
6-13
Writing ast Design Constraint Commands . . . . . . . . . . . . . . .
6-14
Unit Consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
6-16
Specifying Units in the SDC File . . . . . . . . . . . . . . . . . . . . . .
6-17
Checking Unit Consistency . . . . . . . . . . . . . . . . . . . . . . . . . .
6-18
Reporting Design Unit Information. . . . . . . . . . . . . . . . . . . . .
6-18
Writing Out Design Unit Information . . . . . . . . . . . . . . . . . . .
6-18
Astro Timing Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-19
Environment Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECS and Slew Degradation . . . . . . . . . . . . . . . . . . . . . . . .
Setting Ideal Network Delay (Clock Latency) . . . . . . . . . . .
6-20
6-29
6-30
Optimization Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-31
Library Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-37
Parasitics Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-38
Model Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-42
Xtalk Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-45
Crosstalk Filtering Mechanisms . . . . . . . . . . . . . . . . . . . . .

Reporting Crosstalk Filtering Thresholds . . . . . . . . . . . . . .
Sample Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Single Peak Noise Threshold . . . . . . . . . . . . . .
Specifying Accumulated Peak Noise Threshold. . . . . . . . .
Specifying Total Peak Noise Threshold . . . . . . . . . . . . . . .
Specifying Net-Based Noise Thresholds With an
Input File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-49
6-50
6-50
6-51
6-52
6-53
Dynamic Latch Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-55
Setting Clock Transition Defaults at the Clock Pins . . . . . . . . . . . .
6-58
Setting Net Transition Defaults for Nonclock Nets . . . . . . . . . . . . .
6-59
Setting Maximum Capacitance and Transition

Constraints on Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . .
6-60
Setting Maximum Capacitance Constraints on Clock

Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Scheme Commands. . . . . . . . . . . . . . . . . . . . . .
Using the Tcl Command. . . . . . . . . . . . . . . . . . . . . . . . . . .
6-60
6-60
6-62
Setting Maximum Transition Constraints on Clock

Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-62
Setting Capacitance, Transition, and Delay Defaults

for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-53
6-63
7. Analyzing Timing
Using Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Clock Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Probing Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Analyzer Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3
7-10
7-11
7-12
ix
Path Timing Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Search Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-14
7-14
7-15
7-17
Instance Timing Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-17
Net Timing Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-18
Schematic Probe Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-19
Interactive Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
astEdit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-21
astChangeNetlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-23
Place and Route Summary Report . . . . . . . . . . . . . . . . . . . . . . . .
7-21
7-25
Placement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-27
Global Routing Information . . . . . . . . . . . . . . . . . . . . . . . . . .
7-27
Timing/Optimization Information . . . . . . . . . . . . . . . . . . . . . .
7-27
DRC Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-29
Checking Timing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-30
Checking Timing and Optimization for the Design . . . . . . . . . . . .
7-32
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-34
Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-36
Checking Timing Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-36
Effects of Synopsys Design Constraints on Timing

Analysis and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-37
Design Feasibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-39
Checking Library Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-39
Checking Logical Equivalence Information . . . . . . . . . . . . . . . . . .
7-40
Adjusting Preroute Pessimism and Optimism of

Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-40
Determining Extraction in Auto Mode . . . . . . . . . . . . . . . . . . . . . .
7-41
Checking TLU Capacitance Model Parameters. . . . . . . . . . . . . . .
7-41
Using TLUPlus Capacitance and Resistance Models . . . . . . . . . .
7-43
Generating TLUPlus Capacitance and Resistance

Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-43
TLUPlus Resistance Model Considerations. . . . . . . . . . . . . .
7-45
Working With TLUPlus Model Files . . . . . . . . . . . . . . . . . . . .
7-46
Non-Unate Clock Network Analysis. . . . . . . . . . . . . . . . . . . . . . . .
7-47
8. Placement and Placement Optimizations

Placement Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3
Setting Placement Common Options . . . . . . . . . . . . . . . . . . . . . .
8-9
Placing Cells Close to Magnet Objects . . . . . . . . . . . . . . . . . . . . .
8-14
Defining Magnets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-14
Specifying Net Weight Constraints . . . . . . . . . . . . . . . . . . . .
8-15
Using astMagnetPlace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-16
Performing Automatic Placement and Optimization

Before Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . .
8-17
Using Double-Height Cells. . . . . . . . . . . . . . . . . . . . . . . . . . .
8-20
Setting the Size Only Constraint . . . . . . . . . . . . . . . . . . . . . .
8-20
Defining Placement Restrictions for Small (Sliver)

Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-21
xi
Using astAutoPlace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Evaluating Automatic Placement . . . . . . . . . . . . . . . . . . . . . . . . . .
8-28
About Congestion Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-28
Displaying Placement Congestion Maps . . . . . . . . . . . . . . . .
8-31
Updating Placement Congestion Maps . . . . . . . . . . . . . . . . .
8-32
Saving and Loading Placement Congestion Maps . . . . . . . .
8-33
Generating and Displaying Coupling Capacitance Maps. . . .
8-33
Optimizing Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-35
Performing Clock Tree Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . .
8-36
Setting Clock Tree Synthesis Common Options and

Preparing Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-36
Running Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . .
8-38
Performing Postplacement Optimization After Clock

Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-40
Optimizing Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-43
Optimizing Clock Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-43
Enabling Optimization by Group Path . . . . . . . . . . . . . . . . . .
8-45
Reporting Group Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-45
Optimizing Mixed Signal Nets . . . . . . . . . . . . . . . . . . . . . . . .
8-45
Carrying Out Additional Processes . . . . . . . . . . . . . . . . . . . . . . . .
xii
8-22
8-46
Disconnecting Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . .
8-46
Distributing Spare Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-47
Adding Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-48
Inserting Tie-High, Tie-Low, and Tie-HighLow Cells . . . . . . .
8-52
Using Alternative Placement and Optimization

Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-58
Performing Preplacement Optimization . . . . . . . . . . . . . . . . .

High-Fanout Collapse. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design FeasibilityReporting Ideal Slack . . . . . . . . . . . . .
Astro Resynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffering Nonclock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-58
8-63
8-63
8-64
8-64
8-65
Performing Placement and In-Placement Optimization . . . . .

Running Search and Refine . . . . . . . . . . . . . . . . . . . . . . . .
Optimizing High-Fanout Nets . . . . . . . . . . . . . . . . . . . . . . .
8-66
8-67
8-68
Refining Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performing Search and Refine . . . . . . . . . . . . . . . . . . . . . .
Moving Standard Cells in a Specific Area . . . . . . . . . . . . .
8-69
8-69
8-71
Performing Postplacement Optimization . . . . . . . . . . . . . . . .

8-71
Postplacement Optimization Design Flow . . . . . . . . . . . . . 8-71
Topology-Based Methodology . . . . . . . . . . . . . . . . . . . . . . 8-74
Performing Postplacement Optimization
Phase 1 Before Clock Tree Synthesis. . . . . . . . . . . . . . 8-78
Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-83
Running Postplacement Optimization Phase 2 . . . . . . . . . 8-83
Design Rule Fixing in Astro . . . . . . . . . . . . . . . . . . . . . . . . 8-87
Hold Slack Optimization in Astro . . . . . . . . . . . . . . . . . . . . 8-96
Area Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-103
9. Clock Tree Synthesis and Clock Tree Optimizations
About Astro Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . .
9-3
Preparing Library Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-7
Preparing Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-9
xiii
Checking Clock Tree Data in the Design . . . . . . . . . . . . . . . . . . . .
9-12
Viewing Clock Structures in the Design. . . . . . . . . . . . . . . . . . . . .
9-14

Preparing Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-18
Setting the Clock Common Options. . . . . . . . . . . . . . . . . . . .

Defining the Clock Tree Root . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Pin and Port Definition . . . . . . . . . . . . . . . . .
Clock Tree Sink Pins and Synchronous Pins . . . . . . . . . . .
Pulse-Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Tree Stop Pins and Ignore Pins . . . . . . . . . . . . . . . .
Buffers and Inverters for Clock Tree Synthesis. . . . . . . . . .
Logically Equivalent Cells for Clock Tree Optimization. . . .
Delay Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dummy Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Tree Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Tree Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Tree Synthesis Specifications. . . . . . . . . . . . . . . . . .
Gated and Nongated Clock Trees . . . . . . . . . . . . . . . . . . .
9-18
9-20
9-22
9-24
9-26
9-28
9-29
9-33
9-36
9-37
9-39
9-43
9-47
9-49
Splitting Clock Nets to Improve Clock Tree Results . . . . . . . .
9-49
Setting Clock Sinks As Fixed . . . . . . . . . . . . . . . . . . . . . . . . .
9-54
Setting Special Routing Rules to Clock Nets . . . . . . . . . . . . .
9-56
Deleting Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-58
Warning Message for Clock Routed Designs . . . . . . . . . . . .
9-59
Removing Transition Defaults on Clocks . . . . . . . . . . . . . . . .
9-60
Choosing the Clock Tree Synthesis Building Style . . . . . . . .
9-60
Performing Clock Tree Synthesis After Placement . . . . . . . . . . . .

Using the Clock Tree Synthesis Dialog Box . . . . . . . . . . . . . .
xiv
9-62
9-63
Synthesizing Clock Trees in Worst and Best Cases

Simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Skew Clock Tree Synthesis. . . . . . . . . . . . . . . . . . . .
Useful Skew Clock Tree Synthesis . . . . . . . . . . . . . . . . . . .
Top-Level Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . .
9-64
9-65
9-66
9-66
Exploring Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-66
Multiple Clocks With Domain Overlap . . . . . . . . . . . . . . . . . .
9-67
Preserving Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-67
Synthesizing Clock Trees With Local Skew . . . . . . . . . . . . . .
9-68
Synthesizing Clock Trees With Useful Skew . . . . . . . . . . . . .
9-70
Synthesizing Clock Trees for Top-Level and Complex

Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-72
Optimizing Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-75
Resetting Clock Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-76
Using the Clock Tree Optimization Dialog Box. . . . . . . . . . . .

Buffer Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Sizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dummy Load Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-77
9-78
9-79
9-80
9-80
9-81
9-81
9-82
9-82
Balancing Interclock Delays . . . . . . . . . . . . . . . . . . . . . . . . . .
9-83
Optimizing Useful Skew Before Routing . . . . . . . . . . . . . . . .
9-85
Running Postrouting Clock Tree Optimization . . . . . . . . . . . .

Running ECO Routing After Postrouting Clock Tree
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-90
9-91
xv
Running Incremental Clock Tree Synthesis . . . . . . . . . . . .

Using Interactive Clock Tree Synthesis . . . . . . . . . . . . . . .
Analyzing Clock Tree Synthesis Results . . . . . . . . . . . . . .
Analyzing Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Skew for Synthesized Nets . . . . . . . . . . . . . . . .
Synthesizing High-Fanout Nets . . . . . . . . . . . . . . . . . . . . .
Reporting Clock Tree Power Consumption. . . . . . . . . . . . .
9-94
9-96
9-99
9-102
9-107
9-109
9-111
Routing Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-114

10. Routing
Routing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3
Routing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-5
Checking the Design Before Routing . . . . . . . . . . . . . . . . . . .
10-6
Preroutes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-7
Net-Based Routing Rule Tables. . . . . . . . . . . . . . . . . . . . . . .
10-7
Removing Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-8
Adjusting Metal Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-9
Controlling Routing Layers. . . . . . . . . . . . . . . . . . . . . . . . . . .
10-10
Defining and Assigning Variable Routing Rules. . . . . . . . . . . 10-11

Defining Variable Routing Rules. . . . . . . . . . . . . . . . . . . . . 10-13
Assigning Variable Routing Rules . . . . . . . . . . . . . . . . . . . 10-15
Setting Net Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-16
Deep Submicron Design Rule Support . . . . . . . . . . . . . . . . .
10-18
Setting Routing Common Options . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

Routing Groups of Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
Routing Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xvi
10-22
Preparing to Route Clock Nets. . . . . . . . . . . . . . . . . . . . . . 10-22

Defining Pseudo Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
Using axgRouteGroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-23
Setting Crosstalk Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25

Performing Automatic Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Density-Driven Global Routing . . . . . . . . . . . . .
RC Layer Optimization in Global Routing. . . . . . . . . . . . . .
Specifying a No Buffer Zone . . . . . . . . . . . . . . . . . . . . . . .
Performing Global Routing . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying Global Routing Congestion Maps . . . . . . . . . . .
Optimizing After Global Routing . . . . . . . . . . . . . . . . . . . . .
Running Incremental Global Routing . . . . . . . . . . . . . . . . .
10-27
10-28
10-28
10-29
10-30
10-30
10-32
10-32
Track Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Density-Driven Track Assignment . . . . . . . . . . .
Limiting Net Layer Length to Prevent Floating
Antennas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performing Track Assignment. . . . . . . . . . . . . . . . . . . . . . .
Optimizing After Track Assignment. . . . . . . . . . . . . . . . . . .
10-33
10-34
Detail Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performing Detail Routing . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Misaligned Tracks and Off-Grid Pins . . . . . . . . . .
Optimizing After Detail Routing . . . . . . . . . . . . . . . . . . . . .
10-36
10-36
10-36
10-37
Search-and-Repair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-37
10-34
10-35
10-35
Reducing Wire Length and Via Count . . . . . . . . . . . . . . . . . . . . . . 10-38

Performing Additional Routing Processes . . . . . . . . . . . . . . . . . . . 10-39
Removing Unnecessary Stubs . . . . . . . . . . . . . . . . . . . . . . .
10-39
xvii
Filling Notches and Gaps. . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-39
Shielding Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shielding With Rules Defined As Variable Routing
Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ignoring Shielding During Detail Routing . . . . . . . . . . . . . .
Shielding With Default Spacing Rules . . . . . . . . . . . . . . . .
10-40
Running ECO Routing on Detail-Routed Designs . . . . . . . . .
10-44
10-41
10-42
10-42
Using Alternative Routing Commands . . . . . . . . . . . . . . . . . . . . . 10-46

Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-46
Track Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-48
Detail Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-48
Search-and-Repair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-50
Using Distributed Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52

Initializing, Setting Up, and Running . . . . . . . . . . . . . . . . . . .
10-53
Errors and Causes for Failure to Connect . . . . . . . . . . . . . . .
10-55
11. Postrouting Optimization
xviii
Postrouting Optimization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2
Performing Postrouting Optimization . . . . . . . . . . . . . . . . . . . . . . .
11-4
Optimization Histogram Reports . . . . . . . . . . . . . . . . . . . . . .
11-6
Inverter-Only Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-7
Using the Recommended Flow . . . . . . . . . . . . . . . . . . . . . . .
11-8
Using the Customized Postrouting Optimization Flow . . . . . .

Global Routing Optimization. . . . . . . . . . . . . . . . . . . . . . . .
Track Assignment Optimization . . . . . . . . . . . . . . . . . . . . .
Detail Routing Optimization . . . . . . . . . . . . . . . . . . . . . . . .
11-11
11-13
11-14
11-14
Optimizing Power After Detail Routing . . . . . . . . . . . . . . . . . . . . . 11-15

Filler Cell, Power, Ground, and Standard Cell
Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Using Alternative Postrouting Optimization Commands . . . . . . . . 11-18
Routing Optimization After Global Routing . . . . . . . . . . . . . .
11-19
Routing Optimization After Detail Routing . . . . . . . . . . . . . . . 11-21

Using axgAdvRouteOpt . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Using astPostRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
12. Design Finishing and Interactive Changes
Optimizing Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-3
Using axDrouteOptimizeContact . . . . . . . . . . . . . . . . . . . . . .
12-6
Using axgOptimizeContact . . . . . . . . . . . . . . . . . . . . . . . . . .
12-7
Preventing Isolated Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

Performing Design Finishing Processes . . . . . . . . . . . . . . . . . . . . 12-11
Metal Density Filling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Defining Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Using axgFillWireTrack . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Wide Metal Slotting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-14
Optimizing Yield. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

Performing Wire Spreading . . . . . . . . . . . . . . . . . . . . . . . . . .
12-16
Reporting Critical Areas and Displaying Heat Maps . . . . . . .
12-17
Interactively Cleaning Up Routing DRC Errors . . . . . . . . . . . . . . . 12-20

Engineering Change Order Methods. . . . . . . . . . . . . . . . . . . . . . . 12-22
xix
Maintaining Hierarchy Preservation Information During

ECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
Using the ECO-by-Change-File Method. . . . . . . . . . . . . . . 12-23
Using the ECO-by-Net-Compare Method. . . . . . . . . . . . . . 12-24
Using Edit-In-Place . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
Working With Astro Interactive Ultra . . . . . . . . . . . . . . . . . . . . . . . 12-28
Point-to-Point Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-29
Using the Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-31
13. Verification and Back-Annotation

Performing Design Rule Checking and Connectivity
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-2
Design Rule Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Design Rule Checking for Advanced
Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Basic Design Rule Checking . . . . . . . . . . . . . . . .
Running Design Rule Checking and Verification . . . . . . . .
13-2
Connectivity Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-7
Using the Error Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-9
13-3
13-5
13-6
Generating Output for Back-Annotation . . . . . . . . . . . . . . . . . . . . 13-13

Creating Parasitic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-13
Creating Timing Views (Models) . . . . . . . . . . . . . . . . . . . . . .
13-15
Other Output After Completion . . . . . . . . . . . . . . . . . . . . . . .
13-17
14. Antenna Checking and Fixing

Antenna Checking and Fixing Flow . . . . . . . . . . . . . . . . . . . . . . . .
xx
14-3
Preparing Antenna Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-5
Cell Library Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-6
Top Design Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-6
Hierarchical Antenna Data . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-7
Diode Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-8
Technology File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-8
Inserting Diodes on Prerouted Nets . . . . . . . . . . . . . . . . . . . . . . .
14-9
Checking and Fixing Antennas During Search-and-Repair. . . . . . 14-10

Checking and Fixing Floating Wire Antennas . . . . . . . . . . . .
14-11
Setting the Antenna Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-13
Inserting Diodes to Fix Remaining Violations . . . . . . . . . . . . . . . . 14-15

Deleting Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Reporting Antenna Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Importing Hercules Antenna Reports . . . . . . . . . . . . . . . . . . . . . . 14-18
15. Signal Integrity: Crosstalk Prevention,
Analysis, and Fixing
Crosstalk Features and Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-2
Preventing Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-6
Using astAutoPlace to Prevent Crosstalk . . . . . . . . . . . . . . .
15-7
Using astPostPS1 to Prevent Crosstalk . . . . . . . . . . . . . . . . .
15-10
Crosstalk Prevention During Global Routing and Track

Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Track Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
xxi
Using Shielding to Prevent Crosstalk. . . . . . . . . . . . . . . . . . .
15-13
Analyzing Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13

Preparing to Analyze Crosstalk . . . . . . . . . . . . . . . . . . . . . . .
Generating a PARA View (Optional). . . . . . . . . . . . . . . . . .
Setting Timing Setup Options. . . . . . . . . . . . . . . . . . . . . . .
Excluding Nets From Crosstalk Analysis . . . . . . . . . . . . . .
Specifying Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . .
15-13
15-13
15-14
15-17
15-18
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-19
Input From CLF Files and Noise Libraries . . . . . . . . . . . . . . .

CLF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Noise Information From Reference
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Noise Immunity Characteristics With Tcl
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Noise Constraints . . . . . . . . . . . . . . . . . . . . . . .
15-19
15-20
15-20
Running Crosstalk Analysis . . . . . . . . . . . . . . . . . . . . . . . . . .

Analyzing Crosstalk With the Low-Effort Crosstalk
Circuit Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyzing Crosstalk With the Medium-Effort Crosstalk
Circuit Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using xtXTalkAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Analysis Statistics . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Analysis Reports . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-25
15-26
15-27
15-30
15-31
Generating Detailed Crosstalk Reports . . . . . . . . . . . . . . . . .
15-36
Displaying Crosstalk Analysis Results . . . . . . . . . . . . . . . . . .
15-43
15-22
15-23
15-24
15-24
15-25
Generating Stage Delay Reports . . . . . . . . . . . . . . . . . . . . . . 15-44

Sample Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45
xxii
Generating Delta Transition Delay Reports . . . . . . . . . . . . . . 15-45

Sample Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-46
Analyzing Crosstalk-Induced Delay Shift . . . . . . . . . . . . . . . . 15-47
Generating a Timing Report That Considers Crosstalk . . . 15-48
Generating a Crosstalk-Induced Standard Delay Format
File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50
Fixing Crosstalk Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52
Fixing Crosstalk With astPostRouteOpt . . . . . . . . . . . . . . . . .
15-53
Fixing Crosstalk With axgAdvRouteOpt. . . . . . . . . . . . . . . . .
15-56
Using Spacing and Isolation Constraints to Fix

Crosstalk Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-58
Fixing Crosstalk With astXTalkFix . . . . . . . . . . . . . . . . . . . . .
15-60
Calculating Noise During Routing . . . . . . . . . . . . . . . . . . . . .
15-62
Performing Crosstalk Optimization During Search and

Repair Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-62
Additional Information About Crosstalk Circuit Models . . . . . . . . . 15-63

Low-Effort Crosstalk Circuit Model. . . . . . . . . . . . . . . . . . . . .
15-64
Medium-Effort Crosstalk Circuit Model . . . . . . . . . . . . . . . . .
15-66
16. Signal Integrity: Signal and Cell Electromigration

About Signal and Cell Electromigration Analysis. . . . . . . . . . . . . .
16-3
Preparing Data for Signal Electromigration Analysis. . . . . . . . . . .
16-4
Defining Current Units in the Technology File . . . . . . . . . . . .
16-4
Loading Signal Electromigration Constraints . . . . . . . . . . . . .
16-4
Loading the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-7
Loading Net Switching Information . . . . . . . . . . . . . . . . . . . .
16-8
xxiii
Performing Signal Electromigration Analysis. . . . . . . . . . . . . . . . . 16-13

Signal Electromigration Analysis Report . . . . . . . . . . . . . . . .
16-17
Definitions of Average, Absolute Average, Root Mean

Square, and Peak Currents . . . . . . . . . . . . . . . . . . . . . . .
16-20
Repairing Electromigration Violations . . . . . . . . . . . . . . . . . . . . . . 16-23

Verifying Electromigration Analysis Results . . . . . . . . . . . . . . . . . 16-24
Interpreting the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-26
Performing Cell Electromigration Analysis. . . . . . . . . . . . . . . . . . . 16-28

Examples of Signal Electromigration Constraints
Processed in ALF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30
Sample Constraints for Metal Layers . . . . . . . . . . . . . . . . . . .
16-30
Sample Constraints for Via Layers. . . . . . . . . . . . . . . . . . . . .
16-36
Examples of Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37

Sample Script for Running Signal Electromigration
Analysis and Fixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-37

Analysis and Prevention . . . . . . . . . . . . . . . . . . . . . . . . . .
16-39
Appendix A.
Astro Design Flow
Appendix B.
Scan Chains
Scan Chain Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxiv
B-2
Netlist-Defined Scan Chain Optimization Flow . . . . . . . . . . .
B-2
User-Defined Scan Chain Optimization Flow. . . . . . . . . . . . .
B-5
Setting Scan Input and Output Ports . . . . . . . . . . . . . . . . . . . . . . .
B-7
Creating Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-7
Creating Scan Chains by Tracing the Netlist . . . . . . . . . . . . .
B-7
Creating Scan Chains Manually. . . . . . . . . . . . . . . . . . . . . . .
B-9
Detaching Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-9
Creating and Applying Constraints . . . . . . . . . . . . . . . . . . . . . . . .
B-10
Writing Out the Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . .
B-11
Creating the Constraints File . . . . . . . . . . . . . . . . . . . . . . . . .

Delete the Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create an Empty Scan Chain. . . . . . . . . . . . . . . . . . . . . . .
Add a Scan Chain Group . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Default Group Priority . . . . . . . . . . . . . . . . . . . . . . . . .
Add Free Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Add Fixed Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-13
B-14
B-14
B-15
B-15
B-16
B-16
B-16
Applying the Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-19
Creating Global Control Nets . . . . . . . . . . . . . . . . . . . . . . . . .
B-19
Optimizing Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-19
Tracing Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-21
Writing Out New Scan Chain Information . . . . . . . . . . . . . . . . . . .
B-21
Appendix C.
Routing Design Rules
Minimum Length Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-3
Minimum Edge Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-3
Minimum Edge Length Rule. . . . . . . . . . . . . . . . . . . . . . . . . .
C-6
Total Minimum Edge Length Rule . . . . . . . . . . . . . . . . . . . . .
C-6
Special Notch Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-7
xxv
Combined Minimum Edge and Special Notch Rule . . . . . . . .

Via Corner Spacing Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-9
U-Shape Spacing Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-10
Minimum Enclosed Area Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-11
Minimum Enclosed Width Rule . . . . . . . . . . . . . . . . . . . . . . .
xxvi
C-8
C-12
Fat Poly Contact Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-12
Fat Contact Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-13
One-Dimensional Table Rule . . . . . . . . . . . . . . . . . . . . . . . . .
C-13
Two-Dimensional Table Rule . . . . . . . . . . . . . . . . . . . . . . . . .
C-14
Merging Pins With Abutting Obstruction Rule . . . . . . . . . . . . . . . .
C-16
Special End-of-Line Spacing Rules . . . . . . . . . . . . . . . . . . . . . . . .
C-16
End-of-Line Spacing Rule . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-17
Dense End-of-Line Spacing Rule. . . . . . . . . . . . . . . . . . . . . .
C-17
L-Shaped End-of-Line Spacing Rule . . . . . . . . . . . . . . . . . . .
C-19
Enclosed Via Spacing Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-20
Metal Density Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-21
Metal Density Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-21
Metal Density Gradient Rule . . . . . . . . . . . . . . . . . . . . . . . . .
C-22
Via Array (Via Farm) Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-23
Same Net Minimum Spacing Rule. . . . . . . . . . . . . . . . . . . . . . . . .
C-23
Dog Bone Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-24
Protrusion Length Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-25
Via Array Maximum Stack Level Rule . . . . . . . . . . . . . . . . . . . . . .
C-27
Neighboring Layer Fat Extension Range Spacing Rule . . . . . . . .
C-28
Parallel Length Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-30
Jog Wire Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-31
Small Jog Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-31
Jog Wire End-of-Line Via Rule. . . . . . . . . . . . . . . . . . . . . . . .
C-33
Jog Wire Via Keepout Region Rule . . . . . . . . . . . . . . . . . . . .
C-33
Fat Wire Via Keepout Region Rule . . . . . . . . . . . . . . . . . . . . . . . .

Appendix D.
C-33
Astro Parameters
Using Parameters and Getting Information . . . . . . . . . . . . . . . . . .
D-2
Clock Tree Synthesis Parameters . . . . . . . . . . . . . . . . . . . . . . . . .
D-5
Clock Tree Synthesis General Behavior Parameters . . . . . . .

best condition, typical condition, worst condition . . . . . . . .
cto: buffer sizing
cto: buffer relocation
cto: cell sizing
cto: cell relocation
cto: level adjustment
cto: delay insertion
cto: dummy load insertion
cto: reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
delay insertion before gate . . . . . . . . . . . . . . . . . . . . . . . . .
gated clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
move clock gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
size up clock gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-6
D-6
D-8
D-10
D-11
D-11
D-12
Clock Tree Synthesis Legalization Controlling

Placement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECO placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-13
D-13
xxvii
xxviii
ECO weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
legalize placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set OV maximum displacement . . . . . . . . . . . . . . . . . . . . .
D-14
D-15
D-15
D-16
Clock Tree Synthesis Effort Related Parameters . . . . . . . . . .

clustering effort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reclustering iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
synthesis effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-17
D-17
D-18
D-19
Clock Tree Synthesis Clock Constraint Targets Parameters .

target: best transition delay fall. . . . . . . . . . . . . . . . . . . . . .
target: best transition delay rise . . . . . . . . . . . . . . . . . . . . .
target: clock insertion delay . . . . . . . . . . . . . . . . . . . . . . . .
target: clock skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
target: load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . .
target fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
target load relax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
target: transition delay fall. . . . . . . . . . . . . . . . . . . . . . . . . .
target: transition delay rise . . . . . . . . . . . . . . . . . . . . . . . . .
target: worst transition delay fall . . . . . . . . . . . . . . . . . . . . .
target: worst transition delay rise . . . . . . . . . . . . . . . . . . . .
D-20
D-21
D-21
D-22
D-23
D-24
D-24
D-25
D-25
D-26
D-27
D-28
Clock Tree Synthesis Clock Constraint Rules Parameters. . .

rule: maximum capacitance . . . . . . . . . . . . . . . . . . . . . . . .
rule: maximum insertion delay . . . . . . . . . . . . . . . . . . . . . .
rule: maximum skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
rule: maximum transition delay fall . . . . . . . . . . . . . . . . . . .
rule: maximum transition delay rise . . . . . . . . . . . . . . . . . .
rule: maximum wire length . . . . . . . . . . . . . . . . . . . . . . . . .
rule: minimum insertion delay. . . . . . . . . . . . . . . . . . . . . . .
rule: minimum transition delay fall . . . . . . . . . . . . . . . . . . .
D-29
D-30
D-30
D-31
D-32
D-32
D-33
D-34
D-34
rule: minimum transition delay rise. . . . . . . . . . . . . . . . . . .

rule maximum buffer levels. . . . . . . . . . . . . . . . . . . . . . . . .
rule maximum fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-35
D-35
D-36
Clock Optimization Parameters . . . . . . . . . . . . . . . . . . . . . . .

cto: FF relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
cto: FF sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
cto: latch relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
cto: latch sizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
optimization level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-37
D-37
D-38
D-38
D-39
D-39
Clock Routing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .

ECO Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set default route rule on bottom level . . . . . . . . . . . . . . . . .
set default route rule on leaf net. . . . . . . . . . . . . . . . . . . . .
D-40
D-40
D-41
D-41
Standalone Clock Optimization Parameters . . . . . . . . . . . . .

delay balance: clock skew offset . . . . . . . . . . . . . . . . . . . .
delay balance: insertion delay offset . . . . . . . . . . . . . . . . .
fix load cap violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
fix transition violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
minimize placement changes . . . . . . . . . . . . . . . . . . . . . . .
minimize placement changes effort . . . . . . . . . . . . . . . . . .
D-42
D-42
D-43
D-43
D-44
D-44
D-45
Other Clock Tree Synthesis Parameters . . . . . . . . . . . . . . . .

clock tree root minimum fanout . . . . . . . . . . . . . . . . . . . . .
CTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
explore clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
fix ignore pins violations . . . . . . . . . . . . . . . . . . . . . . . . . . .
leaf net transition constraint . . . . . . . . . . . . . . . . . . . . . . . .
length fixed buffer insertion on top . . . . . . . . . . . . . . . . . . .
logic level balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
number of hookup pins per cluster . . . . . . . . . . . . . . . . . . .
D-46
D-47
D-47
D-48
D-49
D-49
D-50
D-50
D-51
xxix
xxx
real clock useful skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

skew type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
update congestion map . . . . . . . . . . . . . . . . . . . . . . . . . . .
use global route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
wire capacitance accuracy . . . . . . . . . . . . . . . . . . . . . . . . .
D-51
D-52
D-52
D-53
D-54
Changing Standard Naming Convention Parameters . . . . . .

bottom level buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
buffer instance prefix name . . . . . . . . . . . . . . . . . . . . . . . .
configuration output file . . . . . . . . . . . . . . . . . . . . . . . . . . .
file name: buffer instances . . . . . . . . . . . . . . . . . . . . . . . . .
file name: clock tree timing. . . . . . . . . . . . . . . . . . . . . . . . .
file name: cluster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
file name: FF relationship . . . . . . . . . . . . . . . . . . . . . . . . . .
file name: re-synthesis nets . . . . . . . . . . . . . . . . . . . . . . . .
file name: synthesized clock tree . . . . . . . . . . . . . . . . . . . .
file name: synthesized nets . . . . . . . . . . . . . . . . . . . . . . . .
net prefix name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-55
D-56
D-56
D-57
D-57
D-58
D-58
D-59
D-59
D-60
D-60
D-61
Changing Default Interpretation of Clock Constraints

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ignore library constraints . . . . . . . . . . . . . . . . . . . . . . . . . .
ignore library maximum capacitance . . . . . . . . . . . . . . . . .
ignore library maximum fanout . . . . . . . . . . . . . . . . . . . . . .
ignore library maximum transition . . . . . . . . . . . . . . . . . . .
ignore SDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ignore SDC maximum capacitance . . . . . . . . . . . . . . . . . .
ignore SDC maximum fanout . . . . . . . . . . . . . . . . . . . . . . .
ignore SDC maximum transition. . . . . . . . . . . . . . . . . . . . .
ignore set_clock_latency . . . . . . . . . . . . . . . . . . . . . . . . . .
ignore set_clock_transition . . . . . . . . . . . . . . . . . . . . . . . . .
D-61
D-62
D-63
D-63
D-64
D-64
D-65
D-65
D-66
D-66
D-67
ignore set_clock_uncertainty . . . . . . . . . . . . . . . . . . . . . . .
D-68
Common Graph Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-69
CGHIER_ENABLE_FAST_REPAIR. . . . . . . . . . . . . . . . . . . .
D-70
cg_opt_context_flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-70
disable_escape_char . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-71
dont_touch_nets_connecting_ls_and_io . . . . . . . . . . . . . . . .
D-72
dont_use_means_dont_touch . . . . . . . . . . . . . . . . . . . . . . . .
D-72
enable_ibt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-72
enable_connection_class. . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-73
max_boolean_syntax_warnings . . . . . . . . . . . . . . . . . . . . . .
D-74
optimize_mix_signal_net . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-74
replace_backslash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-75
save_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-75
Crosstalk Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-76
xtDeltaDelayScale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-77
xtDeltaTransScale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-77
xtEnableRailToRailDeltaDelay . . . . . . . . . . . . . . . . . . . . . . . .
D-78
xtNoAdaptiveInMediumEffort . . . . . . . . . . . . . . . . . . . . . . . . .
D-79
xtNumOfTopAggr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-79
xtTimingWindowHighEffort. . . . . . . . . . . . . . . . . . . . . . . . . . .
D-80
xtUseAdaptiveDetailWvfmThresh . . . . . . . . . . . . . . . . . . . . .
D-81
xtUseNoiseWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-82
xtXtalkDetailWvfmThreshold . . . . . . . . . . . . . . . . . . . . . . . . .
D-83
Global Route Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

accessPolyPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-84
D-87
xxxi
xxxii
avoidCouplingUser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-88
avoidXtalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-89
blncdToSkewCntrlRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-89
blockEdgeAccess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-90
brokenNetsThresholdPercent . . . . . . . . . . . . . . . . . . . . . . . .
D-90
clockBalanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-91
clockComb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-92
combDistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-92
combMaxConnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-93
compactMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-93
congestionWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-94
densityDriven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-95
detourLimitMinNetLen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-96
extraCostsApplyPercent. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-96
extraWireLengthOpt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-97
forceUpperLayersForCritNets . . . . . . . . . . . . . . . . . . . . . . . .
D-97
horReserveTracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-98
ignoreViaBlockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-98
incremental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-99
macroBndryDir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-100
macroBndryExt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-100
macroBndryTrkUtil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-101
macroBndryWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-102
macroCornerTrkUtil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-102
mapOnly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-103
maxDetourPercent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-103
netCriticality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-104
noTopLevelBusFeedThroughs . . . . . . . . . . . . . . . . . . . . . . . .
D-105
paEqPinNetMaxPort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-105
powerDriven. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-106
rcOptByLength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-106
reportDemandOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-107
reportEffectiveOverflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-107
reportGCellDensity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-108
reportNetOrdering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-108
reserveTracksForPowerFile . . . . . . . . . . . . . . . . . . . . . . . . . .
D-109
skewControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-109
skewControlNetBBLowBound . . . . . . . . . . . . . . . . . . . . . . . .
D-110
skewControlWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-111
speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-111
timingDriven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-112
timingWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-113
turboMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-113
VABoundaryToLSWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-114
verReserveTracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-114
xtalkWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-115
PDS Optimization Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . D-116

aggOpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-118
buf_ins_hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-119
flag_cr_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-119
hfn_fanout_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-120
hfn_max_fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-120
xxxiii
max_iteration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-121
max_level_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-121
max_runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-122
max_utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-123
move_flip_flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-123
no_new_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-124
ov_max_displaced_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-124
ov_max_displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-125
pds_message_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-125
pr_use_fpclass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-126
slack_range_hold_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-126
slack_range_hold_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-127
slack_range_setup_max . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-127
slack_range_setup_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-128
target_hold_slack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-129
target_setup_slack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-129
target_utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-130
topo_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-130
use_child_router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-131
use_global_cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-132
wire_delay_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-133
xtalk_noise_limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-134
Rectilinear Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-134
xxxiv
allowMovePG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-136
controlparameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-136
core2Bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-137
core2Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-138
core2Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-138
core2Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-139
doubleBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-139
flipfirst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-140
forceTrackAlignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-140
lengthMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-141
macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-141
rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-142
rowDirction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-143
rowRatio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-143
rpinECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-144
startfirst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-144
stdcells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-145
utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-145
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-146

all_macro_as_VR_block . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-149
ata_crp_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-150
Equivalent PrimeTime Parameter. . . . . . . . . . . . . . . . . . . . D-150
ata_crpr_threshold_ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-150
capture_path_propagate_worst_slew . . . . . . . . . . . . . . . . . .
D-151
case_analysis_disable_entire_path . . . . . . . . . . . . . . . . . . . .
D-152
case_analysis_sequential_propagation . . . . . . . . . . . . . . . . . D-153
clock_cell_has_multiple_edge . . . . . . . . . . . . . . . . . . . . . . . .
D-154
xxxv
clock_gating_propagate_enable . . . . . . . . . . . . . . . . . . . . . . D-154
clock_tree_report_debug_mode . . . . . . . . . . . . . . . . . . . . . .
D-155
disable_cond_default_arcs . . . . . . . . . . . . . . . . . . . . . . . . . . D-156
driving_cell_include_cell_delay . . . . . . . . . . . . . . . . . . . . . . .
D-156
early_launch_at_borrowing_latches . . . . . . . . . . . . . . . . . . . D-157
group_path_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-159
max_RG_size_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-159
multicycle_hold_follow_setup. . . . . . . . . . . . . . . . . . . . . . . . .
D-160
non_unate_clock_compatibility . . . . . . . . . . . . . . . . . . . . . . . D-161
print_Clock_Timing_For_Mixed_Edges . . . . . . . . . . . . . . . . .
D-162
pulse_latch_as_ICG_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-162
rc_degrade_min_slew_when_rd_less_than_rnet . . . . . . . . . D-163
remove_Escape_From_Bus. . . . . . . . . . . . . . . . . . . . . . . . . .
D-164
report_timing_through_sync_pin . . . . . . . . . . . . . . . . . . . . . .
D-164
rpt_max_cap_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-165
rpt_max_tran_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-165
rpt_min_cap_multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-166
rpt_min_tran_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-167
splitEK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-167
Glossary
Index
xxxvi
Preface
FIX ME!
This preface includes the following sections:
Whats New in This Release
About This Guide
Customer Support
xxxvii
Whats New in This Release

Information about new features, enhancements, and changes;
known problems and limitations; and resolved Synopsys Technical
Action Requests (STARs) is available in the Astro Release Notes in
SolvNet.
To see the Astro Release Notes,
1. Go to http://solvnet.synopsys.com/ReleaseNotes. (If prompted,
enter your user name and password. If you do not have a
Synopsys user name and password, follow the instructions to
register with SolvNet.)
2. Click Astro, then click the release you want in the list that appears
at the bottom.
About This Guide

This user guide describes the Astro tool and its basic flow. Astro is
an advanced physical design system for optimization, placement,
and routing from Synopsys. It uses a specialized architecture that
concurrently accounts for physical effects while optimizing the
design. The Astro User Guide: Advanced Topics describes features
for Astro that are outside the scope of the basic flow.
Preface
xxxviii
Audience
This user guide is for design engineers who use Astro to implement
designs. To use Astro,
You need to have general knowledge of the Scheme

programming language or the tool command language (Tcl)
You need to be familiar with physical design principles
You must be familiar with the UNIX operation system
Using Swish-e With Physical Implementation Online

Help
The Swish-e program, which is provided for online Help, is not
Licensed Software or Licensed Product in your license
agreement with Synopsys. The Swish-e program is subject to the
license provisions found at http://swish-e.org, where you can also
find the source code for Swish-e.
Related Publications
For additional information about Astro, see
Synopsys Online Documentation (SOLD), which is included with

the software for CD users or is available to download through the
Synopsys Electronic Software Transfer (EST) system
Documentation on the Web, which is available through SolvNet

at http://solvnet.synopsys.com
The Synopsys MediaDocs Shop, from which you can order

printed copies of Synopsys documents, at
http://mediadocs.synopsys.com
About This Guide
xxxix
You might also want to refer to the documentation for Milkyway and
the following related Synopsys products:
Library Compiler
Design Compiler
IC Compiler
Physical Compiler
PrimeTime
Astro-Rail and PrimeRail
Astro Interactive Ultra
Star-RCXT
JupiterXT
See also Physical Implementation Online Help and the Astro User
Guide: Advanced Topics.
Preface
xl
Conventions
The following conventions are used in Synopsys documentation.
Convention
Description
Courier
Indicates command syntax.
Courier italic
Indicates a user-defined value in Synopsys

syntax, such as object_name. (A user-defined
value that is not Synopsys syntax, such as a
user-defined value in a Verilog or VHDL
statement, is indicated by regular text font
italic.)
Courier bold
Indicates user inputtext you type verbatim

in Synopsys syntax and examples. (User input
that is not Synopsys syntax, such as a user
name or password you enter in a GUI, is
indicated by regular text font bold.)
[]
Denotes optional parameters, such as

pin1 [pin2 ... pinN]
Indicates a choice among alternatives, such as

low | medium | high
(This example indicates that you can enter one

of three possible values for an option:
low, medium, or high.)
_
Connects terms that are read as a single term

by the system, such as
set_annotated_delay
Control-c
Indicates a keyboard combination, such as

holding down the Control key and pressing c.
Indicates a continuation of a command line.
Indicates levels of directory structure.
Edit > Copy
Indicates a path to a menu command, such as

opening the Edit menu and choosing Copy.
About This Guide

xli
Customer Support
Customer support is available through SolvNet online customer
support and through contacting the Synopsys Technical Support
Center.
Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles
and answers to frequently asked questions about Synopsys tools.
SolvNet also gives you access to a wide range of Synopsys online
services including software downloads, documentation on the Web,
and Enter a Call With the Support Center.
To access SolvNet,
1. Go to the SolvNet Web page at http://solvnet.synopsys.com.
2. If prompted, enter your user name and password. (If you do not
have a Synopsys user name and password, follow the
instructions to register with SolvNet.)
If you need help using SolvNet, click HELP in the top-right menu bar
or in the footer.
Preface
xlii
Contacting the Synopsys Technical Support Center

If you have problems, questions, or suggestions, you can contact the
Synopsys Technical Support Center in the following ways:
Open a call to your local support center from the Web by going to
http://solvnet.synopsys.com (Synopsys user name and
password required), then clicking Enter a Call With the Support
Center.
Send an e-mail message to your local support center.

- E-mail support_center@synopsys.com from within North
America.
- Find other local support center e-mail addresses at
http://www.synopsys.com/support/support_ctr.
Telephone your local support center.

- Call (800) 245-8005 from within the continental United States.
- Call (650) 584-4200 from Canada.
- Find other local support center telephone numbers at
http://www.synopsys.com/support/support_ctr.
Customer Support
xliii
Preface
xliv
1
Introduction to Astro
The Astro product is an advanced physical design system for

optimization, placement, and routing. Astro uses a specialized
architecture that concurrently accounts for physical effects while
optimizing the design.
Note:
Different companies might use different terminology for designs
and their components. If you encounter an unfamiliar word or
phrase, see the definitions in the Glossary at the back of this
manual.
This chapter includes the following sections:
Benefits of Using Astro
Astro Packages
Astro Licensing Requirements
1-1
Supported Platforms
Astro Place and Route Flow and Documentation Set
Chapter 1: Introduction to Astro

1-2

Using Astro provides these benefits:
Astro enables you to achieve rapid design convergenceits

architecture is designed for concurrent optimization.
Astro addresses ultradeep submicron (UDSM) effects during

design processes. Its unique technology eliminates iterations, by
concurrently accounting for all physical effects throughout the
design process.
Astro increases clock speeds and provides fast design

completion.
Astro improves productivity, by providing placement change

controls such as incremental overlap removal and incremental
placement. It also ensures the lowest possible clock skew with its
early timing capability and ability to predict congestion impact.
Astro reduces migration and translation issues. Because it is

based on the Milkyway common database, Astro provides direct
plug-and-play into the Synopsys timing closure solution. Design
data created with the previous generation of Synopsys place and
route tools is fully compatible with Astro.
Astro follows the latest, advanced manufacturing process rules,

thereby improving design reliability. It handles antenna repair, via
optimization, metal fill, and metal slotting automatically. Effects
such as conformal dielectrics, copper dishing, and shallow trench
isolation are incorporated into the Astro parasitic extraction
engine.
Astro shortens design cycles. Its new high-performance

algorithms and distributed routing capabilities enable you to get
designs out the door quickly.
1-3
Astro Packages
Synopsys provides a spectrum of Astro product packages, which
vary in complexity with the features offered. Each package in this
hierarchy (Figure 1-1) is a superset of the previous package, except
for Astro Multiroute, which can be added to any configuration.
Figure 1-1
Astro Product Packages

Astro-Xtalk
Astro-Rail
Astro
Multiroute
Astro Express Timing Closure

Astro Pro
Astro Ultradeep Submicron
Place and Route
Astro product packages include
Astro Basic Ultradeep Submicron (UDSM) Place & Route

capabilities include
- Design setup with Milkyway
- Macro and standard cell placement
- Scan chain optimization
- Clock tree synthesis
- Power and ground net prerouting
- Clock and signal net routing
- Engineering change order (ECO) routing

1-4
- Antenna analysis and fixing

- Built-in static timing analysis
- Built-in parasitic extraction
- TLUPlus extraction models
- Built-in DRC/LVS design verification
Astro Procapabilities include

- Timing-driven placement
- Timing-driven routing
- Automatic gated clock tree synthesis
Astro Express Timing Closurecapabilities include

- Clock tree optimization
- Interactive clock tree synthesis
- Clock tree browser
- Timing optimization
Astro-Xtalkcapabilities include
- Crosstalk analysis and optimization
- Static noise (glitch) analysis and optimization
- Signal electromigration analysis
Astro-Railcapabilities include
- Power analysis
- Rail analysis
Astro Packages
1-5
- Power grid electromigration analysis at transistor and gate

level
Astro Multiroutecapabilities include

- Distribution of the routing task over multiple CPUs
In addition, the Astro Interactive Ultra tool provides advanced

interactive routing and editing capabilities in an environment fully
integrated with Astro. For more information, see the Astro Interactive
Ultra User Guide.
Astro Licensing Requirements

You need an Astro license to run Astro. Each of the Astro products,
listed in Astro Packages on page 1-4, requires its own license
feature, such as Astro, AstroExp, AstroXtalk, and AstroRail.
Supported Platforms
Astro software runs on various UNIX platforms. For detailed
information about supported platforms, see the Supported Platforms
Guide at
http://www.synopsys.com/products/sw_platform.html

1-6

You use Astro in conjunction with other Synopsys toolssuch as
Physical Compiler, JupiterXT, PrimeTime, Star-RCXT, Astro
Interactive Ultra, Astro-Rail, and PrimeRailto implement advanced
physical design.
Table 1-1 shows an overview of the Astro design flow and the related
chapters in this document that describe the topics. Detailed flow
drawings appear in related chapters, and for a comprehensive,
detailed design flow, see Appendix A, Astro Design Flow.

1-7
Table 1-1
Overview of Astro Flow
Task
Related chapter in this document
Library setup and data in
Floorplanning
Chapter 5, Floorplanning and Connecting Power and

Ground
Timing setup and analysis
Chapter 6, Setting Up the Design Timing

Chapter 7, Analyzing Timing
Placement and placement

optimization
Chapter 8, Placement and Placement Optimizations
Clock tree synthesis

and optimization
Routing
Postrouting optimization

1-8
Chapter 3, Creating Milkyway Reference Libraries

Chapter 4, Creating a Design Library and Adding Data
Chapter 9, Clock Tree Synthesis and Clock Tree

Optimizations
Chapter 10, Routing
Chapter 11, Postrouting Optimization
Table 1-1
Overview of Astro Flow (Continued)
Task
Related chapter in this document
Design finishing and

interactive changes
Verification and
back-annotation
Other
Chapter 12, Design Finishing and Interactive Changes
Chapter 13, Verification and Back-Annotation
Chapter 14, Antenna Checking and Fixing

Chapter 15, Signal Integrity: Crosstalk Prevention,
Chapter 16, Signal Integrity: Signal and Cell
Electromigration
Astro Documentation Set

In addition to this Astro User Guide, the following documentation and
resources are provided in SOLD, Docs on the Web, and as PDF files
in the Astro installation in the Astro_path/help/pdf_books directory:
Astro User Guide: Advanced Topics, which contains

- Chapter 1, Design Investigation
- Chapter 2, On-Chip Variation and Clock Reconvergence
Pessimism Removal
- Chapter 3, Working With PrimeTime
- Chapter 4, Multi-VDD Design Support
- Chapter 5, Multivoltage Threshold Filler Cells
- Chapter 6, LM View and Delay Calculation

1-9
- Chapter 7, Multicorner and Multimode Analysis and

Optimization
- Chapter 8, Creating and Using HTV Models
- Appendix A, LM View Frequently Asked Questions
Physical Implementation online Help describes the Astro

Scheme commands (see Finding Commands in Scheme Mode
on page 2-13)
Tcl online Help and man pages describe the Astro Tcl commands
(see Finding Commands in Tcl Mode on page 2-15)
The Milkyway Environment Data Preparation User Guide

describes the Milkyway database and library preparation
commands.
The Milkyway Extension Language Reference Manual describes

Scheme and Tcl commands and how to use Tcl in the Milkyway
environment.
For information about accessing SOLD, Documentation on the Web,

and other customer support resources, see Customer Support on
page xlii.
Recommended Astro Script-Based Methodology

The recommended Astro script-based methodology is a sequence of
the physical implementation steps, starting with an existing floorplan,
that you can run with a command wrapper interface. The
methodology is a set of scripts that provide an automatic path for
successfully completing a physical implementation for most designs.
For detailed information, including how to set up the scripting
environment, make edits, and run the methodology, see the
Recommended Astro (Script-Based) Methodology User Guide.

1-10
Power and Reliability Analysis

The Astro-Rail tool provides static power and reliability analysis
capabilities that enable you to resolve power, voltage drop, and
electromigration problems at the cell level during the physical design
process. Astro-Rail can also be used in the sign-off analysis process.
The PrimeRail tool handles dynamic voltage drop and
electromigration violations at the cell and transistor level. Unlike
Astro-Rail, which analyzes the static reliability effects for the design,
PrimeRail is a full-chip solution for dynamic voltage drop and
electromigration analyses.
Astro-Rail
Astro-Rail is designed to be integrated with Astroyou can access
its features from the Power menu and you can make settings in the
Place Common Options dialog box (astPlaceOptions) when you
have the power performance license. Alternately, you can use
Astro-Rail as a stand-alone product, which requires its own license
package.
Astro-Rail provides the following capabilities:
Static power analysis
Power and ground network extraction
Static voltage drop and electromigration analysis at the cell level,

including maps and violation reports

1-11
PrimeRail
PrimeRail is built on the Synopsys sign-off technologies, including
the Star-RCXT, HSPICE, NanoSim and PrimeTime tools. It offers
gate-level and transistor-level static and dynamic voltage drop and
electromigration analysis with on-chip decoupling capacitance and
full-chip sign-off with package parasitics. The integration of
PrimeRail with the Galaxy design platform helps you achieve fast
design convergence and provides a predictable path to sign-off.
PrimeRail requires its own licensing package. PrimeRail is a
stand-alone product and is not accessible in Astro.
PrimeRail provides the following capabilities:
Automatic generation of current waveform power libraries and

intrinsic parasitics libraries, using HSPICE
Embedded power network extraction
Transistor-level dynamic voltage drop and electromigration

analysis
Dynamic macro model generation
Average-based (vector-free) and event-based (vector-based)

dynamic reliability analysis for full-chip analysis
Decoupling capacitance and package parasitic analysis for

full-chip analysis
Analysis of advanced low power design techniques:

Multivoltage
Power switches (MT-CMOS)

1-12
Flexible postanalysis features, including graphic voltage drop and

electromigration maps, waveform viewer, and violation reports
Tx-level signal electromigration analysis
For complete information about Astro-Rail and PrimeRail, see the

Astro-Rail User Guide and PrimeRail User Guide.
Design Flow
You can use Astro-Rail or PrimeRail at different points in the design
flow, after global routing is performed. When global routing is
completed, you can use Astro-Rail or PrimeRail to calculate total
power consumption and to check for voltage drop and
electromigration violations on a circuit. This capability enables you to
detect potential violations before you perform detailed placement
and routing and, therefore, significantly reduces turnaround time
later in the design cycle.
After the detailed routing is complete, use Astro-Rail or PrimeRail to
verify the reliability of your design for sign-off.
Figure 1-2 shows when to use Astro-Rail or PrimeRail in the design
flow.

1-13
Figure 1-2
Using Astro-Rail or PrimeRail in the Design Flow

Technology
file
LM view
Milkyway
database
Floorplanning
The LEF/DEF/GDSII flow
Placement
LEF, DEF, and

GDSII data
Global routing
Conversion
reliability
analysis
Milkyway
database
LM view
Detailed routing
reliability
analysis

1-14
2
Using the Astro GUI and Command Files 2
The Astro graphical user interface (GUI) lets you run Scheme and
Tcl commands as well as view and analyze your design by using a
series of windows. You can also create and replay Scheme and Tcl
command files.
This chapter contains the following sections:
User Interfaces
Scheme and Tool Command Language (Tcl)
Starting an Astro Session
Interrupting or Terminating a Job
Using Menu Commands
Using the Command Window
Getting Help
2-1
Opening and Creating Libraries and Cells
Working With Layout Windows
Creating and Running Command Files
Exiting an Astro Session
Defining and Using Stroke Command Sequences
Using Integer and Real Parameters for Astro Operations
Chapter 2: Using the Astro GUI and Command Files

2-2
User Interfaces
The Astro GUI includes a command window as well as graphical
layout windows that provide views of a cell (a representation of a
design).
When you start an Astro session, the Astro command window that
appears provides menu commands and a command-line interface
(Scheme shell or Tcl shell). Every menu command has an underlying
Scheme or Tcl function. When you select a command from the
menu, the command either runs immediately or displays a dialog
box.
When you open a cell (you must first open the library containing the
cell), the tool creates and opens a graphical layout window
containing the cell. The graphical layout window provides a view of
the cell and several tools and commands for easy access and use.
You can open multiple graphical layout windows, each containing a
different cell or different views of the same cell.
Scheme and Tool Command Language (Tcl)

Astro supports Scheme, which is a high-level programming
language that provides an extensive set of data types and flexible
control structures to be used as an interface for Astro. Scheme
supports operations on the following types of data: strings, lists or
vectors of objects, vectors, numbers, and characters. You can use
Scheme for writing scripts.
Astro also supports the tool command language (Tcl), which is used
in most Synopsys tools, including Physical Compiler and PrimeTime,
and in many tools in the EDA industry. Astro support of Tcl for timing
User Interfaces
2-3
constraints is similar to PrimeTime and other Synopsys Tcl

commands. This support includes the collections mechanism that
was implemented using the same command interpreter as the other
Synopsys tools. For more details, see the information in the
PrimeTime User Guide: Advanced Timing Analysis. You can use Tcl
to extend the Astro command language by writing reusable
procedures and scripts. For more information, see the Milkyway
Environment Extension Language Reference Manual and the Using
Tcl With Synopsys Tools manual.
When presenting command syntax and examples, this user guide
mostly shows Scheme commands. Where Tcl commands are
shown, the command syntax is denoted as Tcl.

To facilitate opening libraries, start the Astro tool in the directory
containing your design library.
To start an Astro session,
Open the Astro window.

- To run Astro in Scheme mode, at the system prompt enter
% Astro &
The Astro window appears and starts in Scheme mode, as

shown in Figure 2-1.
The menu commands invoke Scheme functions, and Astro
creates a replay file named Astro.cmd.mo_dd_hh_mm that
records the commands you use. The commands being
recorded are displayed in the Command History window.

2-4
Figure 2-1
Astro Window in Scheme Mode

Menu bar
Prompt area
Title bar
Command window
Command History window
- To run Astro in Tcl mode, at the system prompt enter

% Astro -tcl &
The Astro window appears and starts in Tcl mode, as shown in

Figure 2-2.
The menu commands invoke Tcl functions, and Astro creates
a replay file named Astro.tcl.mo_dd_hh_mm that records the
commands you use. The commands being recorded are
displayed in the Tcl History window.

2-5
Figure 2-2
Astro Window in Tcl Mode

Menu bar
Prompt area
Title bar
Command window
Tcl History window
Note:
When you run Astro in Scheme mode, the command log file
starts with ;# Scheme. When you run Astro in Tcl mode, the
command log file starts with ;#Tcl. This allows you to write a
smart load command where you identify the file type (Scheme
or Tcl) and use one command to process either Scheme or Tcl
files.
The Astro window contains the areas described in Table 2-1.

2-6
Table 2-1
Astro Window Areas
Area
Description
Title bar
Shows the name of the tool window and the directory

from which you started Astro.
Menu bar
Provides access to the tools main menus.
Prompt area
Displays Scheme or Tcl commands that correspond to

the menu commands you select and prompts you to
select objects or specify points required for command
execution.
Command
window
Area for entering Scheme or Tcl commands. To repeat

a previous command, double-click the command in the
Command History window and middle-click at the
cursor. The command appears. Alternatively, you can
press the Up Arrow key to enter the previous commands
listed in the Command History window.
This area also displays system messages and records
all commands executed and points entered. You can
use the scroll bars to examine the history of your current
session.
Command History
or Tcl History
Displays the Scheme or Tcl commands you have used

during your Astro session and records all commands
executed and points entered.
You can change the scripting or tool language setting while you are
in an Astro session.
To change from Scheme mode to Tcl mode,

Enter begin_tcl in the command window or click the Tcl button
to the left of the prompt area.

2-7
The prompt in the command window changes to Astro>, and the

cursor blinks to show that the Tcl shell is ready to accept
command input.
To change from Tcl mode to Scheme mode,

Enter begin_scheme in the command window or click the
Scheme button to the left of the prompt area.
The cursor blinks to show that the Scheme shell is ready to
accept command input.
Using Startup Options

When you start an Astro session, you can specify various startup
options with the Astro command. The -help option displays
information about the options you can use for starting Astro from the
system window. At the system prompt, enter
% Astro -help
The following information is displayed:

Usage:
Astro [-tcl] [-log <filename>] [-logd <name>] [-cmd <filename>]

[-cmdd <name>] [-load <scm_file>] [-replay <scm_file>]
[-file <tcl_file>] [-iconic] [-nullDisplay] [-nogui] [-msmc]
[-caseSensitive] [-trueColor] [-version] [-release <key...>]
[-buffer] [-astroiu] [-freeAllOptionKeys] [-galaxy]
[-x <command>] [-no_init] [-environ <var=value,var2=value2,etc>]
[-help]
Options/Arguments:
-tcl
startup in tcl mode
-log <filename>
name of the log file
-logd <name>
use <name>.log.mm_dd_hh_mm as log file
-cmd <filename>
name of the command log file
-cmdd <name>
use <name>.cmd.mm_dd_hh_mm as command log file
-load <scm_file>
load and run a command file (no command echo)
-replay <scm_file> replay a command log file (after load)
-file <tcl_file>
Tcl script file to exec after setup
-iconic
display window as an icon

2-8
-nullDisplay
display to an Null X Server
-nogui
do not show gui windows and use text-shell initially
-msmc
enable distributed Multiple Scenario (msmc) commands
-caseSensitive
set process in case sensitive mode
-trueColor
select visual type
-version
display version information
-release <key...>
release license keys
-buffer
use double buffering
-astroiu
astro iu licensing
-freeAllOptionKeys release all optional license keys
-galaxy
set Galaxy mode
-x <command>
Execute a Tcl command after setup
-no_init
don't load user Tcl initialization files (optional)
-environ <var=value,var2=value2,etc> specify shell variable environment
settings (optional)
-help
display this information
The -buffer option affects the way objects are drawn in the overlay
planeit provides a smooth object-dragging appearance. In
buffering mode, the wire is drawn in an internal pixmap and then
copied to the window; in no buffering mode, the wire is drawn directly
to the window.

If you enter the wrong options for a command or enter the wrong
command, you can interrupt command processing and remain in the
tool. To interrupt or terminate a job, press Control-c.
The time the command takes to respond to an interrupt (to stop what
it is doing and return to the prompt) depends on the size of the
design and the function of the command being interrupted.

2-9
Using Menu Commands

When you select a menu from the menu bar of the Astro window,
Astro displays the commands on that menu. When you choose a
command from the menu, the command either runs immediately or
displays a dialog box. An ellipsis (...) indicates that the command
displays a dialog box, as shown in the Library menu in Figure 2-3. An
exclamation point (!) indicates that the command runs immediately.
If there is no ellipsis (...) or exclamation point (!), you need to select
an object or point on which the command can operate.
Figure 2-3
Astro Library Menu
The Tools Menu

The Tools menu (Figure 2-4) lets you change from the Astro menus
to those of another tool, such as the Milkyway Data Prep menus.

2-10
Figure 2-4
Astro Tools Menu
Choose Tools > Data Prep to replace the Astro menus with the Data
Prep menus. The menu bar changes, as shown in Figure 2-5.
Figure 2-5
Data Prep Menus
To change back to the Astro menus, choose Tools > Astro. The menu
bar changes, as shown in Figure 2-6.
Figure 2-6
Astro Menus
The Tools, Library, Cell, Options, Views, Create, Modify, Select,

Query, Timing, and Verify menus are the same in the Astro and Data
Prep menus. Notice that the Data Prep menus have unique menus
such as Cell Library and Wire Tracks that are not available in the
Astro menu, and the Astro menus have many menus such as
PreRoute, PrePlace, and Route Utility that are not available in the
Data Prep menus.
Using Menu Commands

2-11
Detaching Menus
You can detach a menu so you can access frequently used
commands by clicking the dashed line, as shown in Figure 2-3.
Figure 2-7 shows the detached Library menu.
Figure 2-7
Detached Library Menu
All detached menus are closed when you change to a different tool,
for example, by choosing Tools > Astro when you are using the Data
Prep menus.
Types of Commands
The physical implementation commands come in several types:
Global commands operate on the entire design. They require no

object or point selection and terminate after execution.
Point commands operate on specified objects or points in the

design. They require you to select an object or point, and they
remain available for you to reuse after execution.

2-12
Viewing commands operate on the layout window. These are the

only type of commands you can use during execution of another
command. For example, you can use a viewing command to
zoom in to the layout window while you are selecting points for a
point command.
Options commands operate in the Astro environment. They let

you select options that control how Astro operates.

In addition to using menus in the Astro GUI, you can enter
commands in the command window. For example, to open a library,
you can enter geOpenLib in the command window or choose
Library > Open from the menu.
Finding Commands in Scheme Mode

In Scheme mode, you use the functions command to display a list
of all commands or a subset of commands in the command window.
To list all Scheme commands, use the functions command with
no options. In the command window, enter
functions
To list a subset of Scheme commands, use the functions

command with a string pattern. The syntax is
functions "pattern"

2-13
Commands with the pattern (characters specified between the

quotation marks) appearing anywhere in its name are listed. For
example, to list all commands having the character string cell in
them, enter
functions "cell"
This lists all commands that contain the character string, regardless
of case or location in the command name.
Within the string, you can use the special characters listed in
Table 2-2 to be more specific about the command name.
Table 2-2
Special Characters for functions String
Character
Representation
Wildcard representing any number of any

character
Start of the command name
End of the command name
[]
Regular expressions, such as [C, L] or [C-L]
You can use the Tab key for command name completion. For
example, if you enter the following command and then press the Tab
key:
atTim
the command atTimingSetup is completed. To execute the

command, press the Enter key.

2-14
To display a list of all command names that complete an entry, enter

the first part of the command name and press Control-d. For
example, if you enter the following partial command name:
atTim
and press Control-d, the atTimingProbe, atTimingProbeHide,

atTimingSetupGoto, atTimingProbeGoto, atTimingSetup,
and atTimingSetupHide commands are listed.
Finding Commands in Tcl Mode

In Tcl mode, you use the help command to display a list of all
commands or a subset of commands, including those grouped by
category, in the command window.
To list all Tcl commands, use the help command with no options. In
the command window, enter
Astro> help
To list a subset of Tcl commands, use the help command with a

category name (see Figure 2-8) or a string pattern. Tcl command
arguments do not need to be enclosed in quotation marks. For
example,
Astro>
Astro>
Astro>
Astro>
Astro>
Astro>
help
help
help
help
help
help
milkyway
cts
router
timing
core_selection
get*

2-15
Figure 2-8
Listing Commands in Tcl Mode
For more information about using Tcl, see Using Tcl in the Milkyway
Environment in Physical Implementation Online Help and the Using
Tcl With Synopsys Tools manual.
Determining License Availability

To list the licenses available in the current Astro session, in the
command window enter
listFeature
To list all Astro commands and the license required, in the command
window enter
getFunctionLicensing

2-16
Working With and Without the GUI

When you are running with scripts or developing scripts, you might
want to run Astro without the GUI. To start Astro without the GUI, at
the system prompt enter
% Astro -nogui
Enter Astro commands on the shell command line.

To start the GUI when you are running Astro without the GUI, at the
system prompt enter
% start_gui
To leave the GUI and return to running Astro without the GUI, at the
system prompt enter
% stop_gui
Getting Help
Astro provides a comprehensive online documentation system, as
well as an online command help facility, and provides man pages for
selected Tcl commands.
Online Documentation System

The online Help commands are in Hypertext Markup Language
(HTML) format and can be viewed with a Web browser. You can
specify a browser by using the setHelpBrowser command.
Getting Help
2-17
The syntax is
setHelpBroswer "browser_name"
The following Web browsers are supported: Netscape Navigator,

Mozilla, Firefox, Opera, and Internet Explorer. For example, to
specify the use of the Mozilla browser, enter the following in the
command window:
setHelpBroswer "mozilla"
The online manuals are provided in Portable Document Format

(PDF). These files are located in the <astro_path>/help/pdf_books
directory. You can also click the PDF Documentation link at the
bottom of a Help page to view and print the PDF versions of the
manuals.
Using the Web Browser

To view online Help in a Web browser,
1. Click the Help button in any dialog box (in both Scheme and Tcl
mode).
Alternatively, in Scheme mode, you can use the help command
to view a command topic in the browser. The syntax is
help "command_name"
For example, to display the axgAutoRoute command topic,

enter the following in the command window:
help "axgAutoRoute"

2-18
For information about the online command help facility available

in Tcl mode that displays help in the command window, see
Displaying Help in Tcl Mode on page 2-21.
The Web browser appears. (In this example, the axgAutoRoute
command topic is displayed in the Mozilla browser.)
2. In the toolbar, you can click Back and Forward to see Help topics
in your browsing history.
Getting Help
2-19
3. In the navigation frame, you can

- Click the Contents tab to display the top-level table of contents
for the Help system.
- Click the Index tab to display the index for the Help system.
- Click the Search tab to search for text that you enter in the text
box. When you click Go, the search returns a list of topics that
contain the search term.
4. In the topic frame, you can
- Click the show topic in table of contents button to highlight the
current topic in the Table of Contents at the left.
- Click the previous page button (<) to display the previous
page, moving towards the first page in Help.
- Click the next page button (>) to display the next page,
moving towards the last page in Help.
- Click the show navigation button to open the navigation frame
on the left side of the window. This button appears when only
the topic frame is visible.
- Click the feedback e-mail button to open the mail tool in your
windowing system; lets you write a message to Synopsys
Customer Support.
- Click the print button to print the current topic.
For more information about using the Web browser and viewing Help
topics, including detailed information about the search tool, click the
Help QuickStart link at the bottom of each Help page.

2-20
To exit the standard browser
Choose File > Close.

Note:
You can exit Astro without exiting the Web browser.
Displaying Help in Tcl Mode

In Tcl mode, you can use the command help facility to display Help
in the command window.
To get help for specific commands,
Use the help command and specify the command name or enter
the specific command with the -help option
Both approaches are shown in Figure 2-9.
Figure 2-9
Tcl Command Help
Getting Help
2-21
Tcl Man Pages

The man pages provide detailed information about the Tcl
commands supported by Astro and other Synopsys physical
implementation tools, including syntax, arguments, description, and
examples.

To open a cell, you must first open the library containing the cell or
the library in which you want to place the new cell. For information
about creating a library, see the Milkyway Environment Data
Preparation User Guide.
Opening an Existing Library

You can have only one library open at a time.
To open an existing library,
Enter geOpenLib, open_mw_lib, or choose Library > Open.

The Open Library dialog box appears.

2-22
Opening an Existing Cell

To open an existing cell,
1. Enter geOpenCell, open_design, or choose Cell > Open.
The Open Cell dialog box appears.
2. If you want to look at the cell but not edit it, select read only.
This ensures that Astro does not save the cell.
3. Specify a cell name. Do one of the following:
- Next to Cell Name, enter the cell name.
The cell name is the name of the cell you want to open. Enter
top to open a layout cell in the sample library.
- Click Browse to browse the cells in the current library.
The Browse Cell dialog box appears.

2-23
4. Select the options.

- Next to Sort cells by, select alphabet or size.
- Next to List:, select all views to show all views of all cells in
the selected library, as shown in the next figure.

2-24
- Next to List:, select all versions to show all version of all cells
in the selected library, as shown in the next figure.

2-25
Then select the cell from the list of cells.

You can also select a reference library for the currently open
library by double-clicking the library name.
5. Click OK.
Astro displays the cell in a layout window (see Figure 2-10 on
page 2-27).
Creating Cells
To create a new cell,
1. Enter geCreateCell, create_design, or choose Cell >
Create.
The Create Cell dialog box appears.
2. Next to Cell Name, enter the name you want to assign to the new
cell.
If you enter the name of an existing cell, the tool will increment
the current version number of the existing cell for the new cell.
3. Click OK.
The tool creates an empty cell in the open library.

2-26

When you open an existing cell or create a new cell, Astro displays
the cell in a separate layout window, as shown in Figure 2-10.
Figure 2-10
Cell Layout Window

2-27
Navigating Inside a Layout Window

The layout window contains navigation, command history, and
selecting and editing buttons.
Navigation Buttons
Use the buttons at the left of the graphical layout window to navigate
around the design, as described in Table 2-3. If you hold the pointer
over a button, a Tool Tip appears that tells you what the button does.
Table 2-3
Navigation Buttons
Button
Calls this menu command
Performs this function
Views > Redraw
Redraws the design view.
Views > Up
Moves the display in the graphical

layout window up by half.
Views > Fit
Fits the entire design in the

graphical layout window. Use this
command after panning or zooming.
View > Zoom Out X4
Zooms out in the graphical layout

window by a factor of 4.
Views > Left

layout window left by half.
Redraw
Scroll up
Fit cell
Zoom out 4X
Scroll left

2-28
Table 2-3
Navigation Buttons (Continued)
Button
Views > Pan
Pans the design in the graphical

layout window so that a specified
point in the design is in the center of
the window.
Views > Right

layout window right by half.
View > Zoom Out X2
Zooms out in the graphical layout

Views > Pan Pt to Pt
Pans the design in the graphical

layout window by an amount and in
a direction you specify by entering
two points.
Views > Down

layout window down by half.
Views > Fit+
Fits the entire design plus a border

equal to 10 percent of the design
size into the graphical layout
window. Use this command after
panning or zooming.
View > Zoom In X2
Zooms in on the graphical layout

Move center to
Scroll right
Zoom out 2X
Pan to
Scroll down
Fit with margin
Zoom in 2X

2-29
Table 2-3
Navigation Buttons (Continued)
Button
View > Previous View
Returns the graphical layout window

to the state it was in before you
executed the last viewing
command.
None
Returns the graphical layout window

to the state it was in before you used
the previous view button.
View > Zoom In
Zooms in to an area in the graphical

layout window that you specify by
entering diagonal corners of a
rectangle.
None
Moves the side bar to the left or right

side of the graphical layout window.
Previous view
Next view
Zoom to area
Additional
commands
Command History Buttons

Use the buttons at the left of the graphical layout window to invoke
any of the last three commands executed. (As you run commands,
the three buttons are updated with the most-recent command
appearing in the top button.) Commands invoked with bind keys or
shortcut buttons on the graphical layout window side bar do not
appear in these command history buttons.

2-30
Selecting and Editing Buttons

Use the buttons on the left side of the graphical layout window to
access the commands, as described in Table 2-4. Commands
accessed through these buttons do not appear in the command
history buttons.

2-31
Table 2-4
Selecting and Editing Buttons
Button name
Menu command called
Window option
Options > Window
Layer panel
Options > Layer
Query-object
Query > Object
Query-net
Query > Net Query By Point
Select-point
Select > Select Select By Point
Select-line
Select > Select Select By Line
Select-window
Select > Select Select By Window
Deselect-point
Select > Deselect Deselect By Point
Deselect-all
Select > Deselect Deselect All
Ruler
Query > Ruler Ruler
To customize the shortcut buttons, modify the avntInit.scm file in your

directory (under /etc/scheme/.) by editing the setSideButton
section. The setSideButton command defines the side-button
commands. The syntax is
setSideButton windowNum Position "Name" "Command"
where the arguments are

windowNum
The graphical layout window on which you want the side button
to appear. A value of 0 applies the button to all open windows.
Position
The button position on the side bar. Valid values are 110.

2-32
Name
The name that appears on the side button.
Command
The Scheme command you want the side button to invoke.
The default setSideButton settings serve as an example and are

shown below:
(setSideButton
(setSideButton
(setSideButton
(setSideButton
(setSideButton
(setSideButton
(setSideButton
(setSideButton
(setSideButton
(setSideButton
0
0
0
0
0
0
0
0
0
0
1 "Window option" "geWindowOption")

2 "Layer panel" "geLayerPanel")
3 "Query-object" "geQueryObject")
4 "Query-net" "geQueryNet")
5 "Select-point" "gePointSelect")
6 "Select-line" "geLineSelect")
7 "Select-window" "geWindowSelect")
8 "Deselect-point" "gePointDeselect")
9 "Deselect-all" "geDeselectAll")
10 "Ruler" "geRuler")
Using the Context View and Information Bar

When you pan and zoom inside a graphical layout window, it is easy
to get lost; the tool provides a context view and an information bar to
help you find your way.
The context view, located in the upper-left corner of the graphical
layout window, contains the following:
A green rectangle marked with an X that represents the whole

cell
A red rectangle that represents the view of the current layout

window relative to the whole cell
To see how the context view works, use commands from the Views
menu to pan and zoom the current window.

2-33
The information bar, located at the top of the graphical layout

window, contains the following:
X and Y values that represent the location of the pointer in the

current graphical layout window (or in the context view)
A select count that indicates the number of objects selected in

the current graphical layout window
Opening Multiple Layout Windows

Each time you open a cell, Astro creates a graphical layout window.
If you open multiple layout windows, Astro will place them on top of
each other and number them. (The number appears in the upper-left
corner of every layout window.) You can move and size layout
windows, using standard window manager operations.
Making a Layout Window Current

If you have several cells open at once, the commands you execute
apply only to the cell in the current layout window. The current layout
window has a yellow band at the top; this band also displays the
pointer location coordinates. To make a different layout window
current, move the pointer to the band at the top of the layout window
and click the band. The band turns yellow, and the layout window is
current.
Note:
The layout window in front is not necessarily the current window.

2-34
Opening the Same Cell in Multiple Layout Windows

When you use a point command that requires the selection of points
in different areas of the cell, you might want to open the cell in
multiple layout windows. This lets you pan and zoom (in different
windows) to the relevant areas of the cell for a more precise point
selection.
When you move the pointer to an area of a cell that is visible in two
layout windows, the pointer appears in both windows. If you select an
object that is visible in both windows, the tool will highlight the
selected object in both windows.

A command file is a file that contains commands of the following
types:
Replay files, which are created by each tool and contain

commands executed during a session.
Startup files, a special type of replay file used to set up your

environment. You can create a startup file by running a tool, then
editing the automatically generated replay file.
Load files, which are created by the user and generally contain
db functions that provide information needed by the tool.
When you replay or load a command file, the tool reads the file and
executes the commands and functions it contains.

2-35
Replay Files
Each time you run Astro, Astro automatically generates a command
file called a replay file, which contains all the commands executed
during a session. You can replay a replay file by opening the tool with
the -replay startup option. Use the following syntax at the system
prompt:
ToolName -replay fileName
where ToolName is the name of the tool you want to start, such as
Astro, and fileName is the name of the replay file.
For Tcl, use
ToolName -file fileName
By default, Astro creates replay files with the name

ToolName.cmd.mo_dd_hh_mm in Scheme mode and
ToolName.tcl.mo_dd_hh_mm in Tcl mode. However, you can specify
a different name for the replay file when you start Astro, by using the
-cmd startup option.
Alternatively, you can replay the file by using the following command
syntax in the command window:
load fileName
where fileName is the name of the replay file.

For Tcl, use
source fileName

2-36
Caution!
Replay files should not contain replay functions. The behavior of
the replay file when executing a replay function is unpredictable.
In Tcl mode, there is no distinction. Your Tcl file can contain other
Tcl files.
Loading files by using the -load startup option is nearly identical
to replaying files, except that they usually do not flush graphic
operations as often as replay. This means that some GUI display
operations might be skipped; that is, you might see fewer window
or drawing operations with -load.
Startup Files
A startup file is a special type of replay file used to set up your
environment. This startup file is .avntrc in Scheme mode and
.synopsys_astro.tcl in Tcl mode. Use the startup files to set the
environment for Astro in general or for a particular library.
You can create a startup file manually by using a UNIX text editor.
You can also create a startup file by running the tool and editing the
automatically generated replay file. For example, you might create a
startup file to automatically open the library you typically use when
you start the tool or to automatically open the top-level cell when you
open a particular library.
Tool Startup Files

When you start Astro, it looks for the .avntrc or .synopsys_astro.tcl
file in the following directories:
1. The local directory (from which you issue the startup command)
2. Your home directory

2-37
3. The install directory (where the tool is installed)

When it finds a file, the tool stops searching and automatically
replays the file.
Note:
If you have parameters you want to set every time you run Astro,
you can also define the ASTRO_SHELL_ARGS environment
variable for your system. For example, when you define the
ASTRO_SHELL_ARGS as the string -log astro.log, Astro adds
this as an argument on the command line before any arguments
you enter on the command line.
Library Startup Files

When you open a library, the tool looks for a file named
.avntrc-fileName (where fileName is the name of the library you are
opening) in the local directory. When the tool finds the file, it stops
searching and automatically replays the file.
Load Files
Throughout the design flow, you can provide information to the tool
by using load files. These files generally contain db functions. For
example, a port information file that contains
dbSetCellPortTypes functions is a load file.
To load a load file, use the following syntax in the command window:
load fileName
where fileName is the name of the load file.

2-38
Script Files
A script file is a combination of Scheme or a combination of Tcl
functions and command syntax in a text file, which you can use to
accomplish a series of tasks in sequence.
You execute scripts in Astro by using the load_scheme command
or the source command. Enter these commands in the command
window.
To run a Scheme script, the syntax is

load_scheme script_file_name
To run a Tcl script, the syntax is

source script_file_name

When you exit an Astro session, Astro displays a window where you
can select the cells you want to save from a list of all open cells.
To exit an Astro session,
1. If you have a cell and library open, enter geCloseWindow or
choose Cell > Close.
The Save Cells dialog box appears.

2-39
2. In the Save Cells dialog box, select the cells you want to save
from the list of cells, click Save All, or Click Discard All.
3. Click OK.
You can also use the geNameSelect command to select cells to
be saved. In the Name Select dialog box, enter the cell names or
use pattern matching to select all cells with names that match a
pattern and click select. For example, enter .*CEL to select all
cells with names that end with CEL.
4. Enter geConfirmCloseLib or choose Library > Close, and
click OK to confirm that you want to close the library.
5. Enter menuQuit or choose Tools > Quit.
Astro terminates the session and closes any open windows.

2-40

Use the defineStroke command to assign a command or function
to a stroke-code sequence. You can then run the command or
function by left-clicking the mouse and dragging the pointer to form
the specified stroke sequence. The stroke sequence appears as a
white or yellow line.
The syntax is
defineStroke "strokeSequence" "command"
where strokeSequence is the number representing the stroke-code

and command is the name of the command to be invoked by the
stroke.
Keep in mind that the stroke mode is off by default. You can control
whether the stroke mode is on or off by using the disableStroke
command. To enable the stroke mode, in the command window enter
disableStroke #f
For Tcl, enter

disableStroke 0
To disable the stoke mode, enter

disableStroke #t
For Tcl, enter

disableStroke 1

2-41
A stroke-code is a numerical sequence string which represents the

directions the mouse is moved for the stroke. The numbers are
based on the numeric keypad. The following figure shows the
directions associated with each keypadthe implied starting point
for each stroke in the sequence is the center of the matrix (keypad 5).
7
(up/left)
8
(up)
9
(up/right)
4
(left)
6
(right)
1
(down/left)
2
(down)
3
(down/right)
Each change in direction defines a stroke segment. For example, for

a stroke in the form of an L, the numerical sequence is 26, as shown
in the following figure:
Starting point
End point
First stroke
segment
Second stroke
segment

2-42
To assign a command, such as astPlaceOptions, to this

stroke-code sequence, enter the following in the command window:
defineStroke "26" "astPlaceOptions"
When you use this strokeby left-clicking the mouse and dragging
it down and then to the rightthe AstroPlace Options dialog box
opens.
To undefine a stroke, use the undefineStroke command. The
syntax is
undefineStroke "strokeSequence"
To list the strokes currently defined, use the listStroke command.

The syntax is
listStroke
Using Integer and Real Parameters for Astro

Operations
For information about the parameters you can set with the
axSetIntParam and axSetRealParam commands, see
Appendix D, Astro Parameters.
Using Integer and Real Parameters for Astro Operations

2-43

2-44
3
Creating Milkyway Reference Libraries
When using Astro, you need to create and use Milkyway reference
libraries of standard cells, macro cells, and pad cells.
This chapter includes the following sections:
Using the Milkyway Database
Creating a Standard Cell Library
Creating a Macro Cell Library
Creating LM Views for Timing and Power Analysis
Creating Logical Equivalent Cell Information
Loading Pad Orientation, Diode Protections, and Gate Size Data
Defining Multiple Tiles for Placement
3-1

The Synopsys Milkyway database is a widely used database for IC
design implementation and advanced technologies extending to 65
nanometers (nm) and below. Astro and tools related to Astro are built
on the Milkyway design databasethey can directly access critical
data without time-consuming and error-prone translation steps,
significantly reducing design time. The Milkyway database facilitates
convergence of critical design properties, including timing, area,
power, and signal integrity.
Milkyway File Types

The file types used for creating a Milkyway database are the
following.
Technology Files
A technology file defines the characteristics of a Milkyway library, for
example, units of measure, graphical specifications, layer and device
definitions, and design rules.
Cell Library Format Files

A Cell Library Format (CLF) file provides a tool with library-specific
information.
Chapter 3: Creating Milkyway Reference Libraries

3-2
Top Design Format Files

Each design library should contain one or more top design format
(TDF) files. These files provide Astro with special instructions for
planning, placing, and routing the design. TDF files generally include
pin and port information. Astro particularly uses the I/O definitions
from the TDF file in the starting phase of the design flow.
GDSII Files
GDSII is a standard format for physical layout information. This file is
used to transport physical layout designs between different design
environments.
Netlist Files
Verilog, VHDL, and EDIF are standard formats for describing logical
designs. Using Milkyway, you can easily translate data in these
formats to tool cell format, or you can write tool data to these
standard formats.
Synopsys Design Constraints File

Astro uses Synopsys Design Constraints (SDC) commands to do
timing analysis. For more information, see Loading Timing
Constraints on page 6-6.
Design Database File

The standard Synopsys .db file; contains netlist, timing, and design
rule constraints.

3-3
Synthesis Library File

The standard Synopsys synthesis .lib or .db file; contains cell timing
and functionality information.
Data Input Requirements for Astro

Astro requires the following files for creating a Milkyway database:
A technology file (.tf), which is a required element for every

Milkyway design or reference library. It describes the units,
drawing patterns, layers, design rules, vias, and parasitic
resistance and capacitance of the manufacturing process.
You typically create the technology file by manually editing an
existing technology file to ensure complete and accurate
descriptions for the routing layers. Then you create or replace the
capacitance tables by using either the Milkyway
cmCreateCapModel command (see Physical Implementation
Online Help) to create a TLU capacitance table or by using the
Star-RCXT grdgenxo command (see the Star-RXCT User
Guide) to create more accurate TLUPlus capacitance tables.
For details about technology files, see the Milkyway Environment
Data Preparation User Guide.
Reference libraries, which are created from the following files:

- A technology file (.tf)
- GDSII files (.gds) that contain the physical layout information
- Synthesis library files (.lib or .db) that contain cell timing and
functionality

3-4
- (Optional) LEF files (.lef) that contain physical cell library

information
The information in LEF is equal to what is provided in the
technology file and GDSII files.
A design library, which is created from the following files:

- A technology file (.tf)
- GDSII files (.gds) that contain the physical layout information
or reference libraries that contain the physical layout
information
- TDF files (.tdf) that contain pin and port information
- (Optional) A CLF file (.clf) that contains pad orientation
information
- A constraints file (.sdc) that contain timing constraints and
clock definitions
- A Verilog netlist file (.v), VHDL netlist file (.vhd), or EDIF netlist
file (.edf) that contains connectivity information
- A design database file (.db) that contains netlist, timing, and
design rule constraints
- (Optional) PDEF v2.0 files that contain cell placement
locations
- (Optional) DEF files (.def) that contain design netlist
information

3-5
Data Output From Astro

After optimization, placement, and routing, you can generate the files
listed in Table 3-1 from Astro.
Table 3-1
Files Generated by Astro
File type or format
File content
Design .sdf
Post-floorplanning timing
Parasitic .spef or .spf
Parasitic information
Updated Verilog .v (flattened) or .hv

(hierarchical)
Optimized netlist
Updated physical layout .gds
Physical layout information
(Optional) Updated design .pdef
Cell placement locations
(Optional) Updated design .def
Netlist and floorplan (cell placement)

information
(Optional) Updated physical layout .lef
Physical layout, timing, and

technology information of reference
libraries
Milkyway Library Directory

The Synopsys Milkyway database is a collection of directories and
files. The top-level directory is a reference or design library that
contains files, subdirectories called views, and cells. Reference
libraries contain standard cells, macro cells, and pad cells, which are
building blocks for a design. A design library is a design of a block or
chip that is implemented in Astro and instantiates building blocks
from reference libraries.

3-6
After you create a design library and complete the physical design in
Astro, the design library can become a reference library for another
design in a hierarchical design environment.
Figure 3-1 shows the structure of a Milkyway library directory.
Figure 3-1
Milkyway Library Directory

Milkyway library
directory
lib
CEL
EXP
FRAM
LM
LOGIC
NETL
PARA
PWR
TIM
Directory/View
File
A Milkyway library directory should contain the following for each

library:
A library information file named lib. This is a binary file, created

by entering the geCreateLib command or choosing Library >
Create, that contains a catalog of the other elements in the
database. The tools use this file to track the library structure and
content.
Binary files cannot be edited, but you can change the catalog by
using Milkyway commands to unload and reload files, such as the
technology file and CLF files. For example, the catalog is updated
by entering the cmReplaceTech command or choosing

3-7
Library > Replace Tech File. When unloading a technology file,

Milkyway places the technology file information in an editable
format so that you can modify it with a UNIX text editor.
Library views (subdirectories) containing cells of each type in the

library or other information, such as attached binary files.
Milkyway Library Views

Table 3-2 lists the various views in a Milkyway library and their
contents.
Table 3-2
Milkyway Library Views
Data
View
Content
Geometry
and
physical
data
CEL view
Physical data (the CEL view contains all physical data

imported into the database or created by Astro)
FRAM view
Placement and routing abstraction of CEL view
SMASH view
Flattened CEL view
HTV view
Hierarchical timing view of CEL view, similar to an interface

logic model (ILM) in other Synopsys tools
LM view
Timing, power, and logic information (newer format that

provides the same information as the TIM view plus the
PWR view)
PWR view
Power information (older format of LM view)
TIM view
Timing information (older format of LM view)
LOGIC view
Timing constraints, clock definition, and netlist information

from Design Compiler or Physical Compiler (provides the
same information as the NETL view plus the Synopsys
Design Constraints (SDC) file)
Timing,
power, and
logic
Netlist

3-8
Table 3-2
Data
Other
Milkyway Library Views (Continued)

View
Content
NETL view
Netlist information (hierarchical); each module in an

imported Verilog netlist is stored as a binary file in the NETL
directory, or the equivalent for a VHDL or EDIF netlist
EXP view
Expanded (flattened) netlist data
HNET view
Hierarchical netlist information
PARA view
Parasitic RC data for Astro, Star-RCXT, or an external

extractor tool
CONN view
Internal power and ground structure of macro cell

connectivity information for rail analysis with Astro-Rail
ERR view
Results from Astro design rule checking (DRC) or logic

versus schematic (LVS)
FILL view
Routing fill data created by Astro
GAP view
Routing gap data created by Astro
NOTC view
Routing notch data created by Astro
ROUTE view
Routing views created by Astro distributed routing

Figure 3-2 shows the commands for creating a standard cell
Milkyway library.

3-9
Figure 3-2
Standard Cell Library Flow

Create library
cmCreateLib
Technology file
GDSII stream file
Read cell layout

auStreamIn
Cell type definition file

Layer file (optional)
Identify power and ground ports

dbSetCellPortTypes
Extract blockages, pins, and vias

auExtractBlockagePinVia
Prepare
Physical
Data
Set place and route boundary

auSetPRBdry
Define wire tracks

axgDefineWireTracks
Create LM view
gePrepLibs
Prepare
Logical
Data
Load LEQ CLF data

astExtrLEQ
Load supplemental CLF data

auLoadCLF
To design data preparation

3-10
Prepare
Physical
Data
As shown in Figure 3-2, the standard cell library creation flow

includes several tasks. You can use the read_lib command to
select the various library preparation commands, or you can run the
individual library preparation commands separately.
Note:
For more details about the commands and processes described
in the following procedures, see the Milkyway Environment Data
Preparation User Guide and the Physical Implementation Online
Help.
Creating the Library With the read_lib Command

To use the read_lib command for creating a standard cell library,
1. Display the Milkyway Data Prep menus by choosing Tools > Data
Prep or starting the Milkyway executable file.
2. Enter the read_lib command to display the Read Library
dialog box, which lets you select the commands for creating a
Milkyway library.
3. Enter a library name and click Prepare Physical Library to display

the physical library preparation options.

3-11
4. Select a Physical Input Format, for example, the TF+GDSII+CLF

option for creating the library with inputs of a technology file, a
GDSII file, and a CLF file.
The other Physical Input Format options are
- LEF for creating a library with a LEF file input
- TF & LEF for creating a library with a technology file and a
LEF file inputs
- LEF & GDSII for creating a library with LEF file and GDSII file
inputs
- PLIB for creating a library with a PLIB file input
- PLIB & GDSII for creating a library with a PLIB file and GDSII
file inputs

3-12
When you select one of the options, the dialog box expands to
show the physical library preparation options, as shown in the
following figure. The options are listed in the order you typically
use them when creating the library, the first step being to create
the library.

3-13
5. Click Create Library to display the Create Library dialog box,

enter the appropriate information, and click OK. (This dialog box
is described along with the other commands you use for creating
a standard cell library in Creating the Library With the Individual
Commands on page 3-15.)
If you attempt to select a library preparation step out of order,
Astro displays an error message.
Each physical library preparation step you complete is indicated
by a change in the check box color. For example,
You can click Check Library to check for any problems in the
library at any step in the flow.
6. Complete the physical library preparation steps indicated in the
standard cell library creation flow in Figure 3-2 on page 3-10.
7. After you complete the physical library preparation steps, click
Prepare Logical Library to display the library logical preparation
options.

3-14
8. Click LIB/DB for Logical Input Format. This displays the Library
Preparation dialog box, shown on page 3-22.
9. After you prepare the logical data, click Prepare Logical Library,
and click Check Library to check for any problems in the library.
Creating the Library With the Individual Commands

To use the individual commands for creating a standard cell library,
1. Display the Milkyway Data Prep menus. Choose Tools > Data
Prep or start the Milkyway executable file.
2. Create the library. Enter cmCreateLib or choose Library >
Create to display the Create Library dialog box.
Enter the Library Name, Technology File Name, and Hierarchy

Separator, and enable the Set Case Sensitive option.
This creates the directory for the library and the lib binary file for
tracking library elements.

3-15
3. Read the cell layout. Enter auStreamIn or choose Cell Library

> Stream In to display the Stream In Data File dialog box.
Enter the Stream File Name and the Library Name.

4. (Optional) Enter a Cell Type Definition File name. If all cells are
standard cells, you do not need a cell type definition file because
gdsStandardCell is the default cell type definition. A cell type
definition file is a text file where each line specifies a cell type. For
example,
gdsStdFillerCell F*
gdsOtherCell TEST VIA1 RCAP FEED2
gdsPadCell P*
gdsStandardCell *

3-16
This creates CEL views for all the cells in the GDSII file.
The complete physical descriptions from the GDSII file are stored
in the CEL views. Although this is more data than is required by
Astro for place and route, the data is retained to ensure that all
the design data is included when you write files from Astro.
5. Identify power and ground ports. Use dbSetCellPortTypes.
For example, create a text file named pg_only.porttypes with the
following:
dbSetCellPortTypes "cb_mini_a" "*" '(
("VDD" "Power" )
("VSS" "Ground" )
) #f
Then load the file into Astro. Enter,

load "pg_only.porttypes"
6. (Optional) Smash the layout cell to remove hierarchy. Enter

cmSmash or choose Cell Library > Smash.
This creates SMASH views in the library with the flattened CEL
views.
7. Extract pins, blockages, and vias.
Enter auExtractBlockagePinVia or choose Cell Library >
Blockage, Pin & Via to display the Extract Blockage dialog box.

3-17
Enter the appropriate layers to reflect the text definitions in the

GDSII information.

3-18
This creates the FRAM views, which are abstractions of the CEL
views for place and route.
8. Set the place and route boundary. Enter auSetPRBdry or
choose Cell Library > Set PR Boundary to display the Set PR
Boundary dialog box.

3-19
This creates place and route boundary information (a 1xN tile

map) in the FRAM view, which might or might not be the same as
the cell boundary. It allows the placer to move cells together until
their place and route boundaries touch.
Note:
If the standard cell library includes multiheight cells, you need
to use the cmSetMultiHeightProperty command to
generate an MxN tile map for proper placement of multiheight
cells.
9. Define wire tracks. Open the library (geOpenLib or Library >
Open) you created in step 2, then enter
axgDefineWireTracks or choose Wire Tracks > Define Unit
Tile Wire Tracks to display the Define Wire Track dialog box.

3-20
Routing tracks are spaced by the pitch value specified in the

technology file. Enter appropriate offsets for your design. Wire
track information is stored in the FRAM views.
10. Import the logical timing process, temperature, and voltage
(PVT) information. Enter gePrepLibs or choose Cell Library >
Library Preparation to open the Library Preparation dialog box.

3-21
If you have one or more Synopsys .db files with PVT data for
analysis, click Import Logic Model DB, then click Select DB to
display the Import Logic Model DB options.
Enter a .db file name in the appropriate Min DB File, Max DB File,
Typical DB File, or Other DB File fields, which represent various
process corners for analyzing process, temperature, and voltage.
If you have multiple .db files for one process corner, enter the file
names in the field, separated by a space.
This creates LM views for storing the PVT information.

3-22
For information about the other options for importing PVT data,
see Creating LM Views for Timing and Power Analysis on
page 3-29 and the gePrepLib command in Physical
Implementation Online Help.
11. Load logical equivalent cell information. Enter astExtrLEQ or
choose CLF > Extract LEQ.
See Creating Logical Equivalent Cell Information on page 3-35.
12. Load supplemental CLF data. Enter auLoadCLF or choose CLF
> Load.
See Loading Pad Orientation, Diode Protections, and Gate Size
Data on page 3-40.

3-23

Figure 3-3 shows the flow for creating a macro cell library.
Figure 3-3
Macro Cell Library Flow
Technology file
Create library
cmCreateLib
GDSII stream file

Cell type definition file
Read cell layout

auStreamIn
Layer file (optional)

Identify power and ground ports
dbSetCellPortTypes
Smash cells
cmSmash
Prepare
Physical
Data
(Optional) Create CONN views

poCreateConnView
Extract blockages, pins, and vias

geNewMakeMacro
Create LM view
gePrepLibs
Prepare
Logical
Data
Load supplemental CLF data

auLoadCLF
Prepare
Physical
Data
To design data preparation

3-24
As shown in Figure 3-3, the macro cell library creation flow includes
several tasks. You can use the read_lib command to select the
various library preparation commands, as described in Creating the
Library With the read_lib Command on page 3-11. Or you can run
the individual library preparation commands separately, as
described in the following steps:
1. Display the Milkyway Data Prep menus. Choose Tools > Data
Prep or start the Milkyway executable file.
2. Create the library. Enter cmCreateLib or choose Library >
Create to display the Create Library dialog box.
Enter the Library Name, Technology File Name, Hierarchy

Separator, and enable the Set Case Sensitive option.
This creates the directory for the library and the lib binary file for
tracking library elements.
3. Add a reference to the standard cell library required to complete
the physical description of the macro. Enter cmRefLib or choose
Library > Add Ref to open the Ref Library dialog box.
3-25
Enter the Library Name and Ref Library Name.

4. Read the GDSII layout description of the macro cell into the
macro cell library. Enter auStreamIn or choose Cell Library >
Stream In to open the Stream In Data File dialog box.

3-26
Enter the Stream File Name and the Library Name.

Enter a Cell Type Definition File name. Because
gdsStandardCell is the default cell type definition, you need
to define the macro cells. A cell type definition file is a text file
where each line specifies a cell type. For example,
gdsMacroCell BLOCK1 BLOCK2 BLOCK3
gdsMacroCell nand_macro
gdsStandardCell *
This creates CEL views for all the cells in the GDSII file. The
complete physical descriptions from the GDSII file are stored in
the CEL views.
5. Identify power and ground ports. Use dbSetCellPortTypes.
For example,
dbSetCellPortTypes "nand_macro" '(
("VDD" "Power" )
("VSS" "Ground" )
) #f
6. Create an abstract FRAM view of the CEL view for placement

and routing by doing the following:
a. Open the nand_macro_lib library created in step 2.
b. Open the nand_macro cell created in step 3.
c. (Optional) If the cell pins are not available at the top level of
hierarchy, use the cmSmash command to bring the pin
geometries and text to the top level of the cell.
d. Enter geNewMakeMacro or choose Cell > Make Macro
Abstract to open the Make Macro dialog box.

3-27
e. Click Extract Pin by Text and enable Identify Macro Pin By Pin
Text.
This creates a FRAM view that is blocked in all metal layers,
except the area that is cut out for accessing pins.

3-28
Note:
If a place and route boundary is not defined in the GDSII
description, Astro uses the cell boundary to represent the
macro size and dimension.
f. Close the nand_macro cell and the nand_macro_lib library.
7. (Optional) For top-level rail analysis with Astro-Rail, you need to
create a CONN view.
8. You can import the logical timing process, temperature, and
voltage (PVT) information by entering gePrepLibs or choosing
Cell Library > Library Preparation, as described in step 10 in
Creating the Library With the Individual Commands on
page 3-15.
This creates LM views for storing the PVT information.
9. Load supplemental CLF data. Use auLoadCLF or choose CLF >
Load.
See Loading Pad Orientation, Diode Protections, and Gate Size
Data on page 3-40.

Use the gePrepLibs command to create the LM (logic model) view
in the Milkyway database. The LM view stores the Synopsys library
.db information. Astro will use the LM view, when it exists, for timing
and power analysis. If the LM view exists, the default operating
conditions will be set for this library. Optionally, you can choose a
different .db file for an operating condition.
It is recommended that you use LM views, and not TIM views, to get
the best SDC and timing correlation.
3-29
Note:
The TIM and PWR views, which provide almost the same
information as the LM view, are being replaced by the LM view.
The LM view has full backward compatibility with both the TIM
and PWR views. When TIM and PWR views exist, as well as an
LM view, the LM view has a higher priority.
The gePrepLibs command can handle all combinations of
minimum, typical, and maximum operating conditions. The LM view
might have multiple databases for each of these operating
conditions. When you run the gePrepLibs command, it creates the
LM view and does the following:
Attaches all logical, timing, and power libraries to the LM view
Registers the minimum, typical, and maximum logical libraries in

the LM view
The process, voltage, and temperature information is stored in the

LM view for each individual .lib or .db file processed with the
gePrepLibs command.
When you create an LM view within the Milkyway reference library,
you can store the .db files and read them directly into the Astro timer.
The LM view enables the optimization and timing analysis processes
in Astro to use the same timing library as the Design Compiler,
Physical Compiler, and PrimeTime tools. Because the delay model
to be used is now determined by the reference timing library (based
on the LM view), Astro uses the same cell delay calculator as
PrimeTime. You can also read the .db files directly into Astro-Rail
analysis.

3-30
Before you use gePrepLibs, you need the following items:
A Milkyway reference library
A timing library in .lib format or .db format
When you generate an LM file from a .lib file, Astro uses the Library
Compiler tool to convert the .lib format to .db format. You must have
lc_shell in your path before you start Astro.
Note:
For more information about the gePrepLibs command and
options, see Physical Implementation online Help. Also see
Chapter 6, LM View and Delay Calculation in the Astro User
To generate an LM view for a .lib file,
1. Enter gePrepLibs or choose Tools > Data Prep > Cell Library >
Library Preparation.
2. Click Import Logic Model DB to display the Import Logic Model
DB options.
3. Click From .lib to display the options. The following figure shows
the Library Preparation dialog box with the import .lib options
displayed.

3-31
4. Enter the name of the Milkyway reference library to which the LM

view will be added.
5. Enter the .lib file names you want to import.
6. Click OK or Apply.
Library Compiler converts the .lib to .db format, and the
gePrepLibs command stores the .db-formatted information in
the LM view in the specified Milkyway library.

3-32
Alternatively, it might be easier for you to use the compiled .db file
directly. In this process, gePrepLibs does not regenerate the .db
fileit needs to establish the Milkyway category file only. This is
faster than generating the LM view from the .lib file, because there is
no need to invoke Library Compiler to convert the .lib format to .db
format. For detailed information about converting .lib format to .db
format, see the Library Compiler documentation.
To generate an LM view from a .db file,
1. Enter gePrepLibs or choose Tools > Data Prep > Cell Library >
Library Preparation.
2. Click Import Logic Model DB to display the Import Logic Model
DB options.
3. Click Select DB to display the options. The following figure shows
the Library Preparation dialog box with the import .db options
displayed.

3-33
4. Enter the name of the Milkyway reference library to which the LM

view will be added.
5. Enter the .db file names you want to import.
The gePrepLibs command stores the .db-formatted
information in the LM view in the specified Milkyway library.

3-34

It is recommended that logical equivalent cell information be added
to the library during the library preparation flow to clarify which cells
are logically equivalent. For example, signal buffers, delay cells, and
clock buffers might all be similar logically, but it would not be
appropriate for the tool to interchange them.
Astro can utilize logical equivalent cell information prepared in the
reference libraries (known as library LEQ) or build that information
when running on the design cell (known as design LEQ). This
concept of library LEQ and design LEQ lets a library provider or CAD
group explicitly set logical equivalent cell information in the reference
libraries while giving you the capability to override this information
without modifying the reference libraries.
By default, Astro builds the design LEQ during runtime, instead of
using the library LEQ; it also merges logical equivalent cell
information across reference libraries, instead of maintaining
separate information for each library. (This behavior is selectable in
the Optimization page of the AstroTime Timing Setup dialog box and
is saved with the cell.) This allows Astro to find equivalent logic cells
in multiple reference libraries. For example, Astro can swap a
high-speed buffer for a low-speed buffer even when they are in
separate high-speed and low-speed libraries.
Keep the following points in mind:
Typically, logical equivalent cell information should be added

during library creation and stored in the reference library.
By default, logical equivalent cell information is established at

runtime and spans reference libraries.

3-35
If logical equivalent cell information is not found in the reference

library, Astro can automatically generate logical equivalent cell
information.
Extracting and Loading Logical Equivalent Cell

Information From Boolean Information
Use the astExtrLEQ command to extract and load logical
equivalent cell information from Boolean information. This command
also allows extraction of existing logical equivalent cell information,
which is useful for debugging.
To extract and load reference library LEQ from the Boolean
information that exists in the specified reference library,
1. Enter astExtrLEQ or choose Tools > Data Prep > CLF > Extract
LEQ.
The Extract LEQ Cells dialog box appears.
2. Under Library Name, enter the name of the reference library

being extracted.
3-36
3. Under Output To, select where you want the information to be

written (Window or File). If you select File, enter its name in the
File Name box.
The reference library LEQ file contains a list of commands similar
to the following:
dbCreateCellLEQClass
dbClearCellLEQClass
You can review the extracted logical equivalent cell information

and modify the reference library LEQ file if necessary.
4. Click OK.
By default, this command automatically loads the information it is
extracting.
You can choose not to load the extracted information. There are
various reasons not to load the information at this time. For
example, you might want to build a library LEQ file, edit it, and
subsequently load the edited file. To load an edited file, use the
following syntax:
load "leqFileName"
Using Design LEQ

Design LEQ consists of logically equivalent cells used for
optimization. Astro automatically generates logical equivalent cell
information when it is needed. The basic process is as follows:
By default, or if design LEQ does not exist because the design is

freshly opened, Astro extracts the logical equivalent information
for cells not defined by the library LEQ.

3-37
If the Ignore User LEQs option is selected in the Optimization

page of the AstroTime Timing Setup dialog box and if design LEQ
exists, Astro uses it.
Logical equivalent cell information automatically spans reference

libraries, unless the Merge Library LEQs option is deselected in
the Optimization page of the AstroTime Timing Setup dialog box.
Astro supports design-specific specifications, such as

astSetClockCell, astSetDelayCell, and astSetDontUse,
that you can use to customize logical equivalent cell information.
Specifying Design LEQ From Multiple Reference

Libraries
You can use the astLoadDesignLEQ command to specify LEQ
cells from multiple reference libraries so that buffers from the
different reference libraries can be interchanged for optimization.
The information in the file is in addition to what is in the reference
librariesAstro ignores LEQ specified in the reference libraries for
only those cells specified in the file.
If you want the design LEQ specified in the file (loaded with
astLoadDesignLEQ) to be the only source of information, use the
pds_only_design_LEQs parameter. Enter the following:
define pds_only_design_LEQs 1
To specify design LEQs from multiple reference libraries,

1. Create a text file with the LEQ cell pairs. For example,
cell1 cell2
cell1 cell3
cell2 cell4

3-38
cell5 cell6
cell7 cell8
This file specifies that

- Cell1, 2, 3, and 4 are LEQ
- Cell 5 and 6 are LEQ
- Cell 7 and 8 are LEQ
2. Use the astLoadDesignLEQ command to store the file you
created in step 1 in the design library. For example,
astLoadDesignLEQ "leqFileName"
The file is stored in the top-level design CEL view, and the design
LEQ cells are stored in the design library.
Clearing Design LEQ

Use the astClearDesignLEQ command to clear any design LEQ
information from the CEL view.
Verifying Design LEQ

To determine the logical equivalent cell information to be used by
Astro (to aid debugging), you can use the following command syntax:
astDumpDesignLEQ "leqFileName"
To use this command, you must have the library and cell open, and
the cell must be ready for timing analysis. Sample output follows:
** class 151 ***
cell=dl04d4 type=BUFFER "volt_gr=0"

3-39
Z = I
cell=bufbd1 type=BUFFER "clock_cell" "volt_gr=0"
Z = I
cell=dl04d1 type=BUFFER "delay_cell" "volt_gr=0"
You can also use the astDumpAttachedDesignLEQFile

command to write the design LEQ file from the design librarys top
design CEL view. The syntax is
astDumpAttachedDesignLEQFile "leqFileName"
Loading Pad Orientation, Diode Protections, and

Gate Size Data
Use the auLoadCLF command to add non-timing CLF commands
that are required for a specific library and are not included in the
Synopsys .lib file; for example, pad rotating information and antenna
information such as gate size and diode protection.
Examples of nontiming CLF commands are
definePad
defineDiodeProtection
defineGateSize
To load non-timing CLF commands into the library,

1. Enter auLoadCLF or choose Tools > Data Prep > CLF > Load.
The Load CLF File dialog box appears.

3-40
2. Select Load CLF File Without Timing Related Information.
In the reduced window that appears, do the following:

- Enter the name of the CLF file to be loaded.
- Enter the name of the reference library to which the CLF will be
loaded.
Loading Pad Orientation, Diode Protections, and Gate Size Data

3-41
3. Click OK.
Note:
You can also load a supplemental CLF file created during LEF-in
with the auLoadCLF command.

To accommodate placement of single-height and multiple-height
standard cells or describe more than one placement tile, you need to
modify the standard cell library creation flow, defined in Creating a
Standard Cell Library on page 3-9, to do the following:
Modify the technology file to include the additional tile names.

- Use the cmDumpTech command (Tech File > Write To File) to
create an editable technology file.
- Add a new Tile section to the technology file describing the
additional tile.
- Use the cmReplaceTech command (Tech File > Replace) to
replace the technology file in the library.
After setting the place and route boundary (auSetPRBdry), use

the cmSetMultiHeightProperty command or choose Cell
Library > Multi Height Cell to generate a multiheight tile map.
Use the cmMarkLefSite command to map the tile names to the

cell masters. This command opens the Mark Cell Site dialog box.

3-42
Specify the following:

- Library Name: your_library
- Tile Name: new_tile_name
- Apply To: Select Cell Name and enter the cell master to which
the tile applies, or select File Name and enter the name of an
ASCII file that lists the cell masters.
Note:
When you define multiple placement tiles, you need to use
Physical Compiler for floorplanning and use the write_mdb
command to create a Milkyway library of the floorplanned design.

3-43

3-44
4
Creating a Design Library and Adding Data4
A design library is a design-level cell of a block or chip that is
implemented in Astro. You need to create a design library and add
other data to implement a design with Astro.
Creating a Design Library With a Verilog Netlist
Creating a Design Library With a VHDL or EDIF Netlist
Adding TLU or TLUPlus Capacitance Tables to a Design Library
Preserving Hierarchy and Generating Hierarchical Verilog Output
Loading Power Supply Information
Creating LOGIC Views
4-1

Use the auVerilogToCell command to automate creation of the
design library and top cell by doing the following:
Creating the design library, equivalent to using the

cmCreateLib command
Adding reference libraries, equivalent to using the cmRefLib

command
Reading in the Verilog netlist, equivalent to using the

auVerilogIn command
Expanding the netlist, equivalent to using the cmCmdExpand

command
Creating the top cell, equivalent to using the geOpenLib and

geCreateCell commands
Binding the netlist to the cell, equivalent to using the

axgBindNetlist command
Initializing hierarchy preservation, equivalent to using the

astInitHierPreservation command
To use the auVerilogToCell command for creating the design

library and top cell,
1. Change to the directory where you want to create the design
library and start Astro.
% cd path/my_design_lib
% Astro -cmd my_design.cmd -log my_design.log &
2. Enter auVerilogToCell.
The Verilog To Cell dialog box appears.
Chapter 4: Creating a Design Library and Adding Data
4-2
For this example design, the following was entered:

- Library Name: design
- Verilog File Name: super_watch.vg
- Output Cell Name: super_watch
- Tech File Name: designs.tlu.18.tf

4-3
- Set Case Sensitive: Enabled

- Initialize Hierarchy Preservation: Enabled
Enable options that are appropriate for your design. For example,
if you need to provide an HDL-to-GDSII cell type mapping file,
enter the file name in the HDL To GDSII Map File box.
3. Click Global Net Options. The Verilog To Cell dialog box with
global net options appears.
- Net Name: VDD

- Port Pattern: VDD
- Click Apply.

4-4
- Net Name: VSS

- Port Pattern: VSS
- Click Apply and click Hide to close the window.
4. Click Reference Library. The Verilog To Cell dialog box with
reference library options appears.
- Enter Reference Library: cb18os120.

- Click Add.
The reference library name you entered is now in the
Reference Libraries list.

4-5
- Add any additional reference libraries.

- Click Hide to close the window.
5. Click OK.
As the auVerilogToCell command is executing, messages
similar to the following are displayed:
Library design has been created successfully.
Technology file designs.tlu.18.tf has been loaded successfully!
VerilogIn: Reading Verilog file
*****
Verilog HDL translation! *****
*****
Start PASS 1 *****
(Please check the file for mapping Verilog to GDS cell)
** Cannot open map file. **
***** PASS 1 Complete *****
Elapsed =
0:00:01, CPU =
*****
0:00:00
Verilog HDL translation! *****

4-6
*****
Start PASS 2 *****
(Please check the file for mapping Verilog to GDS cell)
** Cannot open map file. **
Module inv0d0 was referenced in creating instance before definition.
Create hccell inv0d0 according to FRAM view.
Module nd02d0 was referenced in creating instance before definition.
Create hccell nd02d0 according to FRAM view.
Module oaim21d1 was referenced in creating instance before definition.
Create hccell oaim21d1 according to FRAM view.
...
Module bufbd7 was referenced in creating instance before definition.
Create hccell bufbd7 according to FRAM view.
*****
PASS 2 Complete *****
*****
Verilog HDL translation completed! *****
Elapsed =
0:00:02, CPU =
0:00:00
Verilog conversion completed.
Peak Memory Usage = 52 M,
Top Module Name
Verilog Translation Memory Usage = 23 M
(super_watch).
Expanding Top Module super_watch ...

Hierarchy Preservation is turned ON
The quick-attach skip-search mode has been turned on.
+++ Global net definitions. +++
Global Net VDDport pattern VDD
Global Net VSSport pattern VSS
Checking single pin net for cell 'super_watch.CEL' now...
Searching for any single pin nets...
Total number of cell instances: 2004
Total number of nets: 2057
Total number of ports: 171 (include 0 PG ports)
Total number of hierarchical cell instances: 32
The quick-attach skip-search mode has been turned off.
Elapsed =
0:00:01, CPU =
0:00:00
Expansion completed, 1 cells created.
Peak Memory Usage = 52 M,
Expansion Memory Usage = 0 M
auVerilogToCell completes successfully

4-7
Creating a Design Library With a VHDL or EDIF Netlist

To create a design library with a VHDL netlist,
1. Create the design library by using the cmCreateLib
2. Add reference libraries by using the cmRefLib command
3. Read in the Verilog netlist by using the auVerilogIn command
4. Expand the netlist by using the cmCmdExpand command
5. Open the design library by using the geOpenLib command
6. Create the top cell by using the geCreateCell commands
7. Bind the netlist to the cell by using the axgBindNetlist
command
8. Initialize hierarchy preservation by using the
astInitHierPreservation command
To create a design library with an EDIF netlist, perform the procedure
above, but substitute the auEDIFIn command in step 3.
Adding TLU or TLUPlus Capacitance Tables to a

Design Library
After you create a design library, you can add TLU or TLUPlus
capacitance tables to the library.
Astro uses a congestion-based coupling model and TLU or TLUPlus
capacitance tables to accurately model the prerouting capacitance
for nets prior to routing. This methodology eliminates the
questionable derivation of the linear capacitance coefficient and

4-8
improves the accuracy of the model by taking into account increases

in coupling capacitance due to increased congestion in different
regions of the chip or block.
TLU or TLUPlus capacitance tables are required for capacitances. If
TLU capacitance models do not exist, use Tools > Data Prep >
Techfile > Create Capacitance Model (cmCreateCapModel) to
build them from the process information. For more information about
TLU models, see Checking TLU Capacitance Model Parameters
on page 7-41.
TLUPlus uses Star-RCXT model generation to create capacitance
and resistance tables for extraction in Astro, as described in
Generating TLUPlus Capacitance and Resistance Models on
page 7-43. These models provide greater correlation between Astro
and Star-RCXT capacitance and resistance extraction than the
standard TLU models.
To add TLUPlus capacitance tables to the library,
1. Enter menuReload "astro_data_prep" or choose Tools >
Data Prep.
2. Enter cmItfToTLUPlus or choose Techfile > ITF to TLU+.
The Convert ITF to TLU+ dialog box appears.
Adding TLU or TLUPlus Capacitance Tables to a Design Library

4-9
3. Enter the following:

- Library Name: design
- Select LPE Mode: MIN, NOM, or MAX.
- Each LPE mode you select requires that you enter a file name
in the matching RCTable File box.
- Star-RCXT Mapping File: starXT018_6m.map
4. Click Sanity Check.
This checks for consistency between the Milkyway technology
file and the Interconnect Technology Format (ITF) file in the
following:
- The conducting layer names
- The etch values

4-10
- The width and minimum spacing values

- The conducting layer thicknesses
5. If the sanity check is successful, click OK.
This attaches a TLUPlus binary file to the LM view.
Preserving Hierarchy and Generating Hierarchical

Verilog Output
Hierarchical Verilog out is the process of regenerating a hierarchical
netlist from a flat layout design after the netlist changes are made by
place and route or ECO-related operations (such as optimization,
clock tree synthesis, scan chain optimization, and so forth).
Astro performs logic optimization on a flat representation of the
design. The hierarchical information of a design is represented as an
overlap and is annotated on the flat design. The data structure that
represents the flat design is called the common graph, and its
accompanying logic hierarchy overlap is called the hierarchical
common graph. You need to initialize this data structure with the
astInitHierPreservation command to enable Astro to output
hierarchical Verilog. Without this initialization step, Astro cannot
output hierarchical Verilog with the astDumpHierVerilog
command.
When Astro performs optimization, it must track the hierarchical
common graph to retain or update the module boundaries. If you
want to output the final, optimized design in a hierarchical netlist
form, you must initialize the hierarchical common graph by using the
astInitHierPreservation command at the outset, during the
data preparation stage. You can specify any modules that must be

4-11
preserved, such as the modules whose boundaries are not to be

altered with astMarkHierAsPreserved. Once marked as
preserved, the module instance does not allow creation or deletion
of any ports.
Note:
Be aware that clock tree synthesis and clock tree optimization are
exceptions to the rule; you might see extra ports on preserved
module instances after clock tree synthesis or clock tree
optimization.
When you run astInitHierPreservation, Astro creates the
hierarchical port information needed by commands such as
ataLoadSDC and astReportTiming.
Note:
It is recommended that you no longer use the
cmCreateHierPorts command to create the hierarchical port
information used for processing SDC. The hierarchy preservation
data structure produced with astInitHIerPreservation is
more complete. Simply replace the cmCreateHierPorts
portion of your command script with
astInitHierPreservationthis creates the data needed
for hierarchical SDC.
If there are problems during the initialize hierarchy preservation
process, you see a warning during SDC loading, such as
hierarchical port was not found, ignored.
The following hierarchy preservation commands are described later
in this chapter:
astInitHierPreservation (see Initializing Hierarchy

Preservation on page 4-16)

4-12
astMarkHierAsPreserved (see Marking Module Instances

As Preserved on page 4-18)
astDumpHierVerilog (see Generating Hierarchical Verilog

on page 4-19)
astRepairHierPreservation (see Repairing Hierarchy

Preservation and Deleting Hiconn Nets on page 4-23)
astDeleteHierPreservation (see Deleting Hierarchical

Preservation on page 4-28)
astDumpHierPeservation (see Hierarchical Preservation

Information on page 4-28)
astCheckHierPresConsistency (see Checking Hierarchy

Preservation Consistency on page 4-28)
In the Astro GUI, these commands, except for

astDumpHierPreservation and
astCheckHierPresConsistency, are in the Hierarchy
Preservation section of the Cell menu.
Useful Hints
When preserving hierarchy, consider the following points:
Do not use the EXP view when running

astInitHierPreservation; use the CEL and NETL views.
Remember to set the correct bus style for the library. If the bus
style is incorrect, Astro issues a warning when generating
hierarchical Verilog.
Use the Astro auVerilogIn command to read the original

Verilog netlist. Also, make sure the netlist is not bit-blasted. If the
original netlist has no buses, it is not possible to generate buses.

4-13
Invoke astInitHierPreservation before loading a TDF file

or performing any netlist changes and after saving the CEL view
after binding the expanded netlist.
Keep in mind that use of the astRepairHierPreservation

command can help when you use commands that manipulate the
database directly. For example, Scheme commands that add
cells or change the netlist might cause problems.
Save the cell prior to inserting the clock tree. That way you can
use the saved cell instead of using astDeleteClockTree to
remove the clock tree in case of problems. Deleting clock trees
sometimes causes problems.
Methodology for Preserving Hierarchy

For the processes listed in steps 1 through 3 of the methodology for
preserving hierarchy, you can use the auVerilogToCell
command. This command performs Verilog netlist input, flattening,
and binding to a CEL view, as well as hierarchy preservation. For
information about the auVerilogToCell command options, see
Creating a Design Library With a Verilog Netlist on page 4-2 and
Physical Implementation Online Help.
A typical hierarchy preservation flow includes these major steps:
1. Input the netlist by
- Reading in the Verilog description to create a NETL view. Use
auVerilogIn or auVerilogToCell.
- Expanding the netlist (NETL view) to create an EXP view. Use
cmCmdExpand or auVerilogToCell.

4-14
2. Create a cell by
- Creating a cell view (CEL view) and binding a netlist view (EXP
view). Use geCreateCell and axgBindNetlist or
auVerilogToCell.
- Adding cells not in the netlist, such as power and ground pads.
- Setting power and ground ports. Use aprPGConnect.
3. Initialize hierarchy preservation information. Use
astInitHierPreservation or auVerilogToCell.
See Initializing Hierarchy Preservation on page 4-16.
4. Mark the module instances in the design you want preserved.
Use astMarkHierAsPreserved.
See Marking Module Instances As Preserved on page 4-18.
5. Add cells not in the netlist, such as VDD/VSS pads.
6. Set power and ground ports. Use aprPGConnect.
7. Initialize timing information by loading timing constraints, using
SDC. At this point, the cell is ready for Astro optimization.
See Loading Timing Constraints on page 6-6.
8. Place and route the cell. Run the following
- Floorplanning
- Preplacement and in-placement optimizations
- Clock tree synthesis and clock tree optimization
- Postrouting and routing optimizations

4-15
9. Delete hiconn nets (nets that connect a module port and ports
outside of the module). Use astRepairHierPreservation.
See Repairing Hierarchy Preservation and Deleting Hiconn
Nets on page 4-23.
10. Generate a hierarchical Verilog netlist by using the
astDumpHierVerilog command.
See Generating Hierarchical Verilog on page 4-19.
11. Check the hierarchy preservation consistency. Use
astCheckHierPresConsistency.
See Checking Hierarchy Preservation Consistency on
page 4-28.
For information about preserving hierarchy for ECOs, see
Engineering Change Order Methods on page 12-22.
Initializing Hierarchy Preservation

The astInitHierPreservation command creates a
hierarchical common graph so that Astro can recognize the
hierarchical structure of the design. Without the hierarchical
common graph information, Astro is not be able to create a
hierarchical Verilog netlist.
Run astInitHierPreservation before loading the TDF file or
performing netlist changes and immediately after saving the cell
(after binding the expanded netlist).

4-16
To initialize hierarchy preservation,

1. Enter astInitHierPreservation or choose Cell > Hierarchy
Preservation Initialize Hierarchy Information.
The Initialize Hierarchy Preservation dialog box appears.
2. Select the options, depending on your requirements.

Note:
Because astInitHierPreservation only creates the
hierarchical common graph, not marking module instances (the
next step in the hierarchy preservation flow) is the same as not
marking any module boundaries. Do not mark module instances
if you want to generate a hierarchical Verilog netlist at the end but
do not care about new ports; the tool can then optimize across
the module boundaries.
Astro maintains the hierarchical common graph when hierarchy
preservation is initialized. Using astMarkHierAsPreserved
ensures that the hierarchical common graph does not create any
additional ports on the marked modules.

4-17
Marking Module Instances As Preserved

Use the astMarkHierAsPreserved command to preserve the
boundary of modules where you do not want optimization to add any
extra ports. Issue this command after
astInitHierPreservation (the hierarchical common graph
must exist for astMarkHierAsPreserved to work properly).
To mark the module instances in the design that are to be preserved,
1. Enter astMarkHierAsPreserved or choose Cell > Hierarchy
Preservation Mark Module Instances Preserved.
The Mark Module Instances Preserved dialog box appears.

You can selectively mark modules to be preserved.
4. Save the cell.

4-18
Generating Hierarchical Verilog

The astDumpHierVerilog command generates a hierarchical
Verilog netlist for a given flat cell (if the cell contains hierarchical
information). Use astInitHierPreservation to create this
hierarchical information. To generate hierarchical Verilog from the
expanded netlist view (EXP view), initialize hierarchy preservation on
cellName.EXP and then output hierarchical Verilog from
cellName.EXP.
To generate hierarchical Verilog,
1. Enter astDumpHierVerilog or choose Cell > Hierarchy
Preservation Hierarchical Verilog Out.
The Dump Hierarchical Verilog dialog box appears.

4-19
2. Select the options or keep defaults. Among the options are

- Must Dump Cell instance Master(s)
Specifies the cell master names for which all cell instances
must be generatedenter all the cell master names,
separated by a space (maximum allowed length is 1,023

4-20
characters), to override the following options: No Corner Pad

Cell instances, No Pad Filler Cell instances, No Core Filler Cell
instances, and No Unconnected Cell instances.
For example, consider a top cell with the following four types of
core filler cells: FILL1, FILL2, FILL4, and FILL8. To generate
hierarchical Verilog output with only FILL4 and FILL8
instances, select No Core Filler Cell instances and enter
FILL4 FILL8 into the Must Dump Cell instance Master(s) box.
The syntax is
astDumpHierVerilog
setFormField "Dump Hierarchical Verilog" "Flattened
Cell Name""top"
setFormField "Dump Hierarchical Verilog" "Hierarchical
Verilog File Name""top"
setFormField "Dump Hierarchical Verilog" "Must Dump
Cell instance Master(s)""FILL4 FILL8"
setFormField "Dump Hierarchical Verilog" "No Core
Filler Cell instances" "1"
formOK "Dump Hierarchical Verilog"
- No power/ground ports
Prevents power or ground ports from being generated for all
the cell instances, module instances, and module definitions,
including the topmost module. For each power or ground net in
a module, a power or ground port is generated for the module
instances and module definition. If such nets exist in the
original netlist, no new port is generated. However, these ports
from the original netlist can never be ignored and are always
generated, regardless of this switch.
- No power/ground nets
Prevents power and ground nets from being declared as
supply1 and supply0 nets in all the module definitions.

4-21
- No empty Cell Module Definitions

Suppresses the generation of empty module definitions for the
leaf-level cells, such as standard cells and hard IP. When this
switch is off, astDumpHierVerilog generates module
definitions for all the FRAM view-only cells that contain port
definitions but no cell instances.
- No Unconnected Ports
Prevents the generation of unconnected ports, including ports
on module instances, macro instances, and standard cell
instances.
- Strip BackSlash before hierarchy separator
Strips the backslash before the hierarchy separator. In almost
all cases, this option is on (the default).
- Output Wire Declaration
Generates wire declarations in the hierarchical Verilog output.
This option affects only scalar wires. For vector wires, a wire
declaration with vector limits is generated, regardless of this
option. Here is an example:
With Output Wire Declaration
wire 246;
wire [1:0] n245;
BUF U12 (.A( n245[0] ). .Y( n246 ));
Without Output Wire Declaration
wire [1:0] n245;
BUF U12 (.A( n245[0] ). .Y( n246 ));
- Generate macro definitions

Generate a hierarchical netlist from submodules that were
placed and routed in Astro.

4-22
If you initialized hierarchy on the submodule and are using

astDumpHierVerilog at the top level,
astDumpHierVerilog dives into that submodule and
works to output the hierarchical netlist for the submodule at the
same time. This is different from the Apollo tools use of
HNETs, in that no HNET is created or required ahead of time.
3. Click OK.
Repairing Hierarchy Preservation and Deleting

Hiconn Nets
The astRepairHierPreservation command corrects the
common graph hierarchy errors by updating the hierarchical
information. It does not preserve the module instance boundaries.
This means that new module ports might be created when
connections are made across the module boundaries.
Also, astRepairHierPreservation might change the flat net
names when the nets are connected to ports outside the module
scope. For example, a net sub1/sub2/net changes to sub1/net when
it is connected to sub1/cell_inst/D. In this example, sub1 and sub2
are module instances, cell_inst is a leaf-level gate instance, and D is
a port on cell_inst. If a net sub1/net already exists, the name might
change to sub1/net_0.
Common graph hierarchy errors can be caused by
Any netlist update done outside the common graph code, either
by use of ECO commands or by direct use of database
commands. For hierarchical ECO, see the Milkyway
implementation commands auHierECO and auHECOByFile.
Any defect in the common graph code.

4-23
Use the astRepairHierPreservation command to update all

netlist changes done with ECO commands, database commands,
and so forth. Do not use this command to fix common graph
hierarchy errors generated by preplacement, in-placement, or
postplacement optimizations or by clock tree synthesis and clock
tree optimization, because the common graph hierarchy errors might
have caused optimizations to terminate prematurely and the cell
could contain incomplete data. To check for hierarchy errors existing
in the CEL view, ensure that you run
astCheckHierPresConsistency in the CEL view before running
astRepairHierPreservation.
The astRepairHierPreservation command handles the
following types of netlist updates:
Creating new ports on the top module

Note:
You must set the correct direction for newly created ports on
the top module before running
Creating or deleting new nets and changing net connections
Adding or deleting cell instances
The astRepairHierPreservation command does not handle

the following types of netlist updates:
Changing names for nets or cell instances
Changing port directions
Deleting existing top module ports

4-24
The astRepairHierPreservation command works on a closed

cell only. It opens the cell to modify it and saves it at the end. If it is
successful in repairing all the common graph hierarchical errors, you
can reopen the cell and continue with the rest of the flow.
For single-port nets, the Astro hierarchical Verilog output process
preserves the net names. However, if the single-port net is a hiconn
net, PrimeTime has difficulty finding such nets. (A hiconn net, by
definition, is a net that connects a module port and ports outside of
the module.) To resolve this, you can delete hiconn nets connected
to single module ports when using the
astRepairHierPreservation command (see the following
procedure).
To repair hierarchical preservation,
1. Enter astRepairHierPreservation or choose Cell >
Hierarchy Preservation Repair Hierarchy Information.
The Repair Hierarchy Information dialog box appears.

4-25
2. Enter the flattened cell name for which hierarchical information is

to be updated.
3. Make sure Repair net connections and instances is selected.
- Select the Remove local hier nets option to clean the data for
local hierarchy nets that you want to load in IC Compiler. This
option removes all local hierarchy nets in a design. Do not
select this option while running the Astro flow.
- The Dry Run Logfile: box displays the file that is used to log
hierarchy repair operation.
You can select Delete hiconn nets connected to single module
port to delete all the hiconn nets that are connected to only one
module port instance; that is, there is a driver only and no fanouts
or only a fanout and no drivers in the module scope. Enabling this
option is useful for PrimeTime back-annotation, because
PrimeTime cannot find such nets.

4-26
You can select Remove feedthrus to avoid assign stmts in hvo

to clean the feedthrough hierarchy nets.
You can select Delete all unconnected hier ports and nets to
clean the dangling hierarchy ports (and related hierarchy nets
and ports).
The flow for generating correct hierarchical Verilog and Standard
Parasitic Exchange Format (SPEF) output files includes these major
steps:
1. Save and close the cell if it is already open.
2. Run the astRepairHierPreservation command. In the
Repair Hierarchy Information dialog box, do the following:
- Deselect the Repair net connections and instances option if
there are no connection errors in the cell.
- Select the Delete hiconn nets connected to single module
port option (useful for PrimeTime back-annotation, because
PrimeTime cannot find such nets).
- Click OK.
3. Generate a hierarchical Verilog output file and a SPEF output file
for use in back-annotation.
You can also use the astRepairHierPreservation command to
maintain hierarchy preservation after using the
auECOByChangeFile command to insert buffers and inverters,
rename cells, insert or remove cells, and insert or remove nets. For
hierarchical ECO, see the Milkyway implementation commands
auHierECO and auHECOByFile.

4-27
Deleting Hierarchical Preservation

The astDeleteHierPreservation command cleans up the
hierarchical information created by astInitHierPreservation
in the given flat, top cell. After hierarchy information is deleted, the
module boundary is not preserved and the hierarchical netlist cannot
be generated by astDumpHierVerilog.
Hierarchical Preservation Information

The astDumpHierPreservation command writes the following
information in the command window:
*
*
*
*
*
Hier
Hier
Hier
Hier
Hier
Cell
Port
Cell
Nets
Port
Masters *
Inst Masters *
Insts *
*
Insts *
Note:
Be aware that astDumpHierPreservation writes all
hierarchy preservation information to the log file; this output can
be quite large for some designs.
Checking Hierarchy Preservation Consistency

Use the astCheckHierPresConsistency command to check
whether the hierarchical common graph in the cell is consistent with
the flat common graph. This command works on the current open
cell and loads the common graph data (if it is not already loaded).
The astCheckHierPresConsistency command reports any
errors (differences) it finds.

4-28
Hierarchical Inout Port Direction

Set the cgRepairHierPortDirectionOfInoutPort variable
before running astRepairHierPreservation. This variable
prevents the inconsistency that arises when
astRepairHierPreservation does not change the direction of
ports connected to the hierarchy inout ports.
To set the cgRepairHierPortDirectionOfInoutPort
variable, enter
define cgRepairHierPortDirectionOfInoutPort 1
Dangling Ports Connected to Hierarchy Inout Ports

During optimization, there might be some dangling ports that are
connected to the hierarchy input ports. To handle such ports,
Check for the necessity of bidirectional (inout) ports. If they are

not serving as bidirectional, change them to unidirectional (in or
out) ports.
Set the cgHierInoutPortHierPreserve variable before

running astRepairHierPreservation if the declaration of
inout ports is necessary. Enter
define cgHierInoutPortHierPreserve 1

Crosstalk analysis can use power supply information loaded into
Astro. If this information is not provided, crosstalk analysis still works,
because it can be based on a voltage value, independent of supply
value. For multiple-voltage designs, it is recommended that you load
4-29
the power supply information to get accurate analysis, because

noise metrics are percentages of the power supply. For
single-voltage supply designs, the result is the same with or without
the supply loaded.
To load power supply information into Astro,
1. Enter poLoadPowerSupply or choose Power > Data
Preparation Load Power Supply.
The Load Power Supply dialog box appears.
2. Next to TDF File Name, enter the name of the TDF file containing
the power supply information.
Here is a sample TDF file:
tdfSetPowerSupply "VDD" 1.08 1.2 1.32

The LOGIC view is a way of connecting Astro and the Physical
Compiler tool. A brief description is included in this section for
more information, see the Physical Compiler documentation.

4-30
The geCreateLogicView command reads the library.db file and

creates a LOGIC view (subdirectory), where the Synopsys design.db
information is stored, in the Milkyway design library. Each CEL view
(flat) in the design library has one LOGIC view (hierarchical).
Use the geCreateLogicView command to bring hierarchical and
flat netlist information into one library instead of having files spread
out in different directories. This allows tools to access the
hierarchical and flat netlist information in the same location in the
same library.
To create LOGIC views,
1. Enter geCreateLogicView or choose Tools > Data Prep > Cell
Library > Create Logic View.
The Create Logic View dialog box appears.
2. Select the options, depending on your requirements. The options

are
- Library Name
Enter the name of the design library to which the LOGIC view
will be added.
4-31
- Design Cell Name

Enter the name of the cell you want to associate with the
design.db.
- db File Name
Enter the name of the .db file that you want to add to the design
cell, and click Add.
- DB To Delete
Enter the name of the .db file that you want to delete from the
named design cell, and click Delete. Click Select DB to show a
list of .db files that were added before.
To delete all logic .db files from the named library, click Delete
All.
3. Click OK.

4-32
5
Floorplanning and Connecting Power and
Ground
5
After you create the design library, you need to define the power and
ground connections, use floorplanning to create the boundary and
core area, and create the power and ground rings and straps.
Connecting Power and Ground
Floorplanning
Adding Power and Ground Rings
Adding Power and Ground Straps
Prerouting Standard Cells
5-1

The power and ground connections are typically not defined in the
netlist. To define these connections, you need to associate port
patterns on the standard cells or macros with a power or ground net.
To define power and ground connections,
1. Change to the design directory and start Astro.
2. Enter geOpenLib or choose Library > Open to open the design
library.
3. Enter geOpenCell or choose Cell > Open to open the top
design cell.
4. (Optional) To preserve the hierarchy of module instances, enter
astMarkHierAsPreserved or choose Cell > Mark Module
Instances Preserved.
Note:
Preserving the module instance hierarchy is recommended for
processing SDC timing constraints.
5. Enter aprPGConnect or choose PreRoute > Connect Ports to
P/G.
The Connect/Disconnect PG dialog box appears.
Chapter 5: Floorplanning and Connecting Power and Ground

5-2
6. Specify the following:

- Net Name: VDD
- Port Pattern: VDD
- Net Type: Power
- Update Tie Up/Down: Disabled
- Model: Connect
7. Click Apply.
A message dialog box appears.

5-3
8. Click OK.
This connects all VDD ports to the VDD net.
9. In the Connect/Disconnect PG dialog box, now specify
- Net Name: VSS
- Port Pattern: VSS
- Net Type: Ground
- Update Tie Up/Down: Enabled
Note:
You need to enable this option the last time you execute this
command to apply the tie-up and tie-down port information
for the entire cell. In a Verilog file, these are 1b1 and 1b0.
- Model: Connect

5-4
- Click OK in the Connect/Disconnect PG dialog box and OK in

the message dialog box.
This connects all VSS ports to the VSS net.
Floorplanning
It is recommended that you use JupiterXT for floorplanning. For
details about floorplanning with JupiterXT, see the JupiterXT Virtual
Flat Flow User Guide.
You can also use Physical Compiler for floorplanning and creating a
floorplan file, as described in Defining Multiple Tiles for Placement
on page 3-42.
Floorplanning
5-5
In Astro, you can create a simple floorplan that determines the size
of the design cell, creates the boundary and core area, and creates
wire tracks for placement of standard cells.
To create a floorplan in Astro,
1. With the design library and top design cell open in Astro, enter
axgPlanner or choose Design Setup > Floorplan Set Up
Floorplan.
The Floor Planner dialog box appears.
2. Enter the appropriate floorplanning options. For example,

- Core Utilization: 0.75
- Row/Core Ratio: 1.0
- Double Back: Enabled

5-6
- Start First Row: Enabled

- Flip First Row: Enabled
- Core To Left: 14
- Core To Right: 14
- Core To Bottom: 14
- Core To Top: 14
3. Click OK.
This creates the wire tracks, the boundary area, and the core
area.
If negative values are entered in the Core To Left, Core To Right,
Core To Bottom, and Core To Top boxes, wire tracks will cover the
entire core area (including the I/O pads) rather than end at the
I/O pads.
The standard cells are now ready for placement in the layout
window.
Floorplanning
5-7
Following is an example of the messages you will receive from Astro

after you run the axgPlanner command:
Start to create wire tracks ...
GRC reference (8400,8400), dimensions (5600, 5600)
Start to place pads/pins ...
Running IO Placement Refinement...
WARNING: Pins cannot be abutted to corner pad.

5-8
IO Placement Refinement Completed Successfully.

Place pads/pins successfully
INFO: top boundary has 4 sides.
INFO: 171 IO pins considered in the design.
INFO: There is no constrained pin.
INFO: resolving IO pin overlap.
INFO: Pin colon_3_4 is fixed or PG, not moved
INFO: Pin colon_1_2 is fixed or PG, not moved
INFO: there is no pin overlap in this design.
INFO: 165 pins moved.
INFO: successfully removed IO pin overlaps.
Planner Summary:
This floorplan is created by using tile name (unit).
Row Direction = HORIZONTAL
Control Parameter = Aspect Ratio
Core Utilization = 0.754
Number Of Rows = 45
Core Width = 252.56
Core Height = 252
Aspect Ratio = 0.998
Double Back ON
Flip First Row = YES
Start From First Row = YES
Planner run through successfully.
The wire tracks are not visible in the cell view. To see the text format
that includes the wire tracks, enter axgDumpFloorPlan or choose
Design Setup > Floorplan Dump Floorplan.
Following is a partial example of the wire tracks information:
;******************
;* Tracks
*
;******************/
define _cell (geGetEditCell)
axPurgeSingleRecordType _cell "track"
axPurgeSingleRecordType _cell "wire dir"
axCreateWireDirRecord _cell 16 #t
axCreateWireDirRecord _cell 18 #f
Floorplanning
5-9
axCreateTrackRecord _cell 16 #t 0.56
0.5600) '(280.5600 279.4400)
axCreateTrackRecord _cell 18 #t 0.56
0.5600) '(280.5600 279.4400)
axCreateTrackRecord _cell 18 #f 0.28
0.0000) '(280.2800 280.0000)
axCreateTrackRecord _cell 16 #f 0.28
0.0000) '(280.2800 280.0000)
0.56 499 '(0.0000

0.56 499 '(0.0000
0.56 501 '(0.2800
0.56 501 '(0.2800
...
axCreateTrackRecord _cell 31 #t 0.58 0.61
0.5800) '(280.5600 279.3500)
axCreateTrackRecord _cell 45 #t 0.58 0.61
0.5800) '(280.5600 279.3500)
axCreateTrackRecord _cell 45 #f 0.98 0.95
0.0000) '(279.3300 280.0000)
axCreateTrackRecord _cell 3 #f 0.98 0.95 294
'(279.3300 280.0000)
458 '(0.0000
458 '(0.0000
294 '(0.9800
'(0.9800 0.0000)

After floorplanning, you need to add power and ground rings.
To add power and ground rings,
1. With the floorplanned design cell open in Astro, enter
axgCreateRectangularRings or choose PreRoute >
Rectangular Rings.
The Create Rectangular Rings dialog box appears.

5-10
2. Specify the appropriate options. For example,

- Around: Core.
- Net Name(s): VDD, VSS
- L-Width: 5

5-11
- R-Width: 5
- B-Width: 5
- T-Width: 5
- L-Layer: 45
- R-Layer: 45
- B-Layer: 3
- T-Layer: 3
- Offsets: Absolute
- Left, Right, Bottom, Top: 1
- Extend: Enable all options, which makes it easy to run
Astro-Rail
3. Click OK.
Looking at the cell layout, you will see the power and ground rings
around the core.

5-12

5-13

After you add the power and ground rings, you need to add power
and ground straps.
To add power and ground straps,
1. With the floorplanned design cell open in Astro, enter
axgCreateStraps or choose PreRoute > Straps.
The Create Straps dialog box appears.

5-14

5-15
2. Specify the appropriate options. For example,

- Direction: Vertical
- Start X: 155.68, which is the approximate center of the
floorplan
- Net Name(s): VDD, VSS
- Width: 5
- Layer: 45
- Low Ends: At First Targets
- High Ends: At First Targets
3. Click OK.
Looking at the cell layout, you will see power and ground straps
for this example running vertically in the core area.

5-16

5-17

The axgPrerouteStandardCells command connects power
and ground pins in the standard cells to the straps and rings of the
power and ground mesh, and connects power and ground rails in the
standard cells. Use axgPrerouteStandardCells before
performing global routing so that the global router can recognize the
routing obstruction. Generally, this is done for all designs, unless you
already created these connections up front, using some other
method.
The axgPrerouteStandardCells command attempts to connect
objects, using the layers that you specify. When it cannot create a
connection that satisfies DRC, axgPrerouteStandardCells can
use other metal layers to jump over obstructions. Because this
approach can sometimes create connections that occupy routing
resources on critical layers, you might want to disable automatic
layer switching. To prevent connections with segments on metal
layers other than those specified, enter
axSetIntParam "preroute" "layerSwitching" 0
You can disable automatic layer switching for the

axgPrerouteInstances and axgCreateStraps commands
also.
To preroute standard cells,
1. Enter axgPrerouteStandardCells or choose PreRoute >
Standard Cells.

5-18

5-19
2. Select the options or keep defaults.

For descriptions of all the axgPrerouteStandardCells
command options, see Physical Implementation Online Help.

5-20
6
Setting Up the Design Timing
Before you can run Astro on your design, you need to set up the
design timing and prepare other data. Astro provides several
commands you can use for checking design data at various points in
the design flow.
Checking Design Data
Loading Timing Constraints
Unit Consistency
Astro Timing Setup
Dynamic Latch Analysis
Setting Clock Transition Defaults at the Clock Pins
Setting Net Transition Defaults for Nonclock Nets
6-1
Setting Maximum Capacitance and Transition Constraints on

Clock Domains
Setting Capacitance, Transition, and Delay Defaults for Nets
Chapter 6: Setting Up the Design Timing

6-2

Astro provides checking utilities that you can use to learn what might
need fixing in your design or what could help improve your design at
different stages of the design flow.
Use the astTimingDataCheck command to verify that timing

data is set up correctly. Run this command before generating a
timing report.
The astTimingDataCheck command reports the following
items:
- Unconstrained endpoints
- Primary inputs with no delay specified
- Register clock pins that are not connected to any clock signal
- Register clock pins that can be reached from multiple clock
signals
- Combinational loops
- Latch pairs with the same clock
- Generated clocks that are not driven by a master clock signal
- Master-slave latch pairs with different clocks that violate the
clock separation specified
- The number of significant digits for calculating clock separation
See Checking Timing Data on page 7-30.

6-3
Use the astCheckDesign command to check your design for

optimization at any phase of the design flow after placement. A
simple way to get a placed design is to run a quick placement
(astFastPlace) immediately after floorplanning.
The astCheckDesign command reports the following:
- Design information (number of instances, macros, pins, nets,
utilization and so forth)
- Timing information
- Operating conditions
- Optimization information
- SDC information
- High-fanout nets
- Dont touch nets
- Library information (cell type, resistance, delay, maximum
transition, maximum capacitance, and buffer area)
See Checking Timing and Optimization for the Design on
page 7-32.
Use the astCheckDesignForCTS command to check the data

relevant to clock trees in your design. Run this command before
performing clock tree synthesis.
The astCheckDesignForCTS command reports the following:
- Clock Tree Overview
- Sync/Ignore Pins
- Clock Domains Overlap

6-4
- Buffers/Inverters Used During CTS

- Delay Cells Used During CTS/CTO
- Dummy Load Cells Used During CTO
- LEQ Cells Used During CTO
- Dont Touch Cell Instances
- Dont Touch Clock Nets
- Clock Tree Constraints/Targets
See Checking Clock Tree Data in the Design on page 9-12
Use the axgCheckDesignForRoute command to check your

design and generate an error cell from which you can view errors,
enabling you to find problem areas in your design before you
perform routing. Run this command after the placement stage of
the design flow and before detail routing.
The axgCheckDesignForRoute command checks various
areas of your design, such as
- Pin access points
- Cell-instance wire tracks
- Pins out of bounds
- Minimum grids
- Pin design rules
- Blockages
See Checking the Design Before Routing on page 10-6.

6-5

Astro uses SDC commands to do timing analysis.
Note:
The initial release of Astro had ata commands that corresponded
to equivalent SDC commands. Now timing commands must use
SDC syntax, and the ata timing commands with equivalent SDC
commands have been removed.
Load the same SDC that you used in PrimeTime, but do not load the
file blindly. Often constraints used for final timing verification or initial
synthesis are not appropriate at all stages of physical optimization.
For example, it is not correct to set propagated clocks or allow data
and clock mixed paths prior to building the clock tree. Other
examples include the use of case analysis.
Keep the following points in mind:
Avoid loading SDC generated by the write_sdc command,

which expands the constraints. It is better to load SDC with
wildcards into Astro than an expanded SDC.
Run astInitHierPreservation prior to loading the SDC file.

This ensures that SDC specified for hierarchical ports that would
disappear during flattening are properly considered.
Before clock tree synthesis, remove or comment out

set_propagated_clock statements from the SDC file, or
disable propagated clocks by selecting Ignore Propagated Clock
in the Environment page of the AstroTime Timing Setup dialog
box.

6-6
Note which signals have case analysis attached to them in the

SDC file. Case analysis is commonly used to set an operating
condition of the chip for timing sign-off when the chip is complete.
At the beginning of the design process, set_case_analysis
might need to be modified.
Figure 6-1 is an overview of the SDC timing constraint flow.

6-7
Figure 6-1
SDC Timing Constraint Flow

Astro
place and route
cell
Contains expanded
netlist bound to cell
Preserve hierarchy (if desired)

Cell > Initialize Hierarchy Information (astInitHierPreservation)
Cell > Mark Module Instance Preserved (astMarkHierAsPreserved)
Add cells, perform floorplanning,
connect power and ground,
connect power supplies
Load timing constraints
Timing > Load SDC (ataLoadSDC)
Comment out set_propagated_clock.
Write timing constraints

Timing > Dump Timing Constraints (ataWriteTC)
Set up timing
Timing > AstroTime Timing Setup
(atTimingSetup)
Set astCells
astSetClockCell, astSetDelayCell,
astSetDontUse
File of SDC commands

Set capacitance model to TLU/TLU+ (Parasitics
page), set net delay model to Medium Effort
(Model page), deselect Run Time PVT Setting
(Library page), and set thresholds (Optimization
page).
Specify clock buffers, delay cells,
dont use, and so forth.
Check timing
Timing >Timing Data Check (astTimingDataCheck)
Write design constraints

Timing > Write Design Constraints (astWriteDC)
Check design
astCheckDesign
Design feasibility

6-8
File of ast commands
Currently, cell must be

placed for this to run.
Perform after preplacement optimization.
Loading Synopsys Design Constraints

You can load a file of SDC commands or load individual SDC
commands. (The SDC information is stored in the CEL view.)
To load a file of SDC commands,
1. Enter ataLoadSDC or choose Timing > Constraints Load SDC.
The Load SDC dialog box appears.
2. Next to SDC File Name, enter the name of the SDC file to be
loaded.
3. Set the options or keep defaults.
For descriptions of the ataLoadSDC command options, see
4. Click OK.

6-9
Note:
Astro cannot load an SDC file that uses the [%d] bus naming
style when the library has the bus naming style set to <%d>. To
solve this problem, use the following syntax in your Scheme
script:
sdc "set enable_bus_name_mapping 1"
To load individual SDC commands,
At the system prompt, enter sdc commands. The syntax is

sdc "sdcCommandSyntax"
Here is a sample of sdc commands to be loaded:

sdc
{ 0
sdc
sdc
"create_clock -name {clk} -period 5.6 -waveform

2.8 } [list {clk} ]"
"set_propagated_clock {*}"
"remove_clock_uncertainty {*}"
Make sure the argument in the sdc command is a valid string.

The following syntax is invalid (clk breaks the string into pieces):
sdc "create_clock -name "clk" -period 5.6 -waveform
{ 0 2.8 } [list {clk} ]"
This syntax is valid:

sdc "create_clock -name \"clk\" -period 5.6 -waveform
{ 0 2.8 } [list {clk} ]"
Note:
The tcl "sdcCommandSyntax" syntax is obsolete. Use sdc
"sdcCommandSyntax" instead. Scripts using tcl
"sdcCommandSyntax" still work, but Astro issues a warning
message.

6-10
Writing Timing Constraints

To write timing constraints,
1. Enter ataWriteTC or choose Timing > Constraints Write
Timing Constraints.
The Write Timing Constraint dialog box appears.
2. Enter a file name to write a file with SDC commands (see

Example 6-1).
You can also write a file that includes non-SDC commands, such
as ataSetNetCapTransAndDelayTime (see Example 6-2).
3. Click OK.
Examples
Example 6-1 Sample SDC Constraints File
# clock definition
create_clock -name "clk" -period 6 -waveform { 0 3 } [list {clk}
# clock latency
set_clock_latency
set_clock_latency
set_clock_latency
set_clock_latency
-min
-min
-max
-max
-rise
-fall
-rise
-fall
2.33 { {clk} }
2.33 { {clk} }
5.9 { {clk} }
5.9 { {clk} }

6-11
# clock uncertainty
set_clock_uncertainty -setup 0.15 {clk}
set_clock_uncertainty -hold 0.15 {clk}
# clock transition
set_clock_transition
-min
-min
-max
-max
-rise
-fall
-rise
-fall
0.1
0.1
0.1
0.1
{
{
{
{
{clk}
{clk}
{clk}
{clk}
}
}
}
}
Example 6-2 Sample File With Appended Non-SDC Constraints

#### Default Net Transition Capacitance and Delay Value/ NON SDC Constraints ####
#### format : (minRise, maxRise, minFall, maxFall) ####
##Net Name : netNameHere
#net_transition : (1, 1, 1, 1)
#net_capacitance : (1, 1, 1, 1)
#net_delay : (1, 1, 1, 1)
Note:
In the initial release of Astro, the ataWriteTC command wrote
ata commands. Now these ata commands are obsolete. When
you write constraints from a design started in the initial release
version of Astro, you should see messages such as the following,
showing conversion to SDC:
SDC:
SDC:
SDC:
SDC:
Reading SDC for cell 3

Create SDC for cell 3
Converting existing ATA to SDC
Dump SDC for cell 3
Modifying SDC Commands

To load minor updates such as setting clock propagation, purging all
clock uncertainty, and so forth, either load an SDC file with those
items only or use the following syntax: sdc "SDCcommandName".
For more information, see Loading Synopsys Design Constraints
on page 6-9.

6-12
For major changes to the SDC file or to reload the original SDC file
with some modifications, first use ataRemoveTC and then use
ataLoadSDC to load the SDC file. The ataRemoveTC command
completely removes the existing SDC constraints prior to loading the
new SDC file.
Be aware that loading a new SDC does not necessarily overwrite the
existing constraint. If you want to change an existing constraint,
either follow the procedure for major changes (listed in the preceding
paragraph) or use the appropriate SDC syntax to remove the
constraint (usually syntax that begins with remove_) and then load
the new constraint. Remove unwanted constraints because Astro
observes the most limiting constraint when multiple constraints exist
for the same object.
Note:
You cannot remove partial path exceptions from your constraints
by using SDC syntax such as remove_path_exception. The
Astro remove command removes all of them. Instead, save the
SDC, modify it, remove the old SDC information by using
ataRemoveTC, and then load the modified SDC.
Backward Compatibility of SDC Commands

Astro can read SDC commands loaded in a previous version of
Astro, but there is no guarantee that constraints loaded in a new
version of Astro will work if the design is opened in a previous version
of Astro. This is because with each version of Astro, the SDC reader
is updated and additional support is provided. The SDC attached to
the design in newer versions might not be compatible with previous
versions.

6-13
If you must go back to a previous version of Astro and the tool reports
a corrupted or invalid SDC file attached to the design, do the
following: In the older version of Astro, use ataRemoveTC to remove
all constraints and then use ataLoadSDC to reload the SDC file. The
following sample log file reports incompatibility when a design was
opened in a previous version of Astro:
SDC information is not backward compatible
SDC stored is version X, while this executable can only read
up to Y.
Reload the SDC files.
Failed to read sdc data
Writing ast Design Constraint Commands

You can write ast commands to a file, such as one used to specify
clock buffers, delay cells, and dont use cells. You can set the
following attributes:
astSetClockCell
astSetDelayCell
astSetDontUse
astSetDontTouch
astSetSizeOnly
astSetLevelShifter
astVoltageGroup (for optimization)
To write design constraints,

1. Enter astWriteDC or choose Timing > Write Design
Constraints.

6-14
The Write Design Constraints dialog box appears.
2. Do one of the following:

- Enter a file name to write a file with ast-type design constraint
commands (see Example 6-3).
- Enter a file name, and select Internal Constraints to write a
report with implicit constraints generated by Astro (see
Example 6-4).
3. Click OK.
You can make a file of the commands, as shown in Example 6-3, to
customize Astro optimizations.

6-15
Example 6-3 Sample ast Design Constraints (Default) File

; design constraints defined in library:
; (dont_use & dont_touch attribute)
astSetDontUse "cload1"
astSetDontTouch "cload1"
astSetDontTouch "adiode"
; design constraints defined on DB cell instances:
; (dont_touch & preserve_logic attribute)
; design constraints defined on DB nets:
; (dont_touch & preserve_logic attribute)
; design constraints defined on cell masters:
; (dont_use, clock_cell, delay_cell, voltage_group, level_shifter attribute)
astSetClockCell "bufbd3"
astSetClockCell "bufbd1"
astSetDelayCell "dl03d1"
Note:
Use astRemoveDC to remove all design constraints, such as the
astSetClockCell, astSetDelayCell, astSetDontTouch,
astSetDontUse, astSetLevelShifter, and
astSetPreserveLogic commands.
Example 6-4 Sample File With Internal Constraints
I io_if/io_decode2/inv0d0_Q5266 (inv0d0) NotBypass
N io_if/io_decode0/G4819 NotBreak NotBypass
N io_if/O1956 NotDelete
Unit Consistency
Design units (resistance, capacitance, timing, voltage, power, and so
forth) come from technology information in design libraries. When
units that differ from those in the design library are used in defining
the constraints in the SDC file, the constraints interpretation can be
affected by the mismatched units, producing unexpected results.
6-16
To prevent this mismatch, Astro provides a way to explicitly specify

the units used in defining the constraints and also performs unit
consistency checking against design libraries when constraints files
are being loaded.
Specifying Units in the SDC File

Use the set_units SDC command to explicitly specify the units
used in defining the constraints in the SDC file. The syntax is
set_units -resistance
<Ohm|kOhm|mOhm|MOhm|10Ohm|100Ohm|<floating><unit> >
-capacitance
<F|fF|pF|nF|uF|mF|10fF|100fF|<floating><unit>>
-time
<s|fs|ps|ns||us|ms 10ps|100ps >
-voltage
<V|fV|pV|nV|uV|mV|10mV|100mV>
-current
<A|fA|pA|nA||uA|mA|10uA|100uA|10mA|100mA>
-power
<W|fW|pW|nW|uW|mW|10uW|100uW|10mW|100mW|10pW|100pW|10nW|100nW>
Capacitance and resistance can accept a floating number unit. For

example,
set_units resistance 0.5kOhm capacitance 2pF
The set_units command is supported only as an SDC command.

Note:
If the SDC file that contains set_units syntax comes from
PrimeTime version Y-2006.12, you need to regenerate the file
with PrimeTime version Y-2006.12-SP1 to make it compatible
with Astro.
Unit Consistency
6-17
Checking Unit Consistency

Astro checks unit consistency against design libraries when
constraints files are being loaded. If conflicts are found, an error
message is issued; however, the rest of the timing constraints are
loaded. This consistency check is triggered when you load
constraints, using any of the following commands: ataLoadSDC,
read_sdc, source sdc_file, and
read_sdc -galaxy.
Reporting Design Unit Information

Use the report_units Tcl command to report the units stored in
the Milkyway design database. Here is a sample report:
****************************************
Report : units
Design : fp
Version: Z-2007.03-APF-BETA2 for IA.32
Date
: Tue Jan 30 03:39:24 2007
****************************************
Units
----------------------------------------capacitance
-resistance
-time
-voltage
-current
-power
:
:
:
:
:
:
pF
kOhm
ns
V
mA
mW
Writing Out Design Unit Information

Use the write_sdc Tcl command or ataWriteTC Scheme
command to write out the design units in the SDC file. In the SDC
file, the design units are written out with the set_units command.
6-18
Astro Timing Setup

The AstroTime Timing Setup dialog box is a convenient place to
control the operation of the timing analysis, extraction, optimization,
and crosstalk parameters for your design.
To open the AstroTime Timing Setup dialog box,
Choose Timing > AstroTime Timing Setup or enter

atTimingSetup.
The AstroTime Timing Setup dialog box appears.
The AstroTime Timing Setup dialog box includes these tabs:
Environment Sets environment options for timing analysis and

optimization.
See Environment Page on page 6-20.
Optimization Sets placement legalizer options, controls the use

of logic equivalency for cells, and controls certain optimization
settings.
See Optimization Page on page 6-31.
Library Sets the process, voltage, and temperature (PVT)

values under which timing analysis and optimization are run.
See Library Page on page 6-37.
Parasitics Sets the parasitic source, layout parasitic extraction

mode, and the capacitance model for timing.
See Parasitics Page on page 6-38.
Astro Timing Setup

6-19
Model Sets the cell delay model information and the net delay
model to be run for timing.
See Model Page on page 6-42.
Xtalk Sets the crosstalk circuit model and specifies filtering

thresholds and global noise thresholds to be honored in both
crosstalk analysis and crosstalk fixing.
See Xtalk Page on page 6-45.
The settings on these tabs are saved (except for the Ignore
Interconnect option on the Environment page) when the cell is
saved. You can use the AstroTime Timing Setup dialog box or the
astCheckDesign command to see the current settings stored in
the cell.
Note:
Equivalent ata commands are referenced in the following
descriptions, when available.
Environment Page
Use the Environment page to easily access the parameters that
affect timing analysis and optimization. You can use the default
settings, which provide the most-typical selections needed for
optimization, or change the settings to meet your objectives.
You might need to change some default settings to achieve
correlation with the Synopsys timing analyzer tool, PrimeTime. In
some cases, the defaults for Astro and PrimeTime might differ (for
example, some default settings in PrimeTime are not good for
optimizing the netlist). Also, the Astro default settings override the

6-20
corresponding SDC settings that do not need to be enabled at all

times in the flow (typically, you load the same SDC that is used for
PrimeTime timing verification).
To select environment options that affect timing and optimization,
1. Open the AstroTime Timing Setup dialog box (atTimingSetup)
and click the Environment tab.
The Environment page appears.
Astro Timing Setup

6-21
2. Select the options or keep defaults. The options are:

- Ignore Interconnect Ignores all parasitic wire capacitance
during timing. Cell loading capacitance is included. The default
is off.
Use this option to generate timing reports prior to placement
(useful for debugging timing reports); moreover, the reports
are generated quickly. This setting is not saved when the cell
is saved.
The equivalent ata commands are
ataIgnoreInterconnect and
ataIncludeInterconnect.
- Enable Time Borrowing Enables time borrowing, which
works to lessen the constraints on successive latch-based
paths during timing. The default is on.
There is no equivalent ata command. You can use the following
syntax to specify an argument (use 1 to activate, 0 to disable):
atCmdSetField "Enable Time Borrowing" "1" or "0"
Use the ataSetTimeBorrowMethod command to set the

time borrowing method you want to use during optimization.
The syntax is
ataSetTimeBorrowMethod ["standard"|"balanced"|"none"]
where standard specifies a method that borrows as much

time as it can for each latch; balanced specifies a method
that tries to equalize the slack between begin- and end-slacks
of the latch, resulting in better worst negative slack (WNS); and
none specifies no time borrowing. The balanced method will
not balance positive slacks.

6-22
- Enable Preset/Clear Arcs Sequential elements have

asynchronous preset and clear inputs, which when asserted,
override the clock and data inputs and force the outputs to the
steady state levels of 1 and 0, respectively. This option enables
asynchronous preset and clear timing arcs. The default is off
(not needed during initial optimizations).
This is the same as the set
timing_enable_preset_clear_arcs SDC command.
ataEnablePresetClearArcs and
ataDisablePresetClearArcs.
- Enable Recovery/Removal Arcs Enables checking for
recovery and removal of asynchronous timing arcs. The default
is off (typically not needed at the beginning of the
optimization).
ataEnableRecoveryRemovalArcs and
ataDisableRecoveryRemovalArcs.
- Enable Mixed Clock/Signal Edges Evaluates data-and-clock
mixing. Normally this option is off (the default) until after clock
tree insertion and then activated for postplacement
optimization. In PrimeTime it is on by default, but that does not
make sense prior to clock insertion, because unbuffered clock
trees contained in the datapaths make timing seem bad. Once
the clock tree is inserted, the capacitance, transition, and delay
along the path are realistic.
Data-and-clock mixing occurs when a valid clock source can
be traced to a valid data end pin. Usually, you want to evaluate
this after clock tree synthesis buffers the clocks. Note that case
Astro Timing Setup

6-23
analysis can affect seeing data-and-clock mixing paths,

because paths are determined by MUXs or feedback paths in
pads in various modes.
To see if you have data-and-clock mixed circuits, do the
following: write a timing report with all paths (set the slack
threshold to 10,000); then set mixed edges on, generate the
same report, and compare the two files.
ataSetDisableMixedEdges and
ataUnsetDisableMixedEdges.
- Enable Scan Enable Enables the scan edge during timing
analysis. This option overrides SDC false path and case
analysis for the scan enable and allows preplacement
optimization to perform high-fanout net synthesis on this net.
The default is on.
The equivalent ata commands are ataEnableScanEnable
and ataDisableScanEnable.
- Enable Inter Clock Enables timing for interclock domain
paths. When this option is deselected, you can effectively treat
all interclock domain paths as false paths. The default is on.
The equivalent ata commands are ataEnableInterClock
and ataDisableInterClock.
- Enable Default Clock Instructs the tool to consider each input
as being connected to a default clockthe default clock has
the same frequency and phase as the endpoint constraining
clock, and the input delay is set to 0. This behavior is the same
as the default in PrimeTime. If you do not want to time this type
of path (input pin --> logic --> flip-flop) when no input delay is
specified, deselect this option. The default is on.

6-24

ataEnableDefaultClock and
ataDisableDefaultClock.
Outputs do not have a default clock. To constrain outputs, use
the appropriate SDC syntax. For example, the following syntax
sets a default virtual clock to all outputs:
sdc "create_clock -name AVANT_VIR -period 25.12
-waveform { 0.000000 12.56 }"
sdc "set_output_delay -clock {AVANT_VIR} 0 {*}"
- Include Library Max Tran Includes the maximum transition

specified from the library. The default is on.
The equivalent ata command syntax is
ataIncludeLibMaxTran #t or #f (#t to activate, #f to
disable).
- Include Library Max Cap Includes the maximum capacitance
specified from the library. The default is on.
The equivalent ata command syntax is
ataIncludeLibMaxCap #t or #f (#t to activate, #f to
disable).
- Enable Multi-Clocks Per Reg Enables the Astro timer to
analyze in the presence of multiple clocks per register,
improving correlation between the Astro timer and PrimeTime.
The default is on.
When a sequential device is driven by different clocks, you can
choose to either restrict the analysis to one clock at a time or
allow Astro to analyze both clocks at the same time. In the
latter case, Astro analyzes all clocks in a single analysis run,
and reports all possible interactions between different clocks
(subject to any restrictions you specify such as false paths or
Astro Timing Setup

6-25
case analysis). The total time for analysis of all clocks is

reduced because multiple runs can be combined into a single
run.
- Enable CRPR Enables the clock reconvergence pessimism
removal process. This process works to remove artificially
induced pessimism from a timing report between a launching
and capturing device, and is mostly applicable for on-chip
variation considerations. The default is off.
- Enable Data To Data Check Enables checking for setup and
hold constraints between two data signals. The constraints are
obtained from the library, or they can be specified by using the
set_data_check SDC command. The default is on.
- Ignore Clock Uncertainty Ignores any
set_clock_uncertainty SDC commands contained in the
database. Enabling this option provides an easy way to
globally ignore all of these commands instead of removing
them one by one with SDC commands. The default is off.
syntax to specify an argument (1 to activate, 0 to disable):
atCmdSetField "Ignore Clock Uncertainty" "1" or "0"
- Ignore Propagated Clock Ignores any

set_propagated_clock SDC commands contained in the
database. It is useful to ignore propagated clocks before you
perform clock tree synthesis and then include them after clock
tree synthesis. Enabling this option provides an easy way to
globally ignore all of these commands instead of removing
them one by one with SDC commands. The default is off.

6-26
Disable this option after clock tree synthesis, when you want to
propagate clocks to get timing information about the clock
paths.
Note:
If set_propagated_clock SDC commands are not
specified, deselecting the option will have no effect (the ideal
clock values will be used).
atCmdSetField "Ignore Propagated Clock" "1" or "0"
- Set IO Clock Latency Computes, for every I/O port, the clock
latency to that port that provides the minimal clock skew on the
I/O port. For example, when the input --> three fanouts, Astro
checks the clock arrival time at all the fanouts and selects the
minimum value. (Astro selects the maximum for output ports.)
The default is off.
atCmdSetField "Set IO Clock Latency" "1" or "0"
- Enable Ideal Network Delay Enables ideal network delay to

be used for input and output ports when clocks are
propagated. The default is on.
You must set this option correctly prior to optimization to avoid
a large shift in slack when comparing propagated clock timing
with ideal timing. It is recommended that you review the timing
report with propagated clocks activated to verify that the
expected paths will be optimized. For more information, see
Setting Ideal Network Delay (Clock Latency) on page 6-30.
Astro Timing Setup

6-27

ataEnableIdealNetworkDelay and
ataDisableIdealNetworkDelay.
- Enable Clock Gating Checks Enables the checking of clock
gating. The default is off.
The equivalent ata commands are ataEnableGatingClock
and ataDisableGatingClock.
- Enable CrossTalk Effects Enables crosstalk-induced delay
effects during timing. The default is off.
Use this option to include or exclude the effects of crosstalk on
timing analysis when track assignment or detail routing is
complete. When it is selected, timing analysis automatically
considers crosstalkthere is no need to run the
xtXTalkAnalysis command. When you use real clocks
(propagated), crosstalk-induced delay on the clock network is
included in the timing report. When Enable CrossTalk Effects
is selected, postroute optimization optimizes for timing,
including the crosstalk effect. If you are using a parasitic view,
be sure to store the coupling mesh when the parasitic view is
generated, to analyze crosstalk with parasitic view. For more
information, see Creating Parasitic Views on page 13-13.
Note:
You do not need to select Enable CrossTalk Effects to report
or fix static or switching noise violations.
The equivalent ata commands are ataIncludeXtalk and
ataIgnoreXtalk.
- Load Useful Skew From DB Loads useful skew budget
values stored in the database during timing. This means that
timing and optimizations use the estimated useful skew
previously calculated by the tool. The default is off.
6-28

atCmdSetField "Set Useful Skew" "1" or "0"
- Include Non Propagated Nets Instructs the timer to calculate

transitions on nets that are not constrained by a setup or hold
constraint. For example, if a disable arc is used to disable an
edge, Astro finds a transition violation (if it exists) on the
disabled edge; when this option is deselected, Astro does not
search for a transition violation. The default is on.
ataIncludeNonPropagatedNets and
ataIgnoreNonPropagatedNets.
- Include SyncPort PhaseDelay Includes sync port delay
information from the .db file during timing. The default is on.
- Enable Trace Mode Enables the trace mode, allowing you to
trace on certain nets. The default is off.
- Include IO Path Includes paths related to boundary ports
during timing analysis and optimization. The default is on.
3. Click Apply.
ECS and Slew Degradation

ECS and slew degradation are used by default in Astro. You can
change this behavior by enabling ATA_SLEW_OFF and
ATA_ECS_OFF (1 is on, 0 is off). For example,
define ATA_SLEW_OFF 1
define ATA_ECS_OFF 1
Astro Timing Setup

6-29
Setting Ideal Network Delay (Clock Latency)

When the clock triggered on a boundary port is a propagated clock,
use ataEnableIdealNetworkDelay to force Astro to use the
ideal network delay for the boundary port. The
ataDisableIdealNetworkDelay command forces Astro to use
0 for the network delay of the boundary port.
In Astro, the ideal network delay is defined by the clock latency in the
SDC file, but this definition does not follow the default behavior in
PrimeTime. For example, the following SDC syntax produces
different timing results in PrimeTime for the related I/O:
set_clock_latency -max 0.9[get_clock {clk}]
set_clock_latency -max 0.9[get_ports {clk}]
In Astro you get the same answer for either syntax. For a boundary
constraint such as the following:
set_input_delay 1 -clock [get_clocks {clk}] -add_delay
[get_ports {lap}]
You get 0.9 ns in the network delay field of the timing report, if youre
using ataEnableIdealNetworkDelay, as shown below.
Clock Network delay
0.9000
20.9000
Using ataDisableIdealNetworkDelay, you get 0 ns in the

network delay field of the timing report, as shown below.
Clock Network delay (propagated)

6-30
0.0000
20.0000
Set this switch to control how the circuit is timed. You can also control
this switch by selecting or deselecting Enable Ideal Network Delay in
the Environment page of the AstroTime Timing Setup dialog box. In
PrimeTime, you control it with the clock latency command, by using
the get_clock or get_port command syntax.
In other words, the network delay for the launching flip-flop and the
capturing flip-flop is accounted for, except at the boundaries, where
the set_output_delay boundary constraint usually does not
account for the network delay of the imaginary capturing flip-flop
outside of the block. This is a way to add or not add the network delay
back for the imaginary capturing flip-flop on the other side of the
input or output pin.
Optimization Page
Use the Optimization page to control certain aspects of optimization.
For example, you can optimize parameters or set certain targets and
thresholds. In addition, you can use this page to control the use of
logic equivalency for cells and to set placement legalizer options.
The Optimization page does not have direct equivalent commands
for setting options like the ata commands associated with the
Environment page. Instead, you can use a command file to specify
Optimization page options, as shown in Example 6-5.
Astro Timing Setup

6-31
Example 6-5 Sample Optimization Command File

atTimingSetup
atTimingSetupGoto "Optimization"
;atCmdSetField "Optimization Task" "setup"
;atCmdSetField "Optimization Task" "hold"
;atCmdSetField "Optimization Task" "maxtran"
;atCmdSetField "Optimization Task" "maxcap"
;atCmdSetField "Optimization Task" "maxtran maxcap"
atCmdSetField "Optimization Task" "setup maxtran maxcap hold"
atCmdSetField "Ignore User LEQs" "1"
atCmdSetField "Merge Library LEQs" "1"
atCmdSetField "Optimization Target Setup Slack" "0.1"
atCmdSetField "Optimization Target Hold Slack" "0"
atCmdSetField "Optimization High Fanout" "40"
atCmdSetField "Optimization Max Transition" "2"
atCmdSetField "Optimization Max Capacitance" "2"
atCmdSetField "Optimization Target Utilization" "50"
atCmdSetField "Optimization Max Utilization" "95"
atCmdSetOptModel
To select the options that affect optimization,

and click the Optimization tab.
The Optimization page appears.

6-32

- You can choose the engine to be used during the placement
legalizing process (Auto, OV inc, or ECO Place), or specify
that the placement legalizing process not be run (None).
Auto Uses the default engine.
OV inc Uses the overlap removal engine. During initialization,
Astro analyzes the design to determine whether row-based
overlap removal or area-based overlap removal is most
beneficial.
Astro Timing Setup

6-33
You can direct Astro to use window-based overlap removal,

which is a combination of row-based and area-based overlap
removal by setting the following parameter:
axSetIntParam "apl" windowOV 1
To return to the default of row-based or area-based overlap

removal, set the parameter to the following:
axSetIntParam "apl" windowOV 0
Cell movement and the size of the window for window-based

overlap removal are determined by the cost of the following:
the ECO weight; the space penalty of the cell size compared
to the available space in a row; the distance between the new
placement location and the original anchor placement location;
and the direction of movement from the anchor placement
location.
ECO Place Uses the ECO place engine.
None The placement legalizer will not be executed.
- You can set the following Library LEQ options:
Ignore User LEQs Instructs Astro to build logic equivalent cell
information at runtime instead of using the logic equivalent cell
information in the reference libraries.
Merge Library LEQs Instructs Astro to merge logic equivalent
cell information across reference libraries. For example, if a
2-input AND gate is contained in both a high-speed (higher
power) and a low-speed (lower power) library, this setting
allows Astro to substitute a high-speed AND gate for a
low-speed AND gate (and vice versa).
Case Insensitive LEQs Specifies case insensitivity for all
named objects in the logically equivalent cell classes.

6-34
Merge User LEQs Instructs Astro to merge user-specified

logically equivalent cell classes with those classes extracted
by Astro. If not selected, the user-specified logically equivalent
cell classes are kept intact.
Detailed Message Report Prints information, such as the
current worst path, at each optimization step. This built-in
debugging capability helps you identify the reasons violations
cannot be fixed.
- You can enter values for the following parameters:
Target Setup Slack and Target Hold Slack Sets the final slack
that Astro tries to achieve.This is particularly effective when the
design is overconstrained (you can relax the clock) or
underconstrained (you can increase the timing margin without
adjusting the clock). These parameters are useful for changing
the effective clock period by a small amount.
High Fanout Threshold Sets the number of fanouts required
before Astro considers a net to be a high-fanout net during
high-fanout optimizations. The default number is 40.
In addition, high-fanout nets should typically be ignored during
placement, so that they do not unduly influence the placement
(by pulling the instances on the high-fanout net together).
Fanouts greater than 40 are ignored by the placer. Do not set
this value too low in an effort not to influence the placement.
Note:
During preplacement optimizations, large high-fanout nets
are ignored during placement for clustering (that is, the
clustering of loads is not influenced by the high-fanout net
connections). This gives the tool knowledge about the
number of buffers needed, which affects area and routability.
Immediately after placement, in phase 1 of postplacement
Astro Timing Setup

6-35
optimization, the high-fanout trees are ripped up and rebuilt,

based on final clustering, which tends to minimize
congestion and optimize the timing on these nets.
Target Max Transition Sets the global maximum transition
target. Astro uses the most constraining value specified in the
library, SDC, or global constraint.
Target Max Capacitance Sets the global maximum
capacitance target. Astro uses the most constraining value
specified in the library, SDC, or global constraint.
Target Utilization Sets the trigger point at which area
recovery is performed.
Target Max Utilization Sets the maximum utilization point at
which optimizations stop processing.
3. Click Apply.
You can use the hfn_fanout_threshold parameter to control the
maximum fanout constraint. This constraint is the number of fanouts
on a net that will trigger high-fanout net synthesis. The default is 40
but you can specify a large upper limit, to effectively avoid
high-fanout net synthesis. For example, during placement,
high-fanout net synthesis (not high-fanout net resynthesis) occurs by
default. However, you might want to skip high-fanout net synthesis at
this stage and instead do stand-alone high-fanout net synthesis later.
The syntax is
(axSetIntParam "pds" "hfn_fanout_threshold" 40)
;;
range [2,10000000], default=40, stored in cell;
;; number of fanouts on a net to trigger HFN optimization

6-36
Library Page
Use the Library page to set the runtime process, voltage, and
temperature (PVT) values under which timing analysis and
optimization are run. For multi-VDD designs, you can specify the use
of multiple nonlinear delay model (NLDM) libraries with the same cell
name.
To select library options that affect timing and optimization,
and click the Library tab.
The Library page appears.

- Run Time PVT Setting Adjusts timing based on changes you
specify to the process, voltage, and temperature information.
Astro Timing Setup
6-37
The timing values are scaled based on these inputs and in

accordance with the scaling factors you specify in the k-factor
file.
- Enable Multi NLDM Library Enables the use of multiple
NLDM libraries with library cells having the same cell name but
characterized for different voltage ranges. This feature is for
multi-VDD designs. For more information, see the Astro User
3. Click Apply.
Parasitics Page
Use the Parasitics page to select options, such as the parasitic
source, the layout parasitic extraction mode, and the capacitance
model for timing.
Astro uses a congestion-based coupling model and TLU or TLUPlus
capacitance tables to accurately model the prerouting capacitance
for nets. This methodology eliminates the questionable derivation of
the linear capacitance coefficient and improves the accuracy of the
model by considering increased coupling due to increased
congestion in different regions of the chip or block.
TLU or TLUPlus capacitance tables are required for capacitances. If
TLU capacitance models do not exist, use Tools > Data Prep >
Techfile > Create Capacitance Model (cmCreateCapModel) to
build them from the process information. TLUPlus uses Star-RCXT
model generation to create capacitance tables.
To select parasitics options that affect timing and optimization,
and click the Parasitics tab.
6-38
The Parasitics page appears.

- Next to Parasitic Source, click one of the following buttons to
choose the source of the parasitics:
LPE, which is extracted by Astro.
DB, which uses the parasitic view from Astro. The parasitic
view is created with the parasitics extracted by Astro or from
the external DSPF or SPEF files.
DB_then_LPE, which uses the parasitic view for nets if it
exists; if it does not exist, DB_then_LPE uses Astro for the
extraction.
Astro Timing Setup

6-39
- Next to LPE Mode, click one of the following buttons to choose

the layout parasitic extraction mode:
Virtual_RC, which uses virtual routing (Steiner tree with
obstruction avoidance) and congestion-based coupling to
estimate preroute parasitics.
Real_R_Virtual_C, which uses resistance extraction based on
real routing and coupling from estimation (after global routing,
the routing geometry is determined for the most part, but there
is no exact coupling information yet because the neighboring
wires are not fixed).
Real_RC, which uses real wire and surrounding wire
geometries for the extraction.
Auto, which uses the extraction mode the tool determines
automatically.
Note:
Astro uses a heuristic to decide what extraction mode to use,
based on the number of polygons and other factors. There
are situations, such as when the correct mode is not used
during global routing, in which you should simply set the
mode manually on the Parasitics page.
- Next to Operating Cond, click the Max, Nom, or Min button to
choose an operating condition.
This operating condition is different from the cell delay model
operating conditions (specified in the Model page); therefore,
you can perform corner analysis.
- Next to Capacitance Model, click one of the following buttons
to choose a capacitance model:

6-40
TLU, which uses normal extraction models built by

cmCreateCapModel with a 3-D field solver, process
geometries, and basic models. Because this command does
not account for more complex processes and models, you can
use TLUPlus.
TLU+, which uses Star-RCXT model generation to create
TLUPlus capacitance tables and resistance tables. These
tables support complex processes and also provide more
accurate modeling than TLU, because test structures used to
develop the tables are more extensive. For more information,
see Generating TLUPlus Capacitance and Resistance
Models on page 7-43.
- Next to Temperature, specify the minimum, nominal, and
maximum operating temperature to be used to scale the
resistances in the library, based on the temperature coefficient
in the technology file.
- Select Real Fill Extraction to activate real fill extraction in the
metal fill flow in Astro. To use this option, you must attach
emulation TLUPlus files (either as metal-fill grounded type or
metal-fill floating type) in addition to the normal TLUPlus files.
If an emulation table is attached as metal-fill grounded type,
the fill polygon will be handled using the grounded model. If an
emulation table is attached as metal-fill floating type, the fill
polygon will be handled using the floating model. Enabling this
option also sets the METAL_FILL_POLYGON_HANDLING:
AUTOMATIC parameter for Star-RCXT when you run the
astStarRCXT command.
When this option is selected, Automatic Metal Fill Polygon
Handling becomes active.
Astro Timing Setup

6-41
- Select Automatic Metal Fill Polygon Handling to instruct Astro

to automatically perform either floating or grounded model
extraction (Real Fill Extraction must also be selected), based
on its own route type in the Milkyway database. This automatic
mode provides better correlation with the Star-RCXT metal-fill
extraction AUTOMATIC mode.
Note:
This option is not active if you are using an older version of
Astro or reading an older version of the Milkyway database.
- Select Derate Resistances From DB to derate resistances
read from the parasitic view in the database (either the DB or
DB_then_LPE parasitic source must also be selected).
- Next to Geometry Scaling Factor, enter the geometry scaling
factor you want to use for your calculation. This scaling factor
affects the length and width of all wires. For example, if you set
the geometry scaling factor to 2.0, the length and width of all
wires will be doubled.
3. Click Apply.
Model Page
Use the Model page to set cell delay model information and to
choose which net delay model to run for timing.
To select model options that affect timing and optimization,
and click the Model tab.
The Model page appears.

6-42
2. In the Cell Delay Model area, choose the operating condition and
specify cell delay or propagation delay values or keep defaults.
- Next to Operating Cond, click the Max, Nom, and/or Min
buttons to choose which corners of the loaded library
information are used during optimizations. Normally Max and
Min are selected.
- Under Cell Delay Method or Propagation Delay Method,
specify input and output time characterization points for the
rise and fall, in percentages, and specify transition delay rise
and fall time from start to end, in percentages.
Astro Timing Setup

6-43
For the cell delay method, also specify the floating number in
the Slew Derate From Table box that shows how the transition
time found in the table must be derated to match the transition
time between the start points and endpoints.
Click Load to load the settings of the cell delay method from the
reference libraries.
Note:
Astro determines the cell delay model to be used based on
your reference timing library. When using LM (logic model)
views, Astro has a consistent cell delay model with PrimeTime.
For more information, see Creating LM Views for Timing and
Power Analysis on page 3-29.
3. In the Net Delay Model area, select one of the methods for
analyzing net delay (Low Effort, Medium Effort, or High Effort).
- Use high effort for interconnect analysis that is consistent with
PrimeTime.
- For low or medium effort, it is recommended that you choose
low effort prior to routing and medium effort after routing. This
can produce faster runtimes when the added accuracy of
medium effort is not needed. However, you can choose to set
medium effort from the beginning. If you do so, low effort net
delay analysis is used by various parts of the tool, even though
medium effort is set, when the added accuracy of medium
effort is not needed (typically during optimizations prior to
routing).
Note:
Before running any timing function or Astro optimization, you
need to set at least one basic setting for the interconnect
model by selecting the appropriate net delay model.
4. Click Apply.
6-44
Xtalk Page
Use the Xtalk page to set the crosstalk circuit model and to specify
crosstalk filtering thresholds (aggressor and electrical) and global
noise thresholds.
The ability to set global noise thresholds in the Xtalk page enables
postplacement optimization, crosstalk analysis, and postrouting
optimization to all use the same noise thresholds. The filtering
thresholds and global noise thresholds specified are honored in
crosstalk fixing as well as crosstalk analysis. See also Chapter 15,
Signal Integrity: Crosstalk Prevention, Analysis, and Fixing."
To select crosstalk options that affect timing and optimization,
and click the Xtalk tab.
The Xtalk page appears.
Astro Timing Setup

6-45
2. In the Crosstalk Filtering Threshold area, specify aggressor and

electrical filter threshold values; or keep defaults. It is
recommended that you use the default values (you can click
Default to see them). See also Table 6-1 on page 6-49.
The three aggressor filter thresholds are used by the Astro
extraction engine. These are coupling capacitance thresholds
that exclude aggressors with coupling capacitances below the
specified values. An aggressor net is filtered when the following
three conditions are met:

6-46
- Relative coupling capacitance threshold The ratio of the total

coupling capacitance (between the aggressor and the victim)
of the net to the total coupling capacitance of the victim net is
less than the threshold.
- Absolute coupling capacitance threshold The total coupling
capacitance between the aggressor net and the victim net is
less than the threshold.
- Average relative coupling capacitance threshold The ratio of
the total coupling capacitance between the aggressor net and
the victim net and the average coupling capacitance between
the victim net and all of its aggressor nets is less than the
threshold.
Note:
For the aggressor filters, the Relative coupling capacitance
threshold default value is 3 percent and the Absolute
coupling capacitance threshold default value is 3 fF. Because
earlier versions of Astro-Xtalk used 10 percent and 10 fF as the
default values, you typically observe more noise violations and
crosstalk-induced delays with the new values. Although you
can change the default values for these variables, it is not
recommended.
The two electrical filter thresholds are used by crosstalk analysis
for consistency with PrimeTime SI. They are based on the
amplitudes of the noises and are used to filter out negligible
noises in the evaluation of noises and crosstalk-induced delays.
An aggressor net is filtered when the following two conditions are
met:
- Single peak noise threshold The peak voltage of the noise
bump induced on the victim net, divided by VDD (the power
supply voltage), is less than the threshold.
Astro Timing Setup

6-47
- Accumulate peak noise threshold The combined height of

smaller noise bumps, divided by VDD (the power supply
voltage), is less than the threshold.
3. In the Global Noise Threshold area, you can do the following:
- Next to Noise Threshold, enter the global noise threshold
values for rise and fall or keep the defaults. The specified
values are in terms of percentage of voltage. These noise
thresholds are used by the placement and routing processes
as noise constraints for optimization. They are also used to
report and constrain noise violations. Rise noise violations are
referred to as above_low and fall noise violations as
below_high.
- Select Use net-based threshold from file, to specify that the
threshold values are obtained from a named input file. For
more information, see Specifying Net-Based Noise
Thresholds With an Input File on page 6-53.
- Next to Noise Type, select one of the following:
Static (the default) to report the noise contributions when
aggressor nets switch and the victim net does not. Static noise
computation is related to the glitch analysis technique.
Switching to report the noise contributions when aggressor
nets and the victim net switch. Switching noise computation is
related to crosstalk-induced delay.
- Select Include Timing Window to specify that
crosstalk-induced delay evaluation takes into account the
timing windows of the victim and aggressor nets. The default is
on.

6-48
4. In the Crosstalk Circuit Model area, next to Circuit Model, choose

the circuit model to use for crosstalk-related analysis and
optimization by clicking one of the following:
- Low Effort, which is fast but not as accurate as the medium
effort.
- Medium Effort, which is more accurate but uses more runtime
than the low effort.
For more information about the low-effort and medium-effort
crosstalk circuit models, see Additional Information About
Crosstalk Circuit Models on page 15-63.
5. Click Apply.
Crosstalk Filtering Mechanisms

The Astro crosstalk filtering mechanisms include three parasitic
aggressor filters and two electrical filters.
Table 6-1 lists the parasitic aggressor filters. These filters are used
by the Astro extraction engine.
Table 6-1
Parasitic Aggressor Filters
Star-RCXT parameter
Default
Astro dialog box parameter
Default
COUPLING_REL_THRESHOLD
3%
Crosstalk aggressor relative threshold
3%
COUPLING_ABS_THRESHOLD
3 fF
Crosstalk aggressor absolute threshold
3 fF
COUPLING_AVG_THRESHOLD
0%
Crosstalk aggressor average threshold
0%
Astro Timing Setup

6-49
Table 6-2 lists the electrical filters. These filters are used by crosstalk
analysis for consistency with PrimeTime SI.
Table 6-2
Electrical Filters
PrimeTime parameter
Default
Astro dialog box parameter
Default
si_filter_per_aggr_
noise_peak_ratio (xVdd)
0.01
Crosstalk electrical single threshold
0.01
si_filter_accum_aggr_
noise_peak_ratio (xVdd)
0.03
Crosstalk electrical accumulate

threshold
0.03
Reporting Crosstalk Filtering Thresholds

Use the xtGetXtalkFilter command to write the filtering
threshold information that is used in Astro to an output file. You can
specify that the output be in Scheme format (to be loaded by Astro)
or Tcl format (to be loaded in PrimeTime SI with scripts).
xtGetXtalkFilter 1 | 2 "filename"
A value of 1 specifies Scheme format, and 2 specifies Tcl format.
Sample Report
Following is the sample output file in Scheme format:
;; DB Capacitance Unit: pf
;; Aggressor filering:
;; Absolute total coupling capacitance threshold is 0.03pf
;; Relative total coupling capacitance threshold is 3%
ekSetCoupleCapThreshold 0.03 30
;; Average relative total coupling capacitance threshold is
;;25%
ekSetCoupleCapAvgPerThreshold 0.25
;; electrical filtering:
;; Peak Noise threshold is 0.01

6-50
xtSetPeakNoiseThreshold 0.01
;; Accumulate peak noise threshold is 0.03
xtSetAccumPeakNoiseThreshold 0.03
Following is the sample output in Tcl command format:

## DB Capacitance Unit: pf
## Aggressor filering:
## Absolute total coupling capacitance threshold is 0.03pf
set si_filter_per_aggr_xcap 0.03
## Relative total coupling capacitance threshold is 3%
set si_filter_per_aggr_xcap_to_gcap_ratio 0.03
## Average relative total coupling capacitance threshold is
25%
set si_filter_per_aggr_to_average_aggr_xcap_ratio 0.25
## electrical filtering:
## Peak Noise threshold is 0.01
set si_filter_per_aggr_noise_peak_ratio 0.01
## Accumulate peak noise threshold is 10
set si_filter_accum_small_aggr_noise_peak_ratio 10
Specifying Single Peak Noise Threshold

Use the xtSetPeakNoiseThreshold command to set the single
peak noise threshold that is used to filter out small amounts of noise
during noise calculation.
Use xtSetPeakNoiseThreshold in conjunction with
xtSetTotalPeakNoiseThreshold and
xtSetAccumPeakNoiseThreshold to control whether the noise
contribution from an aggressor net of a victim net can be safely
ignored during noise calculation. When the noise from an aggressor
net is smaller than the peak noise threshold, it can be ignored. Sort
the aggressor nets of the victim nets by noise value and go through
the list of aggressor nets, starting with the smallest one. When the
accumulated noise is smaller than the accumulated peak noise
threshold and the total noise is smaller than the total peak noise
threshold, the noise of the aggressor net can also be ignored.
Astro Timing Setup

6-51
Alternatively, you can set the xtSetPeakNoiseThreshold value

by using the Xtalk page in the AstroTime Timing Setup dialog box
(atTimingSetup).
xtSetPeakNoiseThreshold value
where value is the peak noise threshold number.
Specifying Accumulated Peak Noise Threshold

Use the xtSetAccumPeakNoiseThreshold command to set the
accumulated peak noise threshold that is used to filter out small
amounts of noise during noise calculation.
Use xtSetAccumPeakNoiseThreshold in conjunction with
xtSetTotalPeakNoiseThreshold and
xtSetPeakNoiseThreshold to control whether the noise
contribution from an aggressor net of a victim net can be safely
the list of aggressor nets, staring with the smallest one. When the
Alternatively, you can set the xtSetAccumPeakNoiseThreshold
value by using the Xtalk page in the AstroTime Timing Setup dialog
box (atTimingSetup).
xtSetAccumPeakNoiseThreshold value
where value is the accumulated peak noise threshold number.

6-52
Specifying Total Peak Noise Threshold

Use the xtSetTotalPeakNoiseThreshold command to set the
total peak noise threshold that is used to filter out small amounts of
noise during noise calculation.
Use xtSetTotalPeakNoiseThreshold in conjunction with
xtSetPeakNoiseThreshold and
xtSetAccumPeakNoiseThreshold to control whether the noise
contribution from the aggressor net of a victim net can be safely
the list of aggressor nets, starting with the smallest one. When the
xtSetTotalPeakNoiseThreshold value
where value is the total peak noise threshold number.
Specifying Net-Based Noise Thresholds With an

Input File
You can create a threshold input file, which provides net-based noise
thresholds, and load it in Astro to be used during the noise analysis
process (xtXTalkAnalysis). When you put the nets in your
design into different noise constraint groups (the maximum number
of groups is 16), you can assign different noise thresholds for each
group. The nets in a group all have the same noise threshold (with
different pruning types if desired), but different constraint groups
have different noise thresholds.
Astro Timing Setup

6-53
The threshold input file has two parts:
The first part defines the noise constraint groups and defines
their noise thresholds
The second part specifies the group to which a net belongs
The syntax for defining constraint groups and their noise thresholds
is
xtDefineXtalkConxGroup groupId riseThreshold fallThreshold
where groupId is the constraint group ID (0 to 15) and riseThreshold

and fallThreshold are the threshold values for rise and fall noise,
respectively.
Group 0 is the default global group. If you do not define the rise and
fall noise threshold values, Astro uses the values specified in the
Crosstalk Analysis dialog box for group 0; otherwise, the value you
define in the input file is used. If a group ID is larger than 15 or
smaller than 0, Astro ignores the group definition.
If a net is not specified in the threshold input file, it belongs to group
0. A net can only belong to one constraint group; if you assign a net
to more than one group, the last setting overwrites the previous one.
The syntax for defining what nets are assigned to a group is
netname patternMatch groupId
where netname can be a net name or a pattern of net names;

patternMatch can be 0 (an exact match) or 1 (a pattern); and groupId
is the group name that the net belongs to, as defined with
xtDefineXtalkConxGroup. If you do not define the group ID,
Astro sets the name to group 0 (the default group).

6-54
Here is a sample threshold input file:

;Part1: constraints group definition
xtDefineXtalkConxGroup 3 0.3 0.3
;Part2: net constraints group specification
a[3] 0 3
b.* 1 2
x.* 1 4

Astro supports the usage of the three-state buffer as a dynamic latch
by connecting the clock to the control input (the enable pin) of the
three-state buffer. For dynamic latch, setup and hold checks of the
data signal can be performed against the enable signal.
Figure 6-2 shows a sample schematic for a three-state buffer that is
used as a dynamic latch.
Figure 6-2
Three-State Buffer Used as Dynamic Latch

6-55
Use the set_dynamic_latch command to define the three-state

buffer as a dynamic latch. Consider the following example:
(tcl "set_dynamic_latch -setup 0.1 -hold 1.2 DL)
where
-setup
is used in the calculation of required time in the ideal mode, as
shown here:
Setup time
0.1000
2.7951
--------------------------------------Required time
2.7951
and is used in the calculation of the maximum borrowed time in

the borrowing mode, as shown here:
--------------------------------------------------CLK nominal pulse width
4.5000
library setup time
-0.1000
--------------------------------------------------max time borrow
4.4000
-hold
is used in the calculation of the required time in both ideal and
borrowing mode, as shown here:
Hold time
1.2000
6.4760
--------------------------------------------------Required time
6.4760
DL
is the instance name of the three-state buffer that is used as a
dynamic latch.

6-56
An information message is shown in the log file during timing

analysis when there is a dynamic latch definition. For example,
INFO: set_dynamic_latch -setup 0.1000 -hold 1.2000 {DL}
To remove the dynamic latch setting, use the

remove_dynamic_latch command.
During timing analysis, setup and hold timing checks are performed
as shown in Figure 6-3.
Figure 6-3
Setup and Hold Timing Checks
The setup and timing checks differ with borrowing and without
borrowing.
Without borrowing, the setup check is performed on the rising

edge and the hold check is performed on the falling edge of the
enable signal.

6-57
With borrowing, the setup check is still performed on the rising

edge of the enable signal, but the borrowing information is now
considered in the calculation of the slack value as in the case of
normal latches. The hold check is still performed on the falling
edge of the enable signal.
The timing checks for the path from the three-state buffer to FF2, as
shown in Figure 6-2 on page 6-55, are the same as when the
three-state buffer is treated as a level-sensitive latch, either without
time borrowing (ideal mode) or with time borrowing (time borrowing
mode).
Note:
Astro supports the definition of clock latency on the enable pin.
For example,
set_clock_latency -max 1 [get_pins
{THREE_STATE_BUFFER/EN}]
set_clock_latency -min 0.5 [get_pins
{THREE_STATE_BUFFER/EN}]
This feature is useful if you perform the timing check when the
clock is not propagated.
Setting Clock Transition Defaults at the Clock Pins

Use the set_clock_transition SDC command to set the clock
transition default values at the clock pins of the sequential cells. Later
in the flow, you can remove the transition defaults, after the clock is
inserted and routed, for a more accurate delay calculation. Due to
various design styles, it is impossible for Synopsys to predict
automatically when to remove this default.

6-58

Astro automatically handles high-fanout nets during the flow;
therefore, for most nets, there is no need to set a transition or
capacitance default.
There are two ways to buffer high-fanout nets in Astro: during
preplacement optimization (see Performing Preplacement
Optimization on page 8-58) and by using Astro clock tree synthesis
(see Performing Clock Tree Synthesis After Placement on
page 9-62).
If you want to run Astro clock tree synthesis, the pins connected to
the net must be clock or scan-clock pins. That is, if the pins on the
net have neither clock nor scan clock assigned to them, they are
ignored by Astro clock tree synthesis. They are ignored because
Astro clock tree synthesis does not know what the trigger edges
(rises or falls) are. As a result, which arrival time (rise or fall) should
be used to calculate skew is also unknown. Typically, scan enables
should be buffered by Astro clock tree synthesis, because the loads
are declared as scan clock in the port types file. To keep
preplacement optimization from buffering these nets, simply declare
the scan enable as a clock.
Other nets, such as resets, do not fall into this category. These nets
are automatically buffered, using a high-fanout net tree, during
preplacement optimization with no action required.

6-59
Setting Maximum Capacitance and Transition

Constraints on Clock Domains
Astro provides commands that you can use to specify the maximum
capacitance and maximum transition to propagate along the nets of
a clock domain.
Setting Maximum Capacitance Constraints on Clock

Domains
The ataSetAndPropagateMaxCapBoundPort and
ataSetAndPropagateMaxCapClockData Scheme commands
let you specify the maximum capacitance to propagate along the
nets of a clock domain. Alternatively, you can use the
set_max_capacitance Tcl command for setting this constraint.
Using the Scheme Commands

Use the ataSetAndPropagateMaxCapBoundPort command to
set and propagate maximum capacitance constraints on all the
boundary ports specified. The constraint is propagated until valid
timing end-points or the output boundary ports are encountered. The
command syntax is
ataSetAndPropagateMaxCapBoundPort "port" value
For example,
ataSetAndPropagateMaxCapBoundPort "IN1" 0.3

6-60
Use the ataSetAndPropagateMaxCapClockData command to

set and propagate maximum capacitance constraints on all the data
path instance pins driven by the specified clock nets. When two
different maximum capacitance constraints join at the same design
pin, the more conservative value is used. The command syntax is
ataSetAndPropagateMaxCapClockData "clock" value
For example,
ataSetAndPropagateMaxCapClockData "clk1" 0.1
Use the following associated commands:
Use ataRemoveMaxCapBoundPort to remove maximum

transition constraints specified with the
ataSetMaxCapBoundPort command. The syntax is
ataRemoveMaxCapBoundPort "port"
Use ataRemoveMaxCapClockData to remove maximum

capacitance specified with the ataSetMaxCapClockData
command. The syntax is
ataRemoveMaxCapClockData "clock"
Use ataDumpPropagatedMaxCap to report all maximum

capacitance specified with the
ataSetAndPropagateMaxCapBoundPort and
ataSetAndPropagateMaxCapClockData commands in a
file. The syntax is
ataDumpPropagatedMaxCap "file_name"
Setting Maximum Capacitance and Transition Constraints on Clock Domains

6-61
Using the Tcl Command

You can use the set_max_capacitance Tcl command instead of
the preceding Scheme commands to specify maximum capacitance
on ports or designs.
To specify the maximum capacitance constraint on ports, use the
following syntax:
set_max_capacitance value [get_ports]
For example, to set a maximum capacitance limit of 2.0 units on

ports OUT*, enter
set_max_capacitance 2.0 [get_ports "OUT*"]
To specify the constraint on the entire design, use the following

syntax:
set_max_capacitance value [current_design]
For example, to set the default maximum capacitance limit of 5.0

units on the current design, enter
set_max_capacitance 5.0 [current_design]
Setting Maximum Transition Constraints on Clock

Domains
The ataSetAndPropagateMaxTransBoundPort and
ataSetAndPropagateMaxTransClockData Scheme
commands let you specify the maximum transition to propagate
along the nets of a clock domain. The usage of these Scheme
commands is similar to the usage of the
ataSetAndPropagateMaxCapBoundPort and
6-62
ataSetAndPropagateMaxCapClockData commands.
Alternatively, you can use the set_max_transition Tcl command
for setting this constraint.
Setting Capacitance, Transition, and Delay Defaults

for Nets
The ataSetNetCapTransAndDelayTime command allows you to
set a default capacitance, transition, and delay on a net. When these
parameters are set, the tool does not try to optimize the net. This is
useful in the following situations:
When you want to prevent preplace optimization from buffering a

nonclock high-fanout net.
When you want to prevent preplace optimization from trying to fix

a critical path that contains a high-fanout clock node caused by
data and clock mixing. This path is not fixed by preplace
optimization, because the net is partially a clock net.
In both of these cases, the ataSetNetCapTransAndDelayTime

command allows you to specify a realistic capacitance, transition,
and delay to the net and a driver for the net, so that optimization
processes do not erroneously concentrate their efforts on trying to fix
the problem. After you have built a tree to solve the high-fanout net
problem, the capacitance, transition, and delay will be realistic. At
that time, remove the default and run optimization processes to fix
any remaining problems.
Setting Capacitance, Transition, and Delay Defaults for Nets

6-63
Note:
Loading ataSetNetCapTransAndDelayTime creates a TIM
view to store the information. You should immediately save the
TIM view after the loading step, by using the
geSaveAllOpenCells command or Cell > Save All Open
Cells.
In a replay script, you can avoid the query boxes that pop up for
the geSaveAllOpenCells command (especially helpful in
nullDisplay mode), by specifying the following:
setDisplayMode "QueryBoxes" #f
geSaveAllOpenCells

6-64
7
Analyzing Timing
Astro provides various ways for you to analyze and understand the
timing results of your design. For example, after optimizing a design,
you can generate reports to analyze your timing, area, and
component selection results. When you study the reports, note any
constraint violations in the design. You might have to apply different
placement and routing techniques to improve the designs timing
results.
Using Timing Reports
Probing Timing
Interactive Editing
Place and Route Summary Report
Checking Timing Data
7-1
Checking Timing and Optimization for the Design
Checking Timing Constraints
Effects of Synopsys Design Constraints on Timing Analysis and

Optimization
Design Feasibility
Checking Library Inputs
Checking Logical Equivalence Information
Adjusting Preroute Pessimism and Optimism of Capacitances
Determining Extraction in Auto Mode
Checking TLU Capacitance Model Parameters
Using TLUPlus Capacitance and Resistance Models
Non-Unate Clock Network Analysis
Chapter 7: Analyzing Timing

7-2

Use the astReportTiming command to generate a timing report
for your design at various stages of the design flow. Depending on
the options you select, you can report valid paths for the entire
design or for specific paths. You might need to run the
atTimingSetup command before using the astReportTiming
command (for more information, see Astro Timing Setup on
page 6-19).
Note:
The timing report does not include crosstalk noise violations. To
report noise information, run the xtXTalkAnalysis command.
Using xtXTalkAnalysis, you can see a summary of noise
statistics, including the number of nets with noise violations, as
listed in the log file. For more information, see Analyzing Noise
on page 15-13.
The timing report helps evaluate why some parts of a design might
not be optimized. The report contains a header section and timing
sections. The header section includes a list of possible explanations
for the lack of optimization, prefaced with an abbreviationwhen
Astro detects a known cause, it prints the abbreviation next to the
instance or net in the Reason column of the timing sections.
To generate a timing report,
1. Enter astReportTiming or choose Timing > AstroTime
Timing Report.
The Timing Report dialog box appears.

7-3

You can report information about setup, hold, maximum and
minimum transitions, and maximum and minimum capacitance
constraints within your design. You can also create a histogram
(graphic representation) for setup and hold constraintsselect

7-4
Max and Min (next to Delay Type) and Max Trans and Max Cap
(under Report Constraints) and Show Histogram (under Other
Options). This produces a quick, summary report for the current
timing. Because only one path is reported for setup and hold (the
default), the report will not be very large. You can search for a
specific path as well as specify additional paths to be reported.
When you select Net Based (under Report Constraints), the
report includes the net name instead of only the port instance
(useful for debugging transition and capacitance violations).
Select Clock Trans to locate transition violations in the clock
network.
You can select Show Clock Path (under Other Options) to print
out detailed clock paths for the start points and endpoints of the
constrained timing path. You must first propagate the clock to get
the clock path to appear. To propagate the clock, include
set_propagated_clock <clk> in the SDC file, or use the
following syntax:
sdc "set_propagated_clock <clk>"
See Viewing Clock Paths on page 7-10.

You can select Report Delta Delay/Trans (under Other Options)
to report crosstalk-induced delta delays and delta transition times
(when you select Enable Crosstalk Effects in the Environment
page of the AstroTime Timing dialog box). Astro reports the
crosstalk effect on cell delay and interconnect delay separately.
You can also use the Dump Time Borrow Script option, which is
primarily for back-annotation purposes (mainly to PrimeTime).
The script can be used to feed back the amount of borrowing
Astro does for latch-based designs. Synopsys has found that you

7-5
must do aggressive borrowing to optimize latch-based designs.

The borrowing script provides a way to minimize any correlation
discrepancies.
3. Click OK.
The Astro timing report appears. It includes a header section and
timing sections.
The header section includes these areas:
- Astro Timing Report
This area lists the tool name, tool version number, design
name, and time stamp.
- Design Setup
This area reports which parameters and constraints were used
to calculate the timing, such as ignore interconnect, default
clock, and recovery and removal arcs.
- Reasons For No Optimization
This area provides an abbreviation key that is used in the
Reason column of the timing sections of the report. This key
can help debug the reason a cell or a net has a large delay,
even after optimization, by alerting you to issues such as
three-state nets, dont touch nets and instances, large pin
caps, and the lack of logical equivalence.
The timing sections report all the paths or specific paths for your
design, from the start point, through the pins, and to the end
point.

7-6
Example
Here is a sample timing report:
************************************************************************************************************
*
*
Astro Timing Report
*
*
Tool
: Astro
*
Version : V-2004.06-Development for IA.32 -- May 27, 2004
*
Design : TCS03_postIR
*
Date
: Thu May 27 17:05:15 2004
*
************************************************************************************************************
*
************************************************************************************************************
*
*
Design Setup
*
*
Analysis Type
: Max
*
Parasitic Source
: from LPE
*
LPE Operating Cond
: Max
*
LPE Mode
: Real_RC
*
Wire Delay
: AWE
*
Time Borrowing
: Enabled
*
Time Borrowing Method
: Standard
*
Preset/Clear Arcs
: Disabled
*
Recovery/Removal Arcs
: Enabled
*
Scan Enable
: Enabled
*
Inter Clock Paths
: Enabled
*
Default Clock
: Enabled
*
Ideal Network Delay
: Enabled
*
Mixed Clock/Signal Paths
: Enabled
*
Include Xtalk Induced Delay
: Enabled
*
Include Timing Window in Xtalk : Enabled
*
Include Non-Propagated Nets
: Disabled
*
Include Lib Max Transition
: Enabled
*
Include Lib Max Capacitance
: Enabled
*
Ignore Clock Uncertainty
: Disabled
*
Ignore Propagated Clock
: Disabled
*
Set IO Clock Latency
: Disabled
*
Enable Data Check
: Enabled
*
Load Useful Skew From DB
: Disabled
*
Enable Clock Gating Checks
: Enabled
*
Multiple Clocks Per Register
: Disabled
*
Include CRPR
: Disabled
*
Operating Conditions
: cb13os120_tsmc_max (Max)
*
cb13os120_tsmc_max (Min)
*
************************************************************************************************************
*
************************************************************************************************************
*
*
Reasons For No Optimization
*
*
NDT : Don't touch net.
*
IDT : Don't touch instance.
*
FIX : Fixed instance.
*
MDR : Multi-Driven net.
*
PCP : Huge pin cap on the net.
*
TRI : Tristate net.
*
PRE : Preserve Logic.
*
DIS : Disabled edges on the net.
*
NEQ : No equivalent cells.
*
************************************************************************************************************
************************************************************************************************************
*
*
Start point : V2Y_RDY_reg/CP
*
( Rising edge-triggered flipflop clocked by PE_CLK )
*
*
End point
: V2Y_RDY
*
( Output port clocked by FE_CLK )
*
*
Clock Group : FE_CLK
*
Delay Type : Max
*
Slack
: 16.1429 (MET)
*

7-7
************************************************************************************************************
Port/Pin
Cap Fanout
DTrans.
Trans.
Delta
Incr
Arri
DArri Reason Master/Net
-----------------------------------------------------------------------------------------------------------Rising edge of clock PE_CLK
0.0000
0.0000
Clock Source delay
0.0000
0.0000
736.3976
736.3976
-----------------------------------------------------------------------------------------------------------V2Y_RDY_reg/CP
0.0000
219.1833
0.0000
0.0000
736.3976
0.0000 r
sdnrb1
V2Y_RDY_reg/Q
0.0634
2
548.8898
580.2972
1316.6948
0.0000 f
V2Y_RDY
V2Y_RDY
0.0000
548.8898
0.0000
1.1857
1317.8805
0.0000 f
-----------------------------------------------------------------------------------------------------------Rising edge of clock FE_CLK
8000.0000
8000.0000
Clock Source delay
0.0000
8000.0000
Clock Network delay
0.0000
8000.0000
Clock Skew
0.0000
8000.0000
Output delay
6665.9766
1334.0234
-----------------------------------------------------------------------------------------------------------Required time
1334.0234
Arrival time
1317.8805
-----------------------------------------------------------------------------------------------------------Slack
16.1429 (MET)
************************************************************************************************************
*
*
Start point : REG_SEL_reg_00/CP
*
*
*
End point
: REG_DATA_reg_310/D
*
( Rising edge-triggered flipflop clocked by PE_CLK at CP )
*
*
Clock Group : PE_CLK
*
Delay Type : Max
*
Slack
: -225.8125 (VIOLATED)
*
************************************************************************************************************
Port/Pin
Cap Fanout
DTrans.
Trans.
Delta
Incr
Arri
0.0000
0.0000
Clock Source delay
0.0000
0.0000
723.1982
723.1982
-----------------------------------------------------------------------------------------------------------REG_SEL_reg_00/CP
0.0000
222.8459
0.0000
0.0000
723.1982
0.0000 r
sdnrb2
REG_SEL_reg_00/Q
0.0220
2
131.2129
435.8871
1159.0853
0.0000 f
n4186
U23330/I
0.0000
131.2129
0.0000
0.2576
1159.3429
0.0000 f
invbd4
U23330/ZN
0.0665
8
147.3377
86.9199 & 1246.2628
0.0000 r
n27428
U23333/I
0.0000
147.3377
0.0000
2.7320
1248.9948
0.0000 r
inv0d1
U23333/ZN
0.0260
4
235.9641
143.9407 & 1392.9354
0.0000 f
n27429
U990/A1
0.0000
236.0962
0.0000
0.0902
1393.0256
0.0000 f
nd02d2
U990/ZN
0.0110
2
129.0408
81.3385
1474.3641
0.0000 r
n5719
U15810/I
0.0000
129.0670
0.0000
0.0261
1474.3903
0.0000 r
invbd2
U15810/ZN
0.1088
14
413.6400
220.1883 & 1694.5786
0.0000 f
n4391
U8270/A2
0.0000
413.6400
0.0000
2.5494
1697.1281
0.0000 f
nd13d1
U8270/ZN
0.0169
2
143.1420
262.8775 & 1960.0055
0.0000 r
n4460
U15090/I
0.0000
143.1420
0.0000
0.2411
1960.2466
0.0000 r
inv0d1
.
.
.
U11131/A2
0.0000
105.5660
0.0000
0.0254
8230.0469
120.8064 f
an12d2
U11131/Z
0.0203
1
112.7747
146.3714 & 8376.4180
120.8064 f
n15540
U11132/I0
0.0000
112.7747
1.3620
1.9609
8378.3789
122.1685 f
mx02d1
U11132/Z
0.0038
1
105.2416
174.3659
8552.7451
122.1685 f
n3185
U4132/B1
0.0000
105.2424
0.0000
0.0008
8552.7461
122.1685 f
aoim21d1
U4132/ZN
0.0062
1
88.5375
278.5966
8831.3428
122.1685 f
n4720
REG_DATA_reg_310/D
0.0000
88.5758
0.0000
0.0382
8831.3809
122.1685 f
sdnrb2
8000.0000
8000.0000
Clock Source delay
0.0000
8000.0000
777.0566
8777.0566
Clock Skew
0.0000
8777.0566
Setup time
171.4879
8605.5684
-----------------------------------------------------------------------------------------------------------Required time
8605.5684
Arrival time
8831.3809
-----------------------------------------------------------------------------------------------------------Slack
-225.8125 (VIOLATED)

7-8
************************************************************************************************************
*
*
Start point : DX13_reg_210/CP
*
*
*
End point
: DX13[21]
*
( Output port clocked by FE_CLK )
*
*
Clock Group : FE_CLK
*
Delay Type : Min
*
Slack
: 3952.0249 (MET)
*
************************************************************************************************************
Port/Pin
Cap Fanout
DTrans.
Trans.
Delta
Incr
Arri
0.0000
0.0000
Clock Source delay
0.0000
0.0000
721.0165
721.0165
-----------------------------------------------------------------------------------------------------------DX13_reg_210/CP
0.0000
211.8713
0.0000
0.0000
721.0165
0.0000 r
sdnrb1
DX13_reg_210/Q
0.1254
3
942.1585
732.2551 & 1453.2717
0.0000 r
DX13[21]
DX13[21]
0.0000
942.1585
-20.0640
-13.0700
1440.2018
-20.0640 r
-----------------------------------------------------------------------------------------------------------Rising edge of clock FE_CLK
0.0000
0.0000
Clock Source delay
0.0000
0.0000
Clock Network delay
0.0000
0.0000
Clock Skew
0.0000
0.0000
Output delay
-2511.8232
-2511.8232
-----------------------------------------------------------------------------------------------------------Required time
-2511.8232
Arrival time
1440.2018
-----------------------------------------------------------------------------------------------------------Slack
3952.0249 (MET)
************************************************************************************************************
*
*
Start point : ZERO_N03_reg/CP
*
*
*
End point
: ZERO_N04_reg/D
*
( Rising edge-triggered flipflop clocked by PE_CLK at CP )
*
*
Clock Group : PE_CLK
*
Delay Type : Min
*
Slack
: 433.3459 (MET)
*
************************************************************************************************************
Port/Pin
Cap Fanout
DTrans.
Trans.
Delta
Incr
Arri
0.0000
0.0000
Clock Source delay
0.0000
0.0000
715.7313
715.7313
-----------------------------------------------------------------------------------------------------------ZERO_N03_reg/CP
0.0000
208.6769
0.0000
0.0000
715.7313
0.0000 r
sdnrq1
ZERO_N03_reg/Q
0.0097
2
115.9748
348.0074
1063.7386
0.0000 f
n18876
ZERO_N04_reg/D
0.0000
116.0561
0.0000
0.0555
1063.7942
0.0000 f
sdnrq1
0.0000
0.0000
Clock Source delay
0.0000
0.0000
716.9586
716.9586
Clock Skew
0.0000
716.9586
Hold time
-86.5103
630.4483
-----------------------------------------------------------------------------------------------------------Required time
630.4483
Arrival time
1063.7942
-----------------------------------------------------------------------------------------------------------Slack
433.3459 (MET)
Timing Report summary

Paths reported
= 4
Violations
= 1
------------------------------------------------------------------------------------------------------------

7-9
************************************************************************************************************
*
*
* Xtalk Noise Violations (static noise)
*
*
*
************************************************************************************************************
Violation Constraint Reason Net
-----------------------------------------------------------------------------------------------------------No xtalk noise violations found in the design.
Viewing Clock Paths

To view the source path details of the launch and capture clocks of
the timing path,
1. Select Show Clock Path in the Timing Report dialog box.
You must also propagate the desired clock. If the clock is not
propagated, the clock path will not be calculated.
An easy way to propagate all clocks is to enter the following in the
command window:
sdc "set_propagated_clock [all_clocks]"
2. Use the timing report in conjunction with the astPath command

to display the desired path in the layout window. In the command
window, use the following syntax:
astPath "
<cut and paste path from report>
"
You can use the astPathClear command to clear the path.

When the launch or the capture clock is a generated clock, view the
details of the path between the master and the generated clocks by
using the path_type full_clock_expanded option of the
report_timing Tcl command.

7-10
The syntax is
(tcl "report_timing -path_type full_clock_expanded")
Probing Timing
The timing probe allows for the interactive querying of paths, the
display of histograms, a schematic display of paths, and case
analysis; also, the timer can be reinitialized.
To launch the Astro timing probe,
Enter atTimingProbe or choose Timing > AstroTime Timing

Probe.
The AstroTime Timing Probe dialog box appears.
The AstroTime Timing Probe dialog box includes several tabs, listed
in this table and described in the following sections.
Tab
Description
Timing Analyzer
Analyzes the changes made to your timing setup,

updates nets, rebuilds the setup conditions, and
updates and starts the timing engine.
Path Timing
Lists the end port and start port names of the path
ports and displays a text window and histogram of
the path end and path start ports.
Instance Timing
Displays the timing between related pins.
Net Timing
Displays information about net timing.
Schematic Probe
Displays the path in a schematic view, including

detailed information of logic components, port
instances, and nets.
Probing Timing
7-11
Timing Analyzer Page

Use the Timing Analyzer page to analyze the changes made to your
timing setup, update nets, rebuild the setup conditions, and update
and start the timing engine.
To use the timing analyzer,
1. Open the AstroTime Timing Probe dialog box (atTimingProbe)
and click the Timing Analyzer tab.
The Timing Analyzer page appears.

7-12
2. Choose an action. You can select

- Run/Update Timer, which starts or updates the timer.
- Timing Setup, which calls the AstroTime Timing Setup dialog
box (atTimingSetup), where you can modify settings for the
timer. For more information, see Astro Timing Setup on
page 6-19.
Probing Timing
7-13
- Free Timer, which frees the timing graph so that when you
update the timer, the timing analysis is done from the
beginning. If you change the operating condition in the
AstroTime Timing Setup dialog box, you must free the timer.
Path Timing Page

Use the Path Timing page to list the end port and start port names
of the path ports and display a text window and histogram of the path
end and path start ports.
To use the Path Timing page,
Open the AstroTime Timing Probe dialog box (atTimingProbe)

and click the Path Timing tab.
The Path Timing page appears.
From this page, you can access the Search Results, List Paths,
and Histogram windows.
Search Results
The Search Results window lists all path start ports, thru ports, and
end ports that match the values you enter in the SPECIFY PATH
SEARCH CRITERIA area, as shown in Figure 7-1.

7-14
Figure 7-1
Search Results Window
List Path
After you locate the path, click List Paths In Text, in the top-right
corner under PATH TIMING COMMANDS, to list the details of the
path in the List Path window that appears, as shown in Figure 7-2.
Probing Timing
7-15
Figure 7-2
List Path Window
Use this window to cross-probe cells and nets. You can either
highlight nets after routing or highlight the flylines of the nets before
routing. At the top of each path listed is an option for highlighting all
the cells in the path and/or all the nets in a path. Alternatively, you
can select individual cells and nets.
To cross-probe the path, click Export This Path To Schematic Probe
(at the bottom of each path).

7-16
Histogram
After you locate the path, click Show Histogram, in the top-right
corner under PATH TIMING COMMANDS, to display the distribution
of path timing in the Histogram window that appears, as shown in
Figure 7-3.
Figure 7-3
Histogram Window
Instance Timing Page

Use the Instance Timing Page to display the timing between related
pins.
Probing Timing
7-17
To display the timing between related pins,

and click the Instance Timing tab.
The Instance Timing page appears.
Net Timing Page

Use the Net Timing page to display information about net timing.
To display information about net timing,

and click the Net Timing tab.

7-18
The Net Timing page appears.
Schematic Probe Page

Use the Schematic Probe page to display the path in a schematic
view, including detailed information of logic components, port
instances, and nets.
To display a path in a schematic view,

and click the Schematic Probe tab.
The Schematic Probe page appears.
Probing Timing
7-19
The Schematic Probe page provides another representation of the

path and further information about it by enabling you to select a
specific cell, port of the cell, or net and to see all the associated
timing arcsnot just the one used for the timing analysis. The
Schematic Probe page also allows the highlighting of cells and nets.
To select information or cross-probe,
1. Under CHOOSE PATH, click the Path Name folder.
The exported path appears.
2. Move the pointer over the cell, cell port, or net and right-click to
select the information or to cross-probe.
7-20
Information is printed under OBJECT INFORMATION, in the

bottom-left corner of the page. To properly view the schematic
page, click Export This Path To Schematic Probe in the List Path
window of the Timing Probe page. If you do not select this option,
there will be nothing to view in the Schematic Probe page.
Interactive Editing
Two commands are provided for interactive editing: the astEdit
command, which is graphically based, and the astChangeNetlist
command, which is name based.
astEdit
Use the astEdit command to find critical paths and interactively
modify the design with techniques such as cell instance sizing, buffer
insertion, net bypassing, net splitting, and cell moving.
The astEdit command should be used after the placement, global
routing, or detail routing phases of the design flow.
To find critical paths or modify the design,
1. Enter astEdit or choose PostPlace > Optimization Interactive
Edit.
The Netlist Change dialog box appears.
Interactive Editing
7-21

- Select the Query Path, Query Cell Instance, and Query Net
options to find critical paths.
- Select the Size Up, Size Down, Buffer Insertion, Bypass, Net
Splitting, or Move options to modify your design.
You can immediately view results and undo any changes you
do not like.

7-22
- Initiate overlap removal (typically, at the beginning of the first

edit) by clicking Start, next to Overlap Removal Engine.
astChangeNetlist
Use the astChangeNetlist command to remove and insert
buffers, size cell instances, and change cell masters.
To change the netlist,
1. Enter astChangeNetlist or choose PostPlace >
Optimization Change Netlist.
The Change Netlist dialog box appears.
Interactive Editing
7-23

- Select a netlist change option and enter the instance name, the
name of the file containing the instances, or the cell master
name. You can specify that only those instances of the cell
master with timing violations are to have their master changed
to the new cell master.

7-24
- Select Force Change to force a netlist change (best used when

the net is a dont touch or clock net type). Generally, Force
Change should be deselected (the default). If you specify an
action that is not allowed, Astro issues an explanation
message. Use this information to decide whether the change
is necessary before you force the action.
- Select Print Result to print information about the changes and
the new nets.
Keep this dialog box active. While it is active, you can continue to
perform all other commands, because the timer, optimization,
and overlap removal processes are still active. You must redo the
initialization if you close the dialog box.

Use the place and route summary command (axgListPRSummary)
to display a summary of placement and routing statistics for a cell.
These statistics can help you evaluate the quality of your design and
help you determine whether or not additional optimizations are
necessary to improve the timing. For example, if the statistics show
an area to have high routing congestion, an optimization might not
have room to add or size-up standard cells.
To view the place and route summary report,
1. Enter axgListPRSummary or choose Query > List PR
Summary.

7-25
The PR Summary dialog box appears. It displays a P&R

Summary window, which includes design information in the
following sections:
- Design Statistics
- Chip Utilization
- Master Instantiation
- Misc. Utilization
- Placement Information
- Timing/Optimization Information
- Global Routing Information
- Track Assignment Information
- Detailed Routing Information
- DRC Information
- Ring Wiring Statistics
- Stripe Wiring Statistics
- PG follow-pin Wiring Statistics
- Signal Wiring Statistics
2. Click Close to remove the PR Summary window, or click Save As
to save the report to a file.

7-26
Placement Information
The Placement Information section reports both the first full-chip
placement statistics and the statistics on area and ECO placement
operations. When you run a full-chip placement, the HISTORY
subsection is reset. The TOTAL RUN TIME subsection provides the
sum of a full-chip placement and all area and ECO placement
operations.
Global Routing Information

The Global Routing Information section reports the number of global
routing cell boundaries (horizontal and vertical) that are over
capacity.
Timing/Optimization Information
A sample Timing/Optimization Information section follows.
This section reports information for ideal timing and the various
optimization processes that you can run throughout the design flow:

7-27
IDEAL
This is the timing without any interconnect and is theoretically the
best answer possible (there can be some optimization without
interconnect, some remapping, and so on). Generally, when this
is not a reasonable number, you need to go back to synthesis.
PRE
These statistics occur after preplacement optimizationthat is,
after high-fanout net analysis, remapping, and simple area
recovery are run. This is a starting point.
IPO
These statistics occur after in-placement optimization.
In-placement optimization intermixes optimization with
placement to minimize congestion and optimize timing. At each
stage, there might not be a valid, complete placement, but
optimization can be executed to help the timing-driven
placement. Although this optimization should remove any large
errors, it is not complete, because not all transition/capacitance/
hold violations are fixed.
Depending on the design, in-placement optimization can be
executed several times throughout the placementit should get
progressively better. Because this happens in the middle of
placement, the timing result does not take into account all of the
placement moves associated with optimization. This is why
POST can be worse than IN (if there were placement moves due
to sizing, buffers, and so on that had not been accounted for in
the IN place number).

7-28
PPO1
These statistics occur after postplacement optimization,
phase 1 (astPostPS1).
PPO
These statistics occur after postplacement optimization,
phase 2 (astPostPS).
GLOBAL
These statistics occur after global routing optimization
(astPostGR).
IN-RT
These statistics occur after postrouting optimization
(axgAdvRouteOpt).
DETAIL
These statistics occur after postrouting detail optimization
(astPostRT).
DRC Information
The DRC Information section reports the number of shorts, the
number of different net spacing violations, and the total number of
errors.

7-29

To check timing data before actually generating a timing report, use
the astTimingDataCheck command. Using this command also
helps locate potential problems in the design.
To check timing data,
1. Enter astTimingDataCheck or choose Timing > AstroTime
Timing Data Check.
The Timing Data Check dialog box appears.
Brief explanations of the options in this dialog box follow. For

additional descriptions of the astTimingDataCheck command
options, see Physical Implementation Online Help.
7-30
- Unconstrained Endpoints
Reports all the primary outputs and registers data pins that are
not time-constrained in the design and are not on any false
paths.
- No Input Delay
Reports all the primary inputs that have no delay specified.
Astro assumes that DEFAULT CLOCK is the reference clock
for these inputs.
- No Clock Fanin
Reports all the register clock pins that are not connected to any
clock signal.
- Multiple Clock fanins
Reports all the register clock pins that can be reached from
multiple clock signals.
- Combinational feedback loops
Reports all the combinational loops found in the design. These
loops are automatically broken by Astro, and you can use the
ataSetDisableTiming command to break such loops
manually.
- Latch Fanout
Reports all the latch pairs with the same clock. The output of
one latch goes to the input of the other latch in the pair. Also
reports latch self-loops, a situation where a latch output might
drive its input through combination logic. The data can flow
through the latch multiple times during the active phase.

7-31
A situation where a timing path goes from latch to latch and

both are driven by the same clock within the same path can
cause open circuits and loss of data.
- Generated Clock Network
Reports all the generated clocks that are not driven by a
master clock signal and also detects any loops within the
generated clocks. Basically this is the derived clock, or the
clock signal derived from the output of a flip-flop or latch.
- Master-Slave Clock Separation
Reports all the master-slave latch pairs, with different clocks,
that violate the clock separation you have specified. Similar to
latch fanout, but the latches are driven by different clocks or
with a different clock phase. The clock separation is defined as
the time difference between the inactive edge of the first clock
and the active edge of the second clock. Use this method to
avoid the overlap between the two latches when both can
become active.
Sometimes this causes timing analysis or optimization
problems when the clock separation is not sufficient.
- Number of Significant Digits
Indicates the number of significant digits for calculating clock
separation.

Run the astCheckDesign command at any time in the design flow
to report useful information about the design and libraries. It is a
valuable aid to understanding the design, offering hints and allowing

7-32
debugging. It performs a check of the design for optimization to get

a better feel of what is contained in the design, what might need
fixing, or what could help improve the design.
Note:
Currently the design needs to be placed for the
astCheckDesign command to work. A simple way to do this is
with the astFastPlace command (geGetEditCell). Be
aware that this quick placement is not based on congestion,
timing, or other normal placement parameters. Cells are simply
placed in allowed locations.
To check the design,
1. Enter astCheckDesign.
The Write Check Design dialog box appears.
2. Next to File Name, enter the name of the file to be generated.


7-33
The Limit settings as well as the Verbose option control how

much information is printed to the file.
For additional descriptions of the astCheckDesign command
4. Click OK.
A report file is printed.
Information
The check design report includes information such as
Current Ignore Interconnect Timing
Current Include Interconnect Timing
Design Information
- Cell instances, macro instances
- Pins, nets
- Utilization, hierarchy preservation, scan chain connections
Timing Information
- Operating condition, LPE information
- Environment panel settings
- Thresholds
Optimization Information
- Target setup slack, target hold slack

7-34
- Maximum fanout
- Target utilization, maximum utilization
SDC Information
- Clocks, generated clocks, global constraints
Buffer/Inverters in Design
HFN Nets, HFN Other Nets
HFN Cant Break Nets With Violations
DontTouch Nets With Violations
Library Information
- Buffers/inverters sorted by driver resistance
- Buffers/inverters sorted by area
- Buffers/inverters sorted by delay
- Buffers/inverters sorted by maximum transition
- Buffers/inverters sorted by maximum capacitance
- DontUse buffers/Inverters sorted by area
- Library sorted by driver resistance
- Library sorted by area
- Library sorted by maximum transition
- Library sorted by maximum capacitance

7-35
Hints
The check design report includes hints on what to do, based on what
is found in the design, such as the following:
Might be useful to set (axSetIntParam "pds"

"more_loc_in_ppo" 1) because macros exist.
Might be useful to add soft blockages to increase utilization to

help setup.
Large number of buffers exists in the design, pdsHFNCollapse

might be useful.
Scan chains should generally be removed before preplacement

or in-placement.
Clock buffers exist in the design.
Need to understand the impact of these nets because they

generally cannot be fixed.
Important to understand when these are necessary to fix.
Checking Timing Constraints

Consider the following questions when you are checking timing
constraints:
Are the SDC constraints accepted by the ataLoadSDC

command?
If accepted, are the constraints properly used?
Are the SDC constraints provided adequate for the design?

7-36
Is the timing analysis correct?
What are the effects of SDC on optimization?
It does not make sense to continue the optimization process until you
are fairly certain that these questions have been answered
satisfactorily. Astro provides several utilities and reports to handle
these issues.
During SDC loading with ataLoadSDC, the tool warns of

commands that are not accepted or have improper syntax and
ports, pins, cells, or nets that are not found.
The astTimingDataCheck command finds typical constraint

problems and concerns without ever placing the design.
Zero interconnect can hide SDC problems affecting optimization

of certain parts of a design. Evaluate timing closely after clocks
are inserted and postplacement optimization is completed and
prior to proceeding to routing. See Design Feasibility
Reporting Ideal Slack on page 8-63 for additional information.
Note:
To run zero interconnect timing in PrimeTime, do not provide any
wire load models in the .lib files read by PrimeTime. The .lib files
written by Astro do not contain wire load models.
Effects of Synopsys Design Constraints on Timing

Analysis and Optimization
Make sure you verify the effects of the SDC commands on the timing
analysis and optimization processes. Often you can use SDC
commands without realizing that the design constraints should be
changed slightly as a design goes through the optimization process.
Effects of Synopsys Design Constraints on Timing Analysis and Optimization

7-37
Astro attempts to match PrimeTime timing analysis as closely as

possible. In doing this, it attempts to handle constraints such as
disable timing and case analysis statements in the same way, by
disabling portions of the circuit. This makes correlation more
consistent.
However, the timing analysis result is passed to optimization. If part
of the circuit does not have timing analysis performed, the
optimization tool can miss some constraints, such as maximum
transition. Astro continues to be improved so that this situation does
not occur.
To help determine whether there is a problem with maximum
transition and maximum capacitance constraints, you can examine
various timing reports. Do the following:
Generate a timing report with normal settings. Make sure you

select Enable Default Clock in the Environment page of the
AstroTime Timing Setup (atTimingSetup) dialog box.
Remove all case analysis statements, and generate a timing

report.
If the case is set on the top-level port, add false paths for setup
and hold from the top-level port to all end ports, to eliminate
timing, using the default clock on inputs. Consider the following
example with case analysis set to the TEST port. To remove case
analysis, use the following Tcl commands:
"remove_case_analysis [get_ports {TEST}]"
"set_false_path -hold -rise -fall -from {TEST} \
-to {*}"
"set_false_path -setup -rise -fall -from {TEST} \
-to {*}"

7-38
Remove disable timing statements from the SDC, and generate

a timing report.
If the number of maximum transition or maximum capacitance

constraints changes, optimize the design to fix the problems. If setup
and hold constraints change, then at a minimum, optimize only the
transition and capacitance. When setup and hold are the same as
the normal operating conditions, it does not hurt to optimize setup
and hold as well as transition and capacitance at the same time.
Design Feasibility
See Performing Preplacement Optimization on page 8-58. It is best
to use the astCheckDesign command after preplacement
optimizations are completed.
Checking Library Inputs

Here are other questions to pose at the beginning of the design
process:
Are you using LM views?
Are the capacitance tables correctly constructed?
Which timing models are used in synthesis, place and route, and
timing sign-off?
These timing models should be consistent.
Are the timing models accurate enough for ultra deep submicron
processes?
Design Feasibility
7-39
Checking Logical Equivalence Information

Sometimes cells are not sized the way you would like. One cause
can be bad logical equivalence information in the libraries. To check,
you can use the astDumpLEQ command. The syntax is
astDumpLEQ "fileName"
This command determines the logical equivalence information to be

used by Astro. The library and cell must be open, and the cell must
be ready for timing analysis. Here is some sample output.
** class 151 ***
cell=dl04d4 type=BUFFER "volt_gr=0"
Z = I
cell=bufbd1 type=BUFFER "clock_cell" "volt_gr=0"
Z = I
cell=dl04d1 type=BUFFER "delay_cell" "volt_gr=0"
Adjusting Preroute Pessimism and Optimism of

Capacitances
Guidelines for adjusting preroute RC are design dependent.
However, preroute RC results that are within a reasonable range and
with as small a pessimistic range as possible are preferable in
postrouting for predicting the design closure quality and achieving a
consistent design convergence.
Make the preroute RC a maximum of 3 to 5 percent pessimistic and
then use routing optimizations to close the remaining nets.
The default setting for adjusting preroute capacitance in Astro is
axSetRealParam "ek" "capMultiplier" 1.05

7-40
The default setting for adjusting preroute resistance in Astro is

axSetRealParam "ek" "resMultiplier" 1.05
These values simply multiply the capacitance and resistance values

of all RC. They are meant to make the prerouting more pessimistic;
values that are too pessimistic might make the results worse. Also,
preroute timing to postroute timing can be 15 percent off, so you
might still have some nets to fix (use the axgAdvRouteOpt and
astPostRT commands to fix the problems).

Astro uses a heuristic to decide on the extraction mode, based on the
number of polygons and other factors. Therefore, when the correct
mode is not used during global routing, simply set the extraction
mode manually by using the LPE Mode option in the Parasitics page
of the AstroTime Timing Setup dialog box. For more information, see
Parasitics Page on page 6-38.
Checking TLU Capacitance Model Parameters

Often, mistakes are made during specification of options for the
timing model, parasitic model, and postrouting calculations in the
timing setup step. Before working on a design, examine the settings
and change them to conform to your own design parameters.
Following are the main options you need to pay attention to when
using TLU capacitance models:

7-41
Layer Scope
This is the number of layers the TLU model considers to be the
interlayer capacitance from above and below the reference
layers. The default is set to maxMetalLayerNum + 1 in Astro.
Use the ekSetLayerScope command to set it in Astro.
Note:
By default, this number is 2 in Apollo, so be careful to
synchronize the setting when comparing Apollo and Astro.
Geometry Scaling Factor

Affects the length and width of all wires. According to the factor
you set, you need to adjust related physical properties. Be sure
to use the cmCreateCapModel command to change the width
and spacing of the layers to the scaled value; the tool does not
change it automatically.
Maximum Distance to Extract Lateral Capacitance

Determines the size of a window in which the application
searches for the same layer neighbor of a given rectangle. When
none are found in the given distance (expressed in units of
minimum spacing), the application assumes there is a virtual
rectangle located at the specified distance for the capacitance
extraction. The default is 8 in Astro. Use the
ekSetMaxIntraCapDistRatio command to set it in Astro
when necessary.
In a design where routing is low-densitythat is, the distance
between the wires is extensivebe careful not to set it to a value
that is too small to reflect the real situation.

7-42
Note:
By default, this number is 3 in Apollo, so be careful to
synchronize the setting when comparing Apollo and Astro.
Cap Multiplier (Global)

This works for linear models only, and you see it only in Apollo.
Astro works only for table lookup, so there are no such settings.
Also in the technology file are Cap Multiplier (Individual) settings
for each layer. Apollo and Astro both take them.
Note:
The following should be set to match the capacitance
multipliers in the technology file, when one exists:
(axSetRealParam "ek" "capMultiplier" 1.05)
and
(axSetRealParam "ek" "resMultiplier" 1.05)

This section describes how to use TLUPlus capacitance and
resistance models with Astro for extraction.
Generating TLUPlus Capacitance and Resistance

Models
The Star-RCXT tool can generate TLUPlus capacitance and
resistance models for extraction in Astro. These models provide
greater correlation between Astro and Star-RCXT capacitance and
resistance extraction than the standard TLU models. The

7-43
capacitance and resistance models also allow Astro to accurately

handle advanced process rules beyond the capability of the original
cmCreateCapModel command, which, for example, cannot
consider nonplanar processes.
Before TLUPlus models can be generated (with the Star-RCXT
grdgenxo command), you need a description of the process
technology in Interconnect Technology Format (ITF), which can
either be supplied by the foundry or be created by you. You also need
a map file to map the process layers to the Milkyway library
technology file.
Generating TLUPlus models and using them in Astro includes these
major steps:
1. In Star-RCXT create one or more binary CapTable/ResModel
files. Use grdgenxo with the -itf2TLUPlus option. For
descriptions of the grdgenxo command options, see the
Star-RCXT documentation.
The output is a binary table lookup file. By default, grdgenxo
assumes the following: There are nominal operating conditions
(for CapTable names only), table dimensions of 5x16, picofarad
and micron units (for ITF as well as Milkyway technology files),
and grid points that are multiples of the minimum width and
spacing values.
2. Attach the ITF file and CapTable files to the Milkyway library. Use
the cmITFToTLUPlus command.
This command lets you encrypt the ITF file so it cannot be
accessed by external tools. For information on the
cmITFToTLUPlus options, see Physical Implementation Online
Help.

7-44
3. In Astro, enable TLUPlus models. Use the ekSetTLUPlus

Scheme function. For example,
ekSetTLUPlus (geGetEditCell) #t
or click TLU+, next to Capacitance Model, in the Parasitics page

of the AstroTime Timing Setup dialog box (atTimingSetup).
After TLUPlus models are created and enabled, you can perform
parasitic extraction, timing analysis, and so on as usual in Astro.
Astro reads both layer and via resistance information from the
TLUPlus file.
Note:
The TLUPlus binary file is stored as an attached file in the library
directory, as indicated in the log file, and is named lib_3 or lib_4,
and so on. Consequently, unlike normal table lookups, the
capacitance tables are not stored in the technology file.
You can use grdgenxo with the -inc option to identify changes
made to CONDUCTOR parameters and to automatically remove and
regenerate the capacitive tables (improves grdgenxo runtime). For
information, see the Star-RCXT documentation.
TLUPlus Resistance Model Considerations

If the ITF file does not contain a valid ResModel, Astro obtains the
ResModel defined in the technology file. However, to handle features
such as width-spacing dependent resistance, thickness variation
resistance, and temperature deration, you must use the TLUPlus
resistance model.
By using the TLUPlus resistance model, you can better define
process parameters that are dependent on width, space, density,
and temperature such as ETCH, RPSQ, THICKNESS,
7-45
THICKNESS_VS_DENSITY,
DENSITY_BOX_WEIGHTING_FACTOR, RPSQ_VS_SI_WIDTH,
ETCH_VS_WIDTH_SPACING, RPSQ_VS_WIDTH_SPACING,
THICKNESS_VS_WIDTH_SPACING, and temperature deration
(GLOBAL_TEMPERATURE, CRT1, CRT2). During RC extraction,
you should consider using these complex variations to get accurate
capacitance and resistance values for timing closure analysis.
For more information, see the Star-RCXT documentation.
Working With TLUPlus Model Files

You can view, edit, and update the TLUPlus information stored in the
Milkyway database by using the cmDumpTLUPlus and
cmReplaceTLUPlus commands.
You use the cmDumpTLUPlus command to write the TLUPlus
information to an ASCII file, which you can view and edit with a text
editor. You can save changes made to the TLUPlus data back to the
Milkyway database by using the cmReplaceTLUPlus command.
Before updating, the cmReplaceTLUPlus command creates a
backup TLUPlus data file named libname.TLUPlus_Replaced.
For information on the cmDumpTLUPlus and cmReplaceTLUPlus

7-46

By default, Astro analyzes only the non-inverting sense of the clock
for a non-unate clock network. To specify that both the inverting
sense and non-inverting sense of the clock are to be analyzed
simultaneously, set the non_unate_clock_compatibility
parameter to its non-default value FALSE. Enter
axSetIntParam "ata" "non_unate_clock_compatibility" FALSE
Use the set_clock_sense command to specify the clock sense

where multiple senses of the same clock have merged together
(such as a non-unate clock network), and it is ambiguous which
sense of the clock the tool should pick. In this case, user-defined
sense propagates forward from the given pins.
The syntax is
set_clock_sense
[-positive]
[-negative]
[-clocks clocks]
port_pin_list
Option
Description
-positive
Specifies positive unateness
-negative
Specifies negative unateness
-clocks
Specifies a list of clock objects to which the

specified clock sense is applied
port_pin_list
Specifies a list of ports and/or pins on which the

clock sense is set

7-47
This command supports the following clock senses:
Non-inverting clock sense, using the -positive option
Inverting clock sense, using the -negative option
If the -clocks option is used, only the specified clock domains are
applied. Otherwise, all clocks passing through the given pin objects
are considered.
Astro will issue warning messages if the specified sense on given
pins cannot be respected in the case where there is predefined
unateness for given pins. Hierarchical pin is not supported.
To undo set_clock_sense, use the remove_clock_sense
command.

7-48
8
Placement and Placement Optimizations 8
After you have a design set up, you are ready to place your design
and run placement optimizations, including preplacement
optimization, in-placement optimization, and postplacement
optimization before clock tree synthesis and after clock tree
synthesis.
Placement Flow
Setting Placement Common Options
Placing Cells Close to Magnet Objects
Performing Automatic Placement and Optimization Before Clock

Tree Synthesis
Evaluating Automatic Placement
8-1
Optimizing Power
Performing Clock Tree Synthesis
Performing Postplacement Optimization After Clock Tree

Synthesis
Optimizing Clock Trees
Optimizing Clock Groups
Carrying Out Additional Processes
Using Alternative Placement and Optimization Commands
Chapter 8: Placement and Placement Optimizations

8-2
Placement Flow
Placement is performed in four optimization phases:
Preplacement optimization
In-placement optimization
Postplacement optimization before clock tree synthesis
Postplacement optimization after clock tree synthesis
You can run these placement optimization phases by using

automatic placement and optimization command, astAutoPlace,
or by using individual placement optimization commands
(astPrePS, astPlaceDesign, astPostPS1, and astPostPS).
The astAutoPlace command simplifies the placement
optimization flow. Use of astAutoPlace is the preferred method for
performing placement optimizations. Following are considerations
for using astAutoPlace rather than the individual placement
optimization commands:
The same global placement technology in Physical Compiler is

used in astAutoPlace. This works to achieve better overall
placement quality in terms of wire length.
The timing-driven placement option in astAutoPlace achieves

better timing and wire length.
The congestion-driven placement option in astAutoPlace

achieves better routability, especially for designs with
complicated floorplans. This helps reduce the runtime for the
routing process.
Placement Flow
8-3
The capacity for astAutoPlace is larger (as much as two times)

than the individual commands, due to better memory
management.
The combination of placement and optimization in

astAutoPlace achieves better timing closure.
The crosstalk prevention placement option in astAutoPlace

helps reduce crosstalk problems for designs of advanced
technology (0.13 microns and below).
The congestion removal option in astAutoPlace in the stage

after clock tree synthesis helps resolve the congestion caused by
clock tree synthesis or postplacement optimization. This
improves the routability of the final placement.
The equivalent Tcl command for astAutoPlace is auto_place.

(Use the Tcl mode online Help auto_place -help command to
list all options.)
The automatic placement optimization command is described in
Performing Automatic Placement and Optimization Before Clock
Tree Synthesis on page 8-17. The alternative placement
optimization commands and their related fine tuning commands are
described in Using Alternative Placement and Optimization
Commands on page 8-58.
For many designs, you can use the recommended flow. When you
use the astAutoPlace command to perform placement, you first
run that command to sequentially perform the preplacement
optimization, the in-placement optimization, and the postplacement
optimization before clock tree synthesis steps. After completing
these steps, the next step in the recommended design flow is clock

8-4
tree synthesis; after which, you return to the astAutoPlace

command to run the last step in the placement flow, postplacement
optimization after clock tree synthesis.
You can use astAutoPlace or the alternative placement and
optimization commands to customize the design flow. For example,
if you see congestion after running astAutoPlace, you might want
to use the astSeachRefine command (see Performing Search
and Refine on page 8-69) to improve cell placement, after which you
return to the astAutoPlace command to run the postplacement
stage.
The astAutoPlace command is a combination of many
commands; it merges processes provided by the stand-alone
commands. When you use stand-alone commands you have more
control over a process and can often analyze the results. For
example, astAutoPlace runs the astTopoHold command, but if
you want to do hold fixing only, you might choose to use the
stand-alone astTopoHold command (see Hold Slack Optimization
in Astro on page 8-96). Another stand-alone command is
astLenBI, which you can use to perform length-based buffer
insertion (see Maximum Wire Length on page 8-93).
Optimization commands, including the astAutoPlace command
and stand-alone placement optimization commands, generate
histogram slack reports that are printed in the log file. For more
information, see Optimization Histogram Reports on page 11-6.
The astAutoPlace command performs high-fanout net synthesis
at the preplacement optimization and in-placement optimization
stages. If the astAutoPlace command does not give satisfactory
results after these stages, another option is to run the astPrePlace
command, which calls the pdsHFNOptimization command, and
Placement Flow
8-5
run astPlaceDesign, which calls astFanoutSetup. The

following stand-alone commands are available for high-fanout net
synthesis:
astFanoutSetup
See Optimizing High-Fanout Nets on page 8-68.
pdsHFNOptimization
See High-Fanout Net Optimization on page 8-88.
astDesignRules
See Design Rule Fixing in Astro on page 8-87
astHFCTS (not recommended for signal net synthesis)

See Synthesizing High-Fanout Nets on page 9-109.
A general procedure for performing clock tree synthesis that fits

within the scope and flow of placement when using the
astAutoPlace command or when using the individual placement
optimization commands is described in Performing Clock Tree
Synthesis on page 8-36. If your design requires a different clock tree
synthesis strategy, see Chapter 9, Clock Tree Synthesis and Clock
Tree Optimizations for a detailed description of clock tree synthesis
options.
Astro uses topology-based optimization, which interacts with
placement and routing. For more information, see Topology-Based
Methodology on page 8-74.
You can perform inverter-only optimization with the astAutoPlace
command and the astPostRouteOpt command, as well as with
topology-based stand-alone optimization commands, such as

8-6
astTopoHold, astTopoSetup, astTopoTransCap, and

astFanoutSetup. For more information, see Inverter-Only
Optimization on page 11-7.
The placement and optimization flow is shown in Figure 8-1.
Placement Flow
8-7
Figure 8-1
Placement and Optimization Flow

From floorplanning
Set placement common options

astPlaceOptions
Perform magnet placement (optional)

astMagnetPlace
Perform preplacement, in-placement,

and postplacement optimizations
before clock tree synthesis
astAutoPlace
Evaluate placement
axgDisplayPLCongestionMap
axgDisplayCouplingCapMap
Perform power optimization

astPowerRecovery
Perform clock tree synthesis

astCTS
Perform postplacement optimization

after clock tree synthesis
astAutoPlace
Perform clock tree optimization

astCTO
To routing

8-8

You use the astPlaceOptions command to set the placement
common options for your design. The placement options affect all
placement-related commands.
The placement phase of the design flow places the cells in the core
area. You can weigh cell placement to optimize various factors of a
design by choosing the primary placement goal. When using
astPlaceDesign, do this by choosing Congestion or Timing
optimization modes in the AstroPlace Options dialog box. When
using astAutoPlace, do this by choosing placer options
(Congestion Driven, Timing Driven, IO Pin Placement, and Prevent
Crosstalk) in the Astro Auto Place dialog box.
To select the common placement options for your design,
1. Enter astPlaceOptions or choose InPlace > Placement
Common Options.
The AstroPlace Options dialog box appears.

8-9

8-10

Under Optimization Mode, select one of the following options:
- Congestion, which minimizes wire length and congestion in the
design.
- Timing, which places cells to meet timing requirements. The
Optimize Netlist option in the AstroPlace Design dialog box
(astPlaceDesign) is dimmed unless you select the Timing
option in this dialog box.
Note:
Remember that these options affect the astPlaceDesign
command only; the astAutoPlace command is driven by its
own placer options (Congestion Driven, Timing Driven, IO Pin
Placement, and Prevent Crosstalk).
Under Placement Constraint, the options are
- Plan Group Astro respects the plan group placement regions
you created using the axgHierPlan command.
Select all to place all cell instances of the plan group into a
soft macro.
Select fixed only to place only fixed cell instances of the plan
group into a soft macro.
- Region Astro honors the placement regions you created and
defined, using the axgCreateRegion or astPlaceDesign
commands.

8-11
Select a rigidity value of 1 to 10, with 10 being the most rigid or

hard constraint for a region or group and 1 being the least rigid.
When the value is smaller than 10, the constraints are relaxed,
and therefore, placement can be optimized by the place option
based on connectivity. This provides a smooth trade-off
between regional constraints and nonregional constraints and
is similar for group constraints.
The axgCreateRegion command allows you to define a
different rigidity for each region, to be honored by the
placement command. When you specify rigidity with
axgCreateRegion, Astro applies the value to the region and
ignores the rigidity value specified with the
astPlaceOptions command (the astPlaceOptions
command will not override the regions rigidity value). When
you do not specify a rigidity value with axgCreateRegion,
the value that is set with astPlaceOptions is applied to all
regions.
- constraint file Enter the name of the text file that contains
your placement constraints.
For example, you can set net weights that affect global
placement (and magnet placement) with the netWeight
constraint. The syntax is
netWeight netPattern contrValueVer constValueHor
For example,
netWeight /core_datapath/net1 10 10
Under Location Constraint, the options are

- Consider Preroute Types Astro recognizes the prerouted
nets of the types you select.

8-12
- No Cells under Preroute of Astro does not place cells under

the prerouted nets on the metal layers you specify. Select all
preroute layers unless the preroutes are dense.
- No Cells Under Via Astro does not place cells under the vias
you specify.
- Short Checking at Preroute of Astro does not place cells
under the prerouted nets on the layers you specify if a short
occurs or if Astro cannot access pins. Astro places the cells
under the preroute layers if a short does not occur and it can
access pins
- No Pins under Preroute of Astro prevents pins of standard
cells from being placed under the metal layers you specify. This
means that a standard is not be placed in a location when any
pin of the cell overlaps with a preroute of the metal layer. For
example, if M3 is selected, a standard cell will not be placed
when any of its pins (regardless of the pins metal layer)
overlaps with a preroute on M3.
Avoiding pin overlap with preroutes improves routability
because there are less routing resources under preroutes due
to the preroute and any vias and contacts along the preroutes.
The default setting is off (pins are allowed to be placed under
preroutes).
Note:
If you select the No Cells Under Preroute of and Short
Checking at Preroute of options for the same layer, cells are
not placed under the prerouted power, ground, and clock nets
on the selected layer, even when there are no shorts and Astro
can access pins.

8-13
Ignore off-grid via region Select if you want the placer to ignore
all off-grid via regions of a pin. Use this option when you have
pins with off-grid via regions but do not want to use off-grid
routing. The exception is when a pin does not have any on-grid
via regions; in this case, Astro considers all the pins via regions
to avoid nonroutable placement.

You can do a magnet placement by using the astMagnetPlace
command. When you use this command, certain fixed objects, such
as macros, are defined as magnets, and all standard cells that are
connected to those magnets are placed close to the magnets.
Magnet placement can help to reach timing convergence and to
overcome certain difficulties specific to complex floorplans.
Use astMagnetPlace before performing global placement, that is,
at a point in the design flow where the majority of the standard cells
are not yet placed (they are outside the chip). For best results, make
sure there is sufficient empty space near the magnets to
accommodate the cells being pulled close to the magnets.
Defining Magnets
To perform magnet placement, you must first define, or select, the
magnets by using the select operations, accessible from the Select
menu. Typically, a fixed object with net connections to placeable
standard cells, such as macros, I/O pins, and pads, can become a
magnet.

8-14
Specifying Net Weight Constraints

You can specify that magnet placement take into account net weight
constraints by using the magnetPlaceByWt parameter (by default,
these constraints are ignored). To enable net weight consideration,
enter
axSetIntParam "place" "magnetPlaceByWt" 1
In this case, instead of using maximum magnetic force to pull a

standard cell to the location of the magnet, astMagnetPlace
scales the magnetic force to be exerted. The scaling is based on the
weight settings you specify with the netWeight placement
constraint.
The syntax is
netWeight <netPattern> <contrValueVer> <constValueHor>
where the range of weight values is 0 to 255. For example, a weight

setting of 255 allows the full magnetic force to be exerted on the
standard cell; a weight setting of 128 reduces the force to half and
moves the standard cell halfway between its original location and the
magnet; a weight of 0 does not move the standard cell at all.
You can use the AstroPlace Options dialog box (astAutoPlace) to
load the text file that contains your net weight constraints. Keep in
mind that to achieve a meaningful effect, all the nets in your design
must be properly weighted. The default weight is 1, which gives very
little pulling force when you enable the magnetPlaceByWt switch.

8-15
Important:
The weight settings for magnet placement are generally not
suitable for global placement. Make sure you use a different set
of weights when performing global placement.
Using astMagnetPlace
After you select your magnets, you are ready to use
astMagnetPlace. This command identifies the cells to be placed
and places the cells in legal locations. It also issues a warning for
magnets that are ignored, such as vias or blockages.
To run magnet placement,
1. Enter astMagnetPlace.
The AstroPlace Magnet Placement dialog box appears.

8-16
- Select Move Fixed or Move Softfixed to specify that cells

marked fixed or soft fixed can be moved. Either option allows
cells to be placed inside soft blockages; no cells will be placed
inside hard blockages.
- Next to Placement Status, select whether the cells, after they
are legally placed close to the magnets, are to be marked orig
(retain their original placement status), fixed, or softfixed.
- Next to Logical Level, enter a number to define how many
levels of logic will collect the cells to be placed. For example, a
cell directly connected to a magnet has logical level 1, a cell
connected to a level-1 cell has logical level 2, and so forth.
Cells beyond the specified logic level will not be moved by the
magnet.
- Select Ignore Soft Blockages to allow cells that are attracted by
magnets to be placed inside soft blockages.
- Select Stop at Sequential Cells to specify that cells beyond a
sequential cell should not be pulled close to a magnet even
though the cells are within the specified logic level limit.
You can click Undo to make the placement revert to the state it
was in before any cell was moved. Clicking Undo a second time
has no effect.
Performing Automatic Placement and Optimization

Before Clock Tree Synthesis
You use the astAutoPlace command to sequentially run
placement optimizations. The astAutoPlace command controls
the placement optimization flow by combining the following steps:
Performing Automatic Placement and Optimization Before Clock Tree Synthesis
8-17
preplacement optimization, in-placement optimization,

postplacement optimization before clock tree synthesis, and
postplacement optimization after clock tree synthesis.
Preplacement optimization optimizes the netlist prior to

performing placement. It generates an initial placement (on by
default) to get the wiring information before optimizing the netlist.
Preplacement optimization also has options to collapse
noncritical buffers (on by default) and downsize cells (off by
default) so that the netlist is easier to place, as well as options to
synthesize high-fanout nets (on by default) and perform quick
synthesis (on by default).
In-placement optimization performs iterations of setup fixing,

incremental timing, and congestion-driven placement.
In-placement optimization has an option to perform netlist
changes (on by default).
Postplacement optimization performs netlist optimization with

ideal clocks. Used before clock tree synthesis, it performs a more
specific timing optimization of the netlist and the layout, including
quick fixing of setup and hold violations and maximum transition
and maximum capacitance violations. Postplacement
optimization has options to perform optimization based on global
routing, to prevent crosstalk violations, and to fix
maximum-length violations (all off by default).
Postplacement optimization after clock tree synthesis improves

the timing results of your design with propagated clocks. It takes
the clock tree into account so that the clock skew can be
preserved. Postplacement optimization after clock tree synthesis
has an option to perform congestion removal before running
optimization (off by default).

8-18
Before you run astAutoPlace, use the astPlaceOptions

command to set the placement common options for your design.
Note that the optimization modes (Congestion and Timing) in the
AstroPlace Options dialog box are not honored by astAutoPlace.
Instead you set the placer options (Congestion Driven, Timing
Driven, IO Pin Placement, and Prevent Crosstalk) in the Astro Auto
Place dialog box.
Remember that the recommended flow is to first run the
preplacement, in-placement, and postplacement optimization
processes (Pre-Place, In-Place, and Post-Place are on by default in
the Astro Auto Place dialog box), and then perform clock tree
synthesis steps (Post-CTS is off by default). After clock tree
synthesis, run astAutoPlace with only Post-CTS enabled (and
congestion removal if desired). Make sure you deselect Pre-Place,
In-Place, and Post-Place.
Note:
If you have a placed design from Physical Compiler, you might
choose to run the postplacement after clock tree synthesis
process by selecting Post-CTS only.
It is recommended that you run astAutoPlace with the default
options, including those shown in the expanded window that appears
when you click Detail Options. The options in the expanded window
apply only to the specific design stages, and are grouped
accordingly. They are active only when the corresponding Stage
option is enabled; otherwise, they cannot be used and appear
dimmed. If your design requirements are not met using the default
settings, you can change them. The options you are most likely to
change are located in the expanded window.

8-19
Using Double-Height Cells

You can specify that optimization will use double-height cells with the
useDHCell parameter. Enter
axSetIntParam "place" "useDHCell" 1
By default, this parameter is set to 0 (optimization will not use

double-height cells).
Setting the Size Only Constraint

Use the astSetSizeOnly command to set or reset the
size_only attribute on specific cell instances or all the cell
instances of a cell master. When cells are marked as size_only,
the following occurs:
Optimization can size (upsize or downsize) the cells.
Placement can move the cells for small legalization purposes.
Note:
Astro automatically switches from row-based overlap removal to
area-based overlap removal when the design has cell instances
that are marked with the size_only attribute.
To view the size_only constraints, as well as other constraints in
your design, use the astWriteDC command (for information, see
Writing ast Design Constraint Commands on page 6-14).

8-20
Defining Placement Restrictions for Small (Sliver)

Areas
Automatic placement supports the sliver-size feature that is already
part of the JupiterXT tool. During placement, blockages are
dynamically created over slivers of the placeable area that are
formed by nearby placement blockages or fixed macros (see the
following figure). Objects cannot be placed in sliver areas, which
helps alleviate congestion.
Use the sliver_size parameter to define the minimum channel

size (in microns) that can be populated by standard cells. Keep in
mind that a sliver is a channel that is too small to have standard cells
placed in it. Such a channel, or sliver, can be created between any
two of the following objects (the object must occupy at least 1/100th
of the total chip area):
Fixed or movable hard macros
Placement blockages
Plan group edges
Core area edges

8-21
The keepout margin of hard macros is not included in the sliver size.
Hard macro slivers are measured from the edge of the keepout
margin, not from the edge of the macro.
The syntax is
axSetIntParam "place" "sliver_size" value
For example, to specify the maximum size of a sliver to be blocked

out (no placement allowed) as 10 microns, enter
axSetIntParam "place" "sliver_size" 10
The default sliver size is 0.
Using astAutoPlace
To perform placement and optimizations before clock tree synthesis,
1. Enter astAutoPlace or choose InPlace > AutoPlace.
The Astro Auto Place dialog box appears.

8-22
2. Next to Effort, select an effort level to be spent on placement

optimization (Prototype, Low, Medium, or High). Prototype is
fastest, but the total wire length is higher than with the other
efforts. High is slowest but gives the most optimized total wire
length results. The default is Medium.
3. Next to Stage, make sure Pre-Place, In-Place, and Post-Place
are selected. For information about using the Post-CTS stage,
see Performing Postplacement Optimization After Clock Tree
Synthesis on page 8-40.
4. Under Placer Options, select one or more of the following:
- Congestion Driven, which performs congestion-driven
placement during in-placement optimization.
- Timing Driven, which performs timing-driven placement during
in-placement optimization.

8-23
- IO Pin Placement, which optimizes I/O pin location during

in-placement optimization.
- Prevent Crosstalk, which performs crosstalk prevention during
in-placement optimization and during postplacement
optimization after clock tree synthesis when you select
Congestion Removal (under Post-CTS Optimization in the
expanded window). The maximum wire density is lowered to
reduce coupling capacitance and therefore crosstalk.
5. Under Optimization Tasks, select one or more of the following:
- Fix Setup, which fixes setup slack violations during the
optimization.
- Fix Transition, which fixes maximum transition violations during
the optimization.
- Fix Hold, which fixes hold slack violations during
postplacement optimization and postplacement optimization
after clock tree synthesis. It is recommended that you not fix
hold until after performing clock tree synthesis.
- Fix Capacitance, which fixes maximum capacitance violations
during the optimization.
6. Under Optimization Options, select from the following:
- Logic Remapping, which is used during the setup slack
optimization and attempts to reduce the number of stages in a
critical path to improve overall timing.
- Area Recovery, which reduces the area in the design by
downsizing cells and removing buffers, as long as no new
timing violations occur.

8-24
7. Click Detail Options to use the options in the expanded window

that appears. Remember that options are active only when the
corresponding Stage option is enabled; otherwise they cannot be
used and appear dimmed.

8-25
For the Pre-Place stage, in the Pre-Place Optimization area

select from the following options:
- Collapse Buffer/Inverter, which collapses all buffer and
inverter-pair trees that have a fanout larger than the supplied
threshold (the default is 10). A buffer that has an input net with
fanouts greater than the threshold is considered noncritical.
When the value is set to 1 or 0, all buffer and inverter pairs are
removed from the design. Removing all buffers can slow down
the optimization, because in general, these nets have to be
buffered again later in the flow.
- Cell Down Size, which downsizes all cells by a certain level
(the default is 1). When levels are set to 1, the next smallest
size of cell for the given logically equivalent class is used.
When levels are set to 0, all cells are downsized to the smallest
possible size. This is useful when the synthesis was completed
with excessive wire load models or when the design cannot fit
into the floorplan. The impact on runtime can be severe
because many cells might have to be sized up later in order to
achieve timing closure. Cell Down Size is off by default.
- Initial Placement, which performs a full quick placement on the
design. A legal placement must exist for preplace optimization
to be completed. When the design is already placed and you
want to keep the placement, deselect this option.
- HFN Synthesis, which performs high-fanout synthesis on nets
with fanouts greater than the high-fanout threshold specified in
the Optimization page of the AstroTime Timing Setup dialog
- Quick Synthesis, which performs ideal (only gate capacitance,
no wire load) optimization for improving the setup slack. In
addition, quick synthesis fixes transition capacitance when you
select Fix Transition under Optimization Tasks.
8-26
For the In-Place stage, in the In-Place Optimization area you can
select Netlist Change, which performs netlist changes for fixing
setup violations during in-placement optimization.
For the Post-Place stage, in the Post-Place Optimization area
select from the following options:
- Use Global Routing, which performs global routing first, after
which design rule fixing is performed, and then the routing
removed. This flow is useful for top-level designs or for designs
that have several channels between macros.
- Prevent Crosstalk, where crosstalk noise is estimated from the
congestion, and noise is computed based on the estimated
aggressors. From this information, violating nets are fixed by
increasing the driver strength or by buffering the net. This
technique attempts to preserve the current timing of the design
and skips prevention when the change causes too much timing
degradation.
- Fix Max Length, which limits all nets to the specified length by
inserting buffers.
For information about the Post-CTS Optimization area, see
Performing Postplacement Optimization After Clock Tree
Synthesis on page 8-40.
8. Click OK.
Note:
If the astAutoPlace command does not give satisfactory
results after the preplacement, in-placement, and postplacement
stages, another option is to run astMagnetPlace. This
command seeds the locations of standard cells to magnet
objects (typically macros) before proceeding to clock tree

8-27
synthesis. After running astMagnetPlace, rerun

astAutoPlace. For more information, see Placing Cells Close
to Magnet Objects on page 8-14.

After performing automatic placement, evaluate the placement and
make changes to improve the routability of the design. To help
evaluate the placement, use a congestion map and the placement
statistics listed in the command window or the place and route
summary report. (See Place and Route Summary Report on
page 7-25.) You can also display coupling capacitance maps at the
placement stage of the design flow.
About Congestion Maps

During data preparation, Astro divides the routing area into global
routing cells, as shown in Figure 8-2.

8-28
Figure 8-2
Routing Area Divisions
Wire tracks
Global routing
cells
During placement, Astro calculates routing congestion, based on the

availability of wire tracks inside the global routing cells. Using these
routing congestion calculations, Astro produces a placement
congestion map that shows the estimated amount of routing
congestion within the design. Likewise, global routing produces a
global routing congestion map that also shows the estimated amount
of routing congestion within the design. The congestion maps look
similar, but the global routing congestion map is more accurate and
takes longer to create.
Astro displays both the placement and global routing congestion
maps as one-dimensional or two-dimensional. The one-dimensional
congestion map appears along the bottom and left edges of the
design. It indicates the estimated routing congestion throughout the
design. The two-dimensional congestion map displays the edges of

8-29
overflowing global routing cells in colors reflecting the severity of the

overflow. Both the one-dimensional and the two-dimensional
congestion maps are shown in Figure 8-3.
Figure 8-3
Sample Congestion Maps
Two-dimensional congestion map shows the edges of the overflowing global routing
cells. The color of the global routing cell edge in your graphics window shows the
severity of the overflow.
Macro cell
One-dimensional
congestion map
for vertical
routing
The demand is
greater than the
capacity for vertical
routing crossing
this line.
Standard cells
Macro cell
One-dimensional congestion
map red line

8-30
Macro cell
One-dimensional congestion map

for horizontal routing
Displaying Placement Congestion Maps

After automatic placement, Astro calculates routing congestion and
displays a one-dimensional or two-dimensional congestion map.
Use the congestion maps to examine the areas where wire track
demand exceeds supply.
To display a placement congestion map,
1. Enter axgDisplayPLCongestionMap or choose InPlace >
Placement Maps Display Congestion Map.
The Placement Congestion Map dialog box appears.
2. Select the options or keep defaults. (The visibility display defaults

are 1-D, 2-D, and text.)

8-31
- 1-D Displays a one-dimensional congestion map that

consists of bars at the bottom and left edges of the design. The
red areas of the display indicate areas of the design where
routing resources are insufficient because of excessive
congestion. To view the specific areas causing the congestion,
display a two-dimensional congestion map.
- 2-D Displays a two-dimensional congestion map that
consists of a grid of global routing cells, with colors indicating
the utilization of wire tracks through each edge of each global
routing cell.
- text Displays numbers to indicate how many tracks are used
along each horizontal and vertical section of the 1-D map, as
well as numbers to indicate the demand or supply of tracks
intersecting the edges of each global routing cell of the 2-D
map. For example, 6/5 means six wire tracks are needed but
only five wire tracks are available.
For descriptions of all the axgDisplayPLCongestionMap
To disable the display of a congestion map, click Clear.
Updating Placement Congestion Maps

Update the congestion map with the axgUpdateCongMap
command every time you perform a placement command. The
axgUpdateCongMap command considers spacing and wide-wire
variable routing rules, as well as shielding variable routing rules,
when calculating congestion.

8-32
To update placement congestion maps,
Enter axgUpdateCongMap or choose InPlace > Placement

Maps - Update Congestion Maps(s)!.
Saving and Loading Placement Congestion Maps

You can save placement congestion maps and load them, enabling
you to evaluate the effect of optimizations on congestion in your
design.
Use the axgSavePLCongMap command to save and name

placement congestion maps that are being displayed for the
current design.
The syntax is
axgSavePLCongMap cellId congMapName
Use the axgLoadPLCongMap to load and display a placement

congestion map previously saved with the axgSavePLCongMap
command. The axgLoadPLCongMap command also prints a list
of placement congestion maps currently saved.
The syntax is
axgLoadPLCongMap cellId congMapName
Generating and Displaying Coupling Capacitance Maps

Use the ekGenVRCCMapAttachFile command to generate a
coupling capacitance map at the placement stage. The syntax is
ekGenVRCCMapAttachFile (geGetEditEcll)

8-33
Use the axgDisplayCouplingCapMap to display the placement

coupling map.
To display a placement coupling capacitance map,
1. Enter axgDisplayCouplingCapMap.
The Coupling Cap Map dialog box appears.
2. Next to Type, make sure Placement is selected.

3. Set the display options or keep defaults.
4. Click OK.

8-34
Optimizing Power
Use the astPowerRecovery command to perform power
optimization after postplacement optimization. Typically, you
optimize for timing and then optimize for power, preserving setup,
hold, transition, and capacitance. Postplacement power optimization
sizes and removes buffers.
To begin power optimization,
1. Enter astPowerRecovery or choose PostPlace >
Optimization Power Recovery.
The Power Recovery dialog box appears.
2. Select the timing constraints to be maintained during the power

recovery.
You can also specify that during preroute power recovery, buffers
can be removed in addition to the cell downsizing.
3. Click OK.
Optimizing Power
8-35
The astPowerRecover command uses a leakage-based

approach.
You can also use astPowerRecovery to do prerouting power
optimization, which uses logical-equivalent cells to downsize and
reduce leakage power (identical to postplacement area recovery).
When you run astPowerRecovery at the postrouting stage of the
design flow, footprint matching can be used to minimize the extent of
design changes (for more information, see Optimizing Power After
Detail Routing on page 11-15).

This section describes a general method for performing clock tree
synthesis. If your design requires a different clock tree strategy, see
Chapter 9, Clock Tree Synthesis and Clock Tree Optimizations for
a complete description of the clock tree synthesis optimization flows.

Preparing Clocks
To select the clock common options,
1. Enter astClockOptions or choose Clock > Clock Common
Options.
The Clock Common Options dialog box appears.

8-36

For descriptions of the astClockOptions command options,
see Setting Clock Tree Synthesis Common Options and
Preparing Clocks on page 9-18.

8-37
Running Clock Tree Synthesis

Astro clock tree synthesis can improve the timing performance of a
chip by carefully distributing clock signals to each synchronous pin,
using balanced multilevel clock trees based on accurate layout
information.
To synthesize clock trees,
1. Enter astCTS or choose Clock > Clock Tree Synthesis
Clock Tree Synthesis.
The Clock Tree Synthesis dialog box appears.

For descriptions of the astCTS command options, see
Performing Clock Tree Synthesis After Placement on
page 9-62.

8-38
By default, Astro clock tree synthesis synthesizes clock trees under
the worst-case operating condition. Its function is to minimize global
skew using timing constraints you specify.
After running clock tree synthesis, you get the following results:
A buffer tree for each clock net. The driver of the buffer tree is a
preexisting cell or the clock source in your clock tree. There is no
buffer tree added to the small net if the driving strength of the
preexisting cell is strong enough.
The completed and legalized placement of buffers and inverters

without overlaps.
The connected power and ground for all inserted buffers and
inverters. There are no power and ground connections when your
design has more than one power line.
The same routing rules you defined before clock tree synthesis
on all new created nets. When a buffer is added to a net, a new
net is created at the buffers output side. The new net inherits all
the routing rules of the original net (the input net).
With clock tree synthesis completed, you need to propagate the
clock using
sdc "set_propagated_clock [all_clocks]"
and select the Enable Mixed Signal Clock/Signal Edges option in

the Environment page of the AstroTime Timing Setup dialog box
(atTimingSetup).

8-39
Performing Postplacement Optimization After Clock

Tree Synthesis
To perform postplacement optimization after clock tree synthesis,
1. Enter astAutoPlace or choose InPlace > AutoPlace to display
the Astro Auto Place dialog box.
2. Next to Effort, select an effort level to be spent on placement
optimization (Prototype, Low, Medium, or High). Prototype is
fastest, but the total wire length is higher than with the other
efforts. High is slowest but gives the most optimized total wire
length results. The default is Medium.
3. Next to Stage, select Post-CTS, and deselect Pre-Place,
In-Place, and Post-Place.

8-40
For the Post-CTS stage, the placer options (Congestion Driven.

Timing Driven, IO Pin Placement, and Prevent Crosstalk) cannot
be used and appear dimmed.
Note:
You can prevent crosstalk in this stage by selecting Congestion
Removal (under Post-CTS Optimization in the expanded
windowsee step 6). The maximum wire density is lowered to
reduce coupling capacitance and therefore crosstalk.
4. Under Optimization Tasks, select one or more of the following:
- Fix Setup, which fixes setup slack violations during the
optimization.
- Fix Transition, which fixes maximum transition violations during
the optimization.
- Fix Hold, which fixes hold slack violations during
postplacement optimization and postplacement optimization
after clock tree synthesis. It is recommended that you not fix
hold until after performing clock tree synthesis.
- Fix Capacitance, which fixes maximum capacitance violations
during the optimization.
5. Under Optimization Options, select from the following:
- Logic Remapping, which is used during the setup slack
optimization and attempts to reduce the number of stages in a
critical path to improve overall timing.
- Area Recovery, which reduces the area in the design by
downsizing cells and removing buffers, as long as no new
timing violations occur.
Performing Postplacement Optimization After Clock Tree Synthesis

8-41
6. Click Detail Options to use the options in the expanded window

that appears. Remember that options are active only when the
corresponding Stage option is enabled; otherwise they cannot be
used and appear dimmed.

8-42
For the Post-CTS stage, in the Post-CTS Optimization area,

select from the following:
- Congestion Removal Removes congestion (for congestion
that occurs after clock tree synthesis) during optimization.
Congestion removal can fix congestion while preserving the
relative location of cells in the placement.
7. Click OK.

After the postplacement optimization after clock tree synthesis step
and before you begin the routing flow, you can consider optimizing
the clock trees to improve both clock skew and clock insertion delay.
To further optimization your clock trees, you use the astCTO
command. For more information, see Optimizing Clock Trees on
page 9-75.

Each clock group is a path group, and Astro optimizes the most
critical path in the group.
You can use the group_path Tcl command to
Force optimization of some paths that are not the most critical
paths
Bypass some paths by specifying a weight that determines

whether or not to optimize a path

8-43
Weight is a calculation of cost for the worst path of each group:

delay cost = weight * violation
When there is no violation on the path, the cost is zero.

Cost is calculated for optimization only. Report timing of slack is
not affected by the weight.
The syntax is
group_path
-name group_name
-weight value
-from from_list
-through through_list
-to to_list
Use the group_path command to specify a higher weight for a path

with a smaller violation so it is optimized. For example,
group_path -name se -from ZS_P_reg1/CP -to Z_reg_15/D
-weight 10.0
Or use the group_path command to create path groups. For

example, to create a group of all inputs to flip-flops and a group of all
flip-flops to outputs, use
group_path -name ins -from [all_inputs]
group_path -name outs -to [all_outputs]
You can specify the group_path command in a Tcl script or in the

SDC file.

8-44
Enabling Optimization by Group Path

You can enable optimization by path group with the
group_path_opt parameter. This works the same in Tcl or
Scheme. Enter
astSetParam "ata" "group_path_opt" 1
To disable group path optimization, set this parameter to zero. This

parameter is enabled by default.
Reporting Group Paths

Use the report_path_group Tcl command to determine the
definition of a group path. The syntax is
report_path_group group_name
Optimizing Mixed Signal Nets

To optimize mixed signal nets, select the Enable Mixed Clock/Signal
Edges option in the Timing Setup dialog box. In addition, turn on the
control flag. Enter
axSetIntParam "cg" "optimize_mix_signal_net" 1
The setup, hold, transition, and capacitance violations are expected

to improve on mixed-signal nets but clock properties will be ignored.
Therefore clock timing, such as clock delay and skew, will be
affected.

8-45

This section provides information about disconnecting (and
reconnecting) scan chains, distributing spare cells, adding filler cells,
and inserting tie-high and tie-low cells.
Disconnecting Scan Chains

Connections between scan outputs and scan inputs within a scan
chain might not be optimal for routing after placement. Scan circuitry
might have timing violations, so they need to be optimized as well.
Additionally, hold times need to be fixed after the scan flip-flops are
placed and the chain connections are optimized.
It is recommended that you disconnect the scan chain prior to
performing placement and optimization with astAutoPlace, and
then stitch or reconnect the scan chain after running
astAutoPlace. Disconnecting the scan chain prevents
optimization from touching or optimizing any of the elements in the
scan chain. It is important to not disturb the disconnected elements
so that they can be retraced later.
You might want to disconnect the scan chain prior to preplacement
optimization and reconnect them after placement and before
postplacement optimization. You can do this by customizing the use
of the astAutoPlace command. In such an approach, disconnect
the scan chain and run astAutoPlace in Pre-Place stage and
In-Place stage. After placement, when the clocks are inserted,
reconnect the scan chain and return to the astAutoPlace
command and run it in Post-Place stage. This allows postplacement
optimization to optimize the chain for timing as necessary.

8-46
If you do not want postplacement optimization to work on the

reconnected chain, wait until after postplacement optimization to
reconnect the chain.
Note:
Use the dbMarkScanPortPairs and
dbDumpScanPortPairs commands when a cell has multiple
scan input and output ports.
See also Appendix B, Scan Chains.
Distributing Spare Cells

If you want to distribute spare cells, do so after global placement. You
can distribute spare cells evenly within a rectangular area.
Distributing spare cells throughout an area includes these major
steps:
1. Create the group of spare cells, using the
aprCmdCreateHierGroup command or the
aprAddGroupBySelSet command.
2. Mark the group as fixed, using the aprCmdFixCell command.
Make sure the cells in the group are outside the core area.
3. Place the standard cells, using the astAutoPlace command
(or the astPlaceDesign command). Note that the spare cells
you marked as fixed are not placed.
4. Mark the group as unfixed, using the aprCmdFixCell
command.
5. Initially place the cells in the spare group, using the
axgSpreadGroupCells command.

8-47
6. Place the spare cells at legal locations, using the axgECOPlace

command.
When you have more than one group of spare cells, repeat steps 1,
2, 4, and 5 as many times as there are groups. Steps 3 and 6 need
to be done only once.
Note:
To avoid disrupting the placement quality, spare cells should not
have any nets connected to ordinary cells.
Adding Filler Cells

You can add filler cells to your entire design or to a specific area of
the design by using the axgAddFillerCell or
axgAddFillerCellByArea commands, respectively. Both
commands allow multiheight filler cells to be placed. Usually, filler
cells are added to a design after placement is complete. Filler cells
are used by silicon vendors to fill open areas in the rows to make
sure all power nets are connected.
Note:
With 0.13 um and smaller technology, do not add filler cells
before postrouting optimization. Postrouting optimization is
needed for timing closure, and at 0.13 um and smaller, other tools
might not be able to size up cells or add buffers.
One method for improving the stability of the power supply is to add
decoupling caps as filler cells. Because these filler cells often contain
metal internally, they can cause a short or a spacing rule violation
with existing metal routes in the design. Using axgAddFillerCell
or axgAddFillerCellByArea, you can specify that filler cells with

8-48
metal be insertedAstro only inserts them and keeps them if they

do not cause DRC violations; otherwise, a regular filler cell without
metal is inserted.
The following procedure describes the axgAddFillerCell
command. The same command options are available for
axgAddFillerCellByArea.
To insert mixed-voltage threshold filler cells,
1. Enter axgAddFillerCell or choose PostPlace > Filler Cell
Add Core Fillers.
The Add Filler Cell dialog box appears.

8-49
2. Specify the filler cell lists to be loaded for use during insertion.
You can do one or more of the following:
- Enter the names of the master cells to be used in the Master
Cell Name(s) Without Metal or the Master Cell Name(s) With
Metal boxes.

8-50
Astro inserts the specified filler cells in two passes. In the first
pass, filler cells with metal are inserted, but filler cells that
cause DRC violations are removed. In the second pass, filler
cells without metal are inserted to complete the insertion
process.
- Select include all VT filler (the default) to specify that all
voltage threshold filler cells are to be loaded. Deselect this
option, and enter one or more names of the voltage threshold
filler cells in the VT Filler Name(s) box, to limit insertion to the
named cells.
For information about defining the filler cells to be used in
mixed-voltage threshold designs, see the Astro User Guide:
Advanced Topics.
3. Select other options, depending on your requirements. You can
- Specify that filler cells be placed in named voltage areas only
by entering the voltage area names in the Only in Voltage
Area(s) box.
- Select Check only to check that fillers are inserted correctly,
based on the specified requirements. This operation checks
that
The left-and-right filler cells are inserted as specified
The filler cells do not overlap with neighboring cells
The filler cells are not outside of the cell row
The filler cells power and ground pins are connected to the
specified power and ground nets
The filler cells are assigned the correct voltage area in
multivoltage designs

8-51
The correct voltage threshold filler cells are inserted between

voltage threshold cells
There are no empty spaces big enough for a filler cell
A filler cell name has the correct hierarchy and user-specified
name identifier
- Select Restore filler snapshot to specify that the filler cell
snapshot be restored during filler cell insertion. The original
filler cells are preserved whenever possible (the x-,
y-coordinates of the filler cells in the design database are
stored as they are deleted), ensuring that the coupling
characteristics are preserved.
For descriptions of all the axgAddFillerCell options, see
Inserting Tie-High, Tie-Low, and Tie-HighLow Cells

Use the connect_tie_cells Tcl command to connect cell inputs
logically connected to VDD or VSS to special tie cells, as shown in
the following figure:

8-52
This process enables the tie-off of unused cell inputs to tie cells. The
connect_tie_cells command does the following:
Automatically instantiates the minimum number of tie cells

needed
Creates the necessary logical connectivity, while honoring the

maximum fanout and maximum wire length constraints
Automatically places the new cells, while honoring all placement

constraints
You run connect_tie_cells on a fully placed design. Also, make

sure the tie cell reference cells already exist in the library and that
your design is fully connected. In particular, the ports that are to be
connected to tie cells cannot be unconnectedrun the
aprPGConnect (connect_pg_nets) command to tie off these
ports to VDD and VSS.
You must provide the following information:
The names of cell instances, reference cells, or port instances to

be connected (pattern matching is available)
The tie-high, tie-low, and tie-highlow reference cells to be used
The maximum number of cells that can be tied to a single tie cell
(this is the maximum fanout constraint), or you can use the
default constraint
The maximum allowed net wire length as a constraint, or you can

use the default

8-53
The syntax is
connect_tie_cells
-objects {<collection>}
-object_type [cell_inst |lib_cell |port_inst]
-tie_high_lib_cell string
-tie_low_lib_cell string
-tie_highlow_lib_cell string
-tie_high_port_name string
-tie_low_port_name string
-max_fanout n
-max_wirelength n
-incremental [true | false]
Use -tie_highlow_lib_cell to insert two output-pin tie cells

(TIEHL) instead of, or in tandem with, one output-pin tie cell
(TIEH and TIEL).
Use -tie_high_port_name and -tie_low_port_name to

specify the name of the ports driving logic 1 and logic 0,
respectively. For TIEHL cases, you must specify the port names
to distinguish which output pin drives high or low.
Use -max_fanout to specify the maximum number of ports that

can be driven by the single tie cell. If you do not specify this
option, the maximum fanout is 8.
Use -max_wirelength to specify the maximum Manhattan

wire length in microns from a tie cell to each driven cell port. If
you do not specify this option, the maximum wire length is 100
microns.
Use -incremental to add cells with tie-high, tie-low, and

tie-highlow pins at a later stage of the design flow, such as the
postroute stage. In this mode, the command does not disrupt
existing tie cells; it simply adds more companion tie cells near the
pins or uses existing tie cells. Additionally, use the incremental
mode to repair constraint violations for existing tie cell placement
and to validate the tie cell placement.

8-54
You can run the connect_tie_cells command in the following

modes:
TIEH and TIEL only

- Both the -tie_high_lib_cell and -tie_low_lib_cell
options must be used
- The -tie_highlow_lib_cell option must not be used
- The -tie_high_port_name and -tie_low_port_name
options are unnecessary and are disregarded
TIEHL only
- The -tie_high_lib_cell and -tie_low_lib_cell
options must not be used
- The -tie_highlow_lib_cell option must be used
- Both the -tie_high_port_name and
-tie_low_port_name options must be used
TIEHL and TIEH and/or TIEL mixed mode

- One or both of the -tie_high_lib_cell and
-tie_low_lib_cell options must be used
- The -tie_highlow_lib_cell option must be used
- Both the -tie_high_port_name and
-tie_low_port_name options must be used
In this case, if there are both tie-high and tie-low ports in the
same vicinity, the TIEHL cell is used. Otherwise, TIEH and TIEL
cells are inserted as needed to further reduce area.

8-55
By default, the connect_tie_cells command automatically

inserts the separator ! to the output signal net of the tie cell after
the tie is inserted. For example, BLOCKA/MYTIEH!U1netA.
Use the nameSeparator parameter to change the separator ! to
another character. The syntax is
axSetIntParam "place" "nameSeparator" #n
where #n is the decimal number that can be defined by typing "man

ascii" in UNIX to get the ASCII table.
Decimal - Character
SunOS 5.8 Last change: 11 Aug 1994 1
Standards, Environments, and Macros ascii(5)
0 NUL 1 SOH 2 STX 3 ETX 4 EOT 5 ENQ 6 ACK 7 BEL
8 BS 9 HT 10 NL 11 VT 12 NP 13 CR 14 SO 15 SI
16 DLE 17 DC1 18 DC2 19 DC3 20 DC4 21 NAK 22 SYN 23 ETB
24 CAN 25 EM 26 SUB 27 ESC 28 FS 29 GS 30 RS 31 US
32 SP 33 ! 34 " 35 # 36 $ 37 % 38 & 39 '
40 ( 41 ) 42 * 43 + 44 , 45 - 46 . 47 /
48 0 49 1 50 2 51 3 52 4 53 5 54 6 55 7
56 8 57 9 58 : 59 ; 60 < 61 = 62 > 63 ?
64 @ 65 A 66 B 67 C 68 D 69 E 70 F 71 G
72 H 73 I 74 J 75 K 76 L 77 M 78 N 79 O
80 P 81 Q 82 R 83 S 84 T 85 U 86 V 87 W
88 X 89 Y 90 Z 91 [ 92 \ 93 ] 94 ^ 95 _
96 ` 97 a 98 b 99 c 100 d 101 e 102 f 103 g
104 h 105 i 106 j 107 k 108 l 109 m 110 n 111 o
112 p 113 q 114 r 115 s 116 t 117 u 118 v 119 w
120 x 121 y 122 z 123 { 124 | 125 } 126 ~ 127 DEL
For example, if you enter

axSetIntParam "place" "nameSeparator" 95

8-56
before running the connect_tie_cell command, then the signal

net connected to the output of the tie cell will be BLOCKA/
MYTIEH_U1netA.
Examples
In the following example, all input ports of cells "ANY_CELL_*/*" that
are tied off to power or ground are connected to new tie-high and
tie-low cells.
connect_tie_cells -objects [get_cells "ANY_CELL_*/*"]
-obj_type cell_inst -tie_high_lib_cell TIEH
-tie_low_lib_cell TIEL
In the following example, all input ports named A of cells

"ANY_CELL_*/*" that are tied off to power or ground are connected
to new or existing tie-high and tie-low cells that are at most 64
microns of Manhattan distance away.
connect_tie_cells -objects {"ANY_CELL_*/*/A"}
-obj_type port_inst -tie_high_lib_cell TIEH
-tie_low_lib_cell TIEL -max_wirelength 64
-incremental true
In the following example, all input ports of cells "ANY_CELL_*/*" that

are tied off to power or ground will be connected to new tie-highlow
cells. Ports that are tied off to power will be connected to port OUT1
on cell TIEHL. Ports that are connected to ground will be connected
to port OUT0 on cell TIEHL.
connect_tie_cells -objects [get_cells "ANY_CELL_*/*"]
-obj_type cell_inst -tie_highlow_lib_cell TIEHL
-tie_high_port_name OUT1 -tie_low_port_name OUT0

8-57
Using Alternative Placement and Optimization

Commands
Individual placement commands fall under three different menu
headingsPrePlace, InPlace, and PostPlaceaccording to the
stage in the design in which they should be used. Individual
placement optimization commands can be used when the
astAutoPlace command flow does not give satisfactory results.
Use PrePlace menu commands to run preplacement

optimization, create placement blockages and other constraints,
and trace and delete scan chains.
Use InPlace menu commands to select placement common

options, place cells, manage placements, and display placement
maps.
Use PostPlace menu commands to run postplacement

optimizations, run scan chain optimization, and add filler cells.
Before you perform placement, use the astPlaceOptions

command to select the placement common options for your design.
For more information, see Setting Placement Common Options on
page 8-9.
Performing Preplacement Optimization

You can use the astPrePS command to optimize the netlist prior to
performing placement. This command generates a fast placement,
from which it gets wiring information, before optimizing the netlist.
Because astPrePS creates a valid placement, make sure you
specify your placement common options before running the
command.

8-58
The astPrePS command performs these processes:
Quick placement
High-fanout collapse
High-fanout net synthesis
Gate sizing
Cell moving
Buffer and inverter bypassing
Buffer and inverter insertion
Gate duplication
Net splitting
Area recovery
Remapping
To perform preplacement optimization,

1. Enter astPrePS or choose PrePlace > Pre-Placement
Optimization.
The Pre-Placement Optimization dialog box appears.

8-59

Under Design Cleanup, the options are
- High-Fanout Collapse
Collapses high-fanout nets inserted by synthesis.
Generally, when synthesis inserts buffers for fanouts greater
than 10, it can interfere with Astro optimizations and increase
congestion. Therefore, rebuffer these in Astro, based on the
actual physical placement. Setting a lower value does not
improve optimization significantly but can increase the runtime,
because Astro must rebuffer these nets. Setting the value to 1
removes all buffers from the design.
See also High-Fanout Collapse on page 8-63.

8-60
- Cell Downsize
Enables downsizing during preplacement optimization. The
box to the right specifies how far it can downsize. For example,
a value of 1 allows downsizing by only one drive strength; a
value of 0 downsizes all the way. Downsizing all cells could
create a huge impact on placement and, because Astro might
not be able to upsize all the cells in the design, use this only
when absolutely necessary.
- Area Recovery
Eliminates buffers and downsizes cells. By default, the
utilization at which this occurs is 50 percent or higher, as
specified in the AstroTime Timing Setup dialog box. Use the
AstroTime Timing Setup dialog box to lower this threshold
when you want more recovery to occur.
Use the Remove Buffers option to remove buffer that do not
affect the setup slack.
Under Quick Placement, the option is
- Enforce Full Place
Forces the tool to complete a full quick placement before trying
to fix high-fanout nets. When unselected, it simply runs the
ECO placement. Assuming you already have a valid
placement in your design, you do not need to rerun a full
placement; an ECO placement suffices. Previously, the
strategy was to do more massive changes, such as a
high-fanout nets optimization, before detail placement began.
When the location constraint options in the Place Common
Options dialog box need to be changed from the defaults, do
so prior to running preplacement optimization. For example, if
you have preroutes on metal 1 that are of the strap type and

8-61
cover most of the design, preplacement optimization fails at

placement, because the default placement option is not to
place cells under metal 1 straps.
Note:
Maximum transition and maximum capacitance are no
longer optimized by preplacement optimization or
in-placement optimization. It is intended that the first-time
transition and capacitance constraints are to be fixed during
postplacement phase 1 optimization.
Under Optimization, the options are
- High-Fanout Synthesis
Does a quick buffering of high-fanout nets. By default, the
threshold is set to 40, as specified in the AstroTime Timing
Setup dialog box (see Optimization Page on page 6-31).
- Ideal Optimization
Attempts to optimize the design with zero interconnects,
resistance, and capacitance. On large designs, it might be
better to turn this option off to save runtime.
- Logic-Remapping
Does logic optimization during preplacement optimization. For
more information, see Remapping on page 8-64.
3. Click OK.
Astro does a quick placement and then performs the selected
options, such as high-fanout net optimization with area recovery,
ideal optimization, and logic remapping.

8-62
High-Fanout Collapse
High-fanout nets are addressed automatically while the astPrePS
command is running. There is no need to set the high-fanout net
transition delay. Use the ataSetNetCapTransAndDelayTime
command to force the astPrePS command to exclude a specific
net. For nets such as reset, use the stand-alone pdsHFNOptNet
command. To reduce congestion, run high-fanout collapse before
preplacement optimization to clean up the synthesis netlist. You can
select High Fanout Collapse and enter 10 (the default) in its text box
in the Pre-Placement Optimization dialog box.
Design FeasibilityReporting Ideal Slack

During preplacement optimization, Astro first identifies critical paths
without interconnect RC. This result is called ideal slack. The ideal
slack is an indicator that this is the upper bound for timing that you
can get in the physical domain. Based on ideal slack information,
Astro performs optimization.
The ideal slack should be positive after preplacement optimization.
You can locate this number in the log file after running the astPrePS
command. You can also obtain ideal slack by setting the timing
engine to ignore interconnect and then running the timer. The slack
should be positive.
If the ideal slack from preplacement optimization shows negative
values, it is either extremely difficult or impossible to meet the timing.
This information can be given back to designers early in the flow for
redesigning, resynthesizing, or verifying the constraints.
When the number is far into the negative range, you examine the
critical path with zero interconnect timing. The only acceptable
source for a large negative number is when the data and clock are
mixed. Because the clock tree is not yet built, it is possible to have a
8-63
high-fanout net in the clock after preplacement optimization. When

the data and clock are mixed, this high fanout can cause a large pin
capacitance that leads to large transitions and delays. After the tree
is built, this goes away. If data-and-clock mixing is the cause of the
high negative slack, turn off mixed edges during timing analysis and
redo zero interconnect timing after preplacement optimization.
Note:
You can use the astCheckDesign command to obtain the ideal
slackthis command provides detailed information about the
design.
Astro Resynthesis
Astro resynthesis focuses on physical optimization. Traditional
synthesis has netlist elaboration, which is typically netlist translation.
Netlist optimization, with accurate and accessible physical
information, is the key to achieving fast timing closure. Astro
synthesis technology provides various optimization approaches that
are applied to different scales at each place and route stage.
Unlike traditional synthesis tools with design-size limitations, Astro
synthesis focuses on optimization by allocating reasonable clusters
or working regions. It does not have an inherent design-size
limitation. As long as the design can be accepted by the Astro
system, depending on 32-bit or 64-bit architecture, the Astro
synthesis technology can work on it.
Remapping
Remapping includes the following algorithms and techniques:
Uses quick Boolean matching to explore the solution space
Uses graph-based covering with area reduction

8-64
Does block-level cell sizing and moving, simultaneously moving

and sizing cell instances in a block
Optimizes the worst setup slack and the total negative setup
slack; does not fix hold time
Buffering Nonclock Nets

The pdsHFNOptimization command, which is built into
high-fanout net fixing in preplacement optimization, can be used to
buffer nonclock nets.
However, you can also run pdsHFNOptimization as a
stand-alone process after a placement exists. You might find it more
convenient to buffer large high-fanout nets, such as resets or
enables, using this command after placement is finished instead of
during preplacement optimization. Make sure you use the
ataSetNetCapTransAndDelayTime command to specify a
realistic capacitance, delay, and transition for the net and to prevent
high-fanout optimization during preplacement optimization.
Note:
You can write the ataSetNetCapTransAndDelayTime
command values by using the ataWriteTC command or by
choosing design constraints that are not from Synopsys.
To find all high-fanout nets in a design, use the astDumpHFN
astDumpHFN n
This command displays nets with n or more pins on them.

See also Performing Clock Tree Synthesis After Placement on
page 9-62.

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Performing Placement and In-Placement Optimization

Use the astPlaceDesign command to place standard cells in the
design and to perform in-placement optimization.
The placement phase of the design flow places the cells in the core
area. You can weight cell placement to optimize various factors of a
design by choosing the primary placement goal. When using
astPlaceDesign, do this by choosing Congestion or Timing
optimization modes in the AstroPlace Options dialog box
(astPlaceOptions). The mode you set is shown in the AstroPlace
Design dialog box (next to Mode). For descriptions of the modes
(Congestion and Timing), see Setting Placement Common Options
on page 8-9.
While astPlaceDesign is running, placement might stop with the
following warning and error messages:
WARNING: can't restore area partition (SPLCongAP) from DB's
attached file (possible data lost: congestion map, ...)
ERROR: placement congestion map cannot be found/restored
In that case you need to update the congestion map with the
axgUpdateCongMap command and restart the astPlaceDesign
command.
After automatic placement, Astro displays a congestion map that
contains an estimate of the routing congestion in the design. The
astPlaceDesign command also performs cell sizing, cell moving,
cell bypassing, buffer and inverter insertion, gate duplication, and net
splitting optimization techniques.

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To perform placement and in-placement optimization,

1. Enter astPlaceDesign or choose InPlace > Design
Placement.
The AstroPlace Design dialog box appears.

For descriptions of the astPlaceDesign command options,
see Physical Implementation Online Help.
Running Search and Refine

After you run automatic placement, you can use the
astSearchRefine command to change the placement of cells
within congested areas. You can also use the astPlaceArea
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command to move standard cells in a congested area to a

less-congested area. For more information about these commands,
see Refining Placement on page 8-69.
Optimizing High-Fanout Nets

By default, high-fanout net optimization (that is, collapse and
resynthesis) now occurs during the in-placement optimization stage
of the flow instead of during postplacement phase 1 optimization.
However, if you are not performing in-placement optimization,
perform high-fanout net optimization during postplacement
optimization phase 1.
Use the astFanoutSetup command to perform timing-driven
high-fanout net optimization that can create a balanced tree, while
attempting to minimize the insertion delay, using buffers and
inverters.
To perform timing-driven high-fanout optimization,
1. Enter astFanoutSetup.
The Fanout Optimization dialog box appears.

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- Next to Fanout Limit, enter the maximum fanout constraint.
To optimize for the transition time, specify a high number, such
as 200. To optimize for the number of fanouts, specify a lower
number, such as 40 (the default).
- Next to From File, enter the name of the file from which the net
names are read.
- Select Collapse HFN Net to specify that buffer and inverter
collapse can precede synthesis to regenerate fanout trees.
- Select Timing Driven to instruct Astro to generate a balanced
tree using the number of fanout pins as a constraint.
- Deselect Disable Net Splitting to do source sizing and source
splitting to minimize the worst setup slack on driving port
instances.
3. Click OK.
Refining Placement
After you run automatic placement, you can improve placement by
using the astSearchRefine and astPlaceArea commands, as
described in the next sections.
Performing Search and Refine

Use the astSearchRefine command to improve cell placement by
evaluating the current placement and then changing the placement
within congested areas. The astSearchRefine command never
makes your placement worse, because it reverts to your initial

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placement when it cannot improve the placement. You can use the
astAddPlaceSRConst command to specify areas in which Astro
runs the astSearchRefine command.
To run search and refine placement,
1. Enter astSearchRefine or choose InPlace > AstroPlace
Search and Refine.
The AstroPlace Search & Refine dialog box appears.

For descriptions of the astSearchRefine command options,

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Moving Standard Cells in a Specific Area

Use the astPlaceArea command to move standard cells in a
specified area if the design is still not routable after you run the
astSearchRefine command. The area you specify should include
congested and less-congested areas to give Astro the space needed
to move cells. You must have an existing placement to run area
placement.
Important:
When the area is severely congested, try using different
placement options for the astPlaceOptions command or
apply density constraints to the placement area using the
aprSetDensity command.

The stand-alone postplacement optimization flow includes four main
steps:
1. Netlist optimization with ideal clocks
2. Clock tree synthesis
3. Optimization with propagated clocks
4. Clock tree optimization
The flow also details how to use design rule fixing, hold slack
optimization, and power optimization in Astro.
Postplacement Optimization Design Flow

During placement, your design is optimized for global costs such as
total weighted wire lengths (timing driven) and congestion. At the
end of the placement, the location of all cells in the design is legal
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and there is no cell overlapping. In combination with the

congestion-based parasitics, the estimation of design timing
becomes more accurate. If you are satisfied with the quality of the
placement and the estimated congestion, you can perform a more
specific timing optimization of the netlist and the layout.
Although global timing cost is already considered during placement
as a timing-driven weight, it does not correspond to any direct timing
measure such as the maximum clock frequency, the worst negative
setup slack, or the total negative setup slack. To check the feasibility
of the design timing constraints with ideal clocks, run a full
placement-based optimization targeted on the total negative setup
slack, the number of setup violations, and the design rulessuch as
the maximum fanout, maximum transition time, and the maximum
capacitance.
Use postplacement optimization phase 1 to achieve these targets.
During this step, you achieve the most significant change to the
placed design (in terms of the number of inserted buffers and
inverters, and moved cells). You employ topology-based optimization
methodology, high fanout net optimization algorithms, and different
cell moving techniquesas well as fast cell sizingto achieve fast
layout optimization results. For complicated floorplans with narrow
channels and large placement blockages, it might not be easy to
predict the routing patterns. As a result, the accuracy of the timing
prediction might be low and the optimization results not optimal. In
this situation, postplacement optimization phase 1 provides an
option to use the global routing-driven synthesis, which is exclusively
based on global routing topology. For details about topology-based
optimization methodology used in the postplacement and
postrouting optimization flow, see Topology-Based Methodology on
page 8-74.

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Postplacement optimization phase 1 also provides an option to

prevent crosstalk (for information, see Preventing Crosstalk on
page 15-6). In addition, the maximum wire length constraint can be
used to minimize the crosstalk effect by preventing very long wires.
The next step in the recommended design flow is clock tree
synthesis. Your design might require different clock tree synthesis
strategies. The most important are global skew, local skew, and
useful skew strategies. For detailed descriptions of the Astro clock
tree synthesis flows and how they can be used in the postplacement
optimization flow, see Performing Clock Tree Synthesis After
Placement on page 9-62. If you use a slack-driven clock tree
synthesis, such as useful skew, postplacement optimization phase 1
is required.
Using the propagated clock option in atTimingSetup further
refines the accuracy of the timing analysis. The second phase of
postplacement optimization phase 2 is required to improve the timing
results of your design with propagated clocks. This optimization
phase uses a different set of optimization techniques than
postplacement optimization phase 1. Detailed optimization
algorithms, which include logic remapping, are used for setup slack
optimization, design rule fixing, and area recovery. These algorithms
consider a wider search space and are targeted for optimal
solutions; they take the opposite approach from postplacement
optimization phase 1 techniques that are targeted on fast results and
larger improvement. The primary reason for setup slack optimization
is to improve the worst negative slack.
Timing analysis with propagated clocks provides the necessary
accuracy for fixing hold slack violations. Postplacement optimization
phase 2 can optimize the design for both setup and hold fixes. The
use of topology-based techniques for hold fixing minimizes the
impact of the layout changes on routing congestion.
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If the hold violations in your design are considerable, run hold fixing
during postplacement optimization phase 2 and fix any remaining
violations in the postrouting stage. Postrouting optimization can
make only small changes and might not be capable of fixing
numerous hold violations.
Layout changes during postplacement optimization phase 2 might
also disturb the clock structure. Therefore, clock tree optimization is
required at the end of postplacement optimization. For detailed
information about clock tree optimization, see Optimizing Clock
Trees on page 9-75.
Topology-Based Methodology
Topology-based optimization, which is used throughout the Astro
postplacement optimization flow, greatly assists in timing
optimization and has powerful techniques that allow you to close
timing where other approaches cannot.
During routing, the optimization uses the actual topology of the
routing to place new cells along the route while honoring all
placement and routing blockages, thus minimizing congestion and
improving timing. Before global or detail routing, however, the tool
must be capable of handling placement blockages, routing
blockages, and future congested channels while accurately placing
cells in desired locations. Topology-based optimization and its
interaction with placement and routing constitute the topology-based
methodology.

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The topology-based methodology interacts with the virtual router,

which provides the flexibility to explore various routing topologies.
The following three basic routing modes are explored during
optimization:
1. Minimum wire length routing
2. Routing with placement blockage avoidance
3. Hierarchical routing
As a result, topology-based optimization attempts to find a solution
that satisfies all the design rule constraints simultaneously with
placement and routing constraints and hierarchy preservation
restrictions. It makes possible the autodebugging mechanism during
topology-based optimization, which helps the optimizer adjust in
accordance with the problem encountered. For more information,
see Design Rule Fixing in Astro on page 8-87.
The technology of routing with placement blockage avoidance is also
inherited in the global router. The global router is controlled by the
blocked capacitance limit that is generated by the optimizer. For
more information, see Specifying a No Buffer Zone on page 10-29.
Unlike virtual routing, global routing does not allow modification
routing topology to satisfy hierarchy preservation requirements.
Therefore, you might see unfixed violations because of hierarchy
preservation that can easily be fixed by altering the routing topology.
Postrouting optimization flow relies on the accuracy of parasitics
prediction before and after the routing repair. Topology-based
algorithms provide excellent accuracy for incremental extraction
when the existing wires are reused in the routing repair flow. To
achieve this, a special forward-annotation exchange file is used,
called ECO_route.rpt. This file contains information about broken

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nets and the new nets generated from them. This file is generated
during optimization and read in during the reconnect procedure of
the routing repair flow.
If you want to maintain predictability of the results during the routing
repair flow, the number of broken nets should not be too large. A
placement engine internally controls the number of broken nets and
interrupts the optimization when a certain threshold is reached. If this
happens, you see the OV-INTERRUPT message in your log file. The
routing repair is called after that and the optimization continues.
The following situation illustrates topology-based methodology:
Assume that a transition violation occurred that requires the buffers
on the right and left to be inserted as shown in Figure 8-4. Because
the routing is not blocked by using the dotted line path, the routing
estimate can route over the block. If you are trying to fix the transition
violation, however, you must insert a buffer, but when it is inserted
under the estimated routing, it is considered illegal. Topology-based
fixing considers both the routing and placement blockages to
determine that the optimal solution is to insert one buffer on the left
and one in the gap on the right. If you do not use topology-based
optimization, the solution is not obvious.

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Figure 8-4
Transition Violation Example
Placement blockage
Routing blockage
Consider a different situation:

As shown in Figure 8-5, virtual routing puts all signal routes through
the channel, but after global routing some signals are pushed out.
Topology-based fixing can be run at the placement stage, based on
quick global routing, to correctly predict this situation and place the
buffer in the optimum location. Now, when further postplacement
optimizations are run, virtual routing goes around the channel
blockage because the buffer has already been placed outside the
channel.

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Figure 8-5
Routing Around Channel Blockage

Detoured
route
Macro
Congested routing channel

Phase 1 Before Clock Tree Synthesis
When you use postplacement optimization phase 1 (astPostPS1),
you take advantage of topology-based optimization methodology, as
discussed in the previous section, prior to global routing or detail
routing. This methodology allows you to optimize designs with
significant routing and placement obstructions. Run postplacement
optimization phase 1 either before clock tree synthesis or before the
postplacement optimization phase 2.
To run postplacement optimization phase 1,
1. Enter astPostPS1 or choose PostPlace > Optimization
Post-Place Optimization Phase 1.
The Post-Placement Optimization Phase 1 dialog box appears.

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2. You can select the following options:

- Optimization Effort
LOW (default) Is the gross total negative setup slack and the
faster, worst negative setup slack optimization. The total
negative setup slack optimization is run in two stages: First,
using the topology-based techniques and, second, using the
cell moving technique. The worst negative setup slack
optimization is called at the end of postplacement optimization
phase 1.
MEDIUM Adds an extra loop of total negative setup slack
optimization and the refinement of the worst negative setup
slack optimization with logic restructuring.
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Medium effort takes nearly two times as long as the Low effort
and usually provides a noticeably better total negative setup
slack and a worst negative setup slack at the end.
HIGH Adds one more loop of total negative setup slack
optimization and worst negative setup slack optimization,
using logic restructuring and detail optimization algorithms.
The runtime in High effort significantly increases as a tradeoff
for extra stress on the worst negative setup slack optimization.
- Re-do HFN Synthesis
Because placement ignores nets with fanouts more than 32,
you might end up with a bad placement for nets that contribute
to increased wire length and congestion. This might happen
when you perform timing-driven or congestion-driven
placement without in-placement optimization and your starting
netlist has synthesized high-fanout nets (HFN). In this case,
resynthesize all such nets. The Re-do HFN Synthesis option
performs high-fanout net collapsing and then rebuilds the
high-fanout nets based on final placement clustering. This
helps relieve congestion in the design.
When an in-placement optimization flow is run, this step has
already been performed and must not be rerun in
postplacement optimization phase 1.
- Use Global Routing
Sometimes the layout floorplan is so complicated that the
estimation of the layout parasitics as well as the prediction of
the routing topology-based optimization on virtual routing
algorithms is often inaccurate. As a result, they cannot be used
for timing estimation and topology-based optimization. An
example of such a layout is a design with narrow routing

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channels. To solve this problem, optimization driven by the real

global routing, rather than the virtual routing, estimation is
recommended.
If you select the Use Global Routing option,
- Quick global routing is performed
- Topology-based optimization with global routing extraction is
executed, and
- Global routing is deleted when the optimization is finished.
When optimizing hierarchical nets, global routing topology
might create restrictions for topology-based algorithms that
result in unfixed timing violations. Therefore, it might be useful
to run postplacement optimization phase 1 again without this
option selected to clean up those remaining violations.
- Setup Fixing
Performs total negative setup slack optimization, according to
the effort level you select under Optimization Effort.
- Hold Fixing
Optimizes hold slack in a way that does not affect the number
of setup violations or the total negative setup slack. For more
information about setting the low effort for hold fixing, see
Hold Slack Optimization in Astro on page 8-96. Violations
that cannot be fixed this way remain.
This feature is useful in fixing large hold slack violations that
are not dependent on clock tree synthesis. To avoid fixing small
violations, set the target hold slack on the optimization
environment page to a desired negative slack number.

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Use the Preserve option to control the effort. Select WNS for
medium effort and TNS for low effort.
- Design Rule Fixing
Fix Max Length On some designs, it helps to place buffers at
specified lengths before doing detailed optimization. Typically,
these are large designs or designs with several macro
blockages. The buffers serve as a guide.
Fix Tran/Cap Fixes maximum transition and capacitance
violations.
Activating the Detailed Message Report option in the
Optimization page of the AstroTime Timing Setup dialog box
(atTimingSetup command) might help debug unfixed
violations. For example, the following message for a given net
Cannot Insert Buffers #Times : Placement
means that the algorithm cannot find a suitable legal location

along the topology. You might need to review the placement
blockages added to the layout to determine how they block
given nets and modify them when necessary or review the
maximum transition time and capacitance constraints. After
that, use the astDesignRules command to fix the remaining
violations, as described in Design Rule Fixing in Astro on
page 8-87.
Prevent Xtalk Uses cell sizing and buffer insertion, based on
the routing topology, to prevent potential crosstalk problems.
3. Click OK.

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Clock Tree Synthesis

The next step in the recommended design flow is clock tree
synthesis. A general method for performing clock tree synthesis,
which you can use for this step, is described earlier in this chapter in
Performing Clock Tree Synthesis on page 8-36. If your design
requires a different clock tree strategy, see Chapter 9, Clock Tree
Synthesis and Clock Tree Optimizations for a complete description
of the clock tree synthesis optimization flows.
Running Postplacement Optimization Phase 2

Use postplacement optimization phase 2 (astPostPS) to improve
the timing results of your design. During postplacement optimization
phase 2, your optimization targets are
Setup slack violations
Hold slack violations
Maximum transition violations
Maximum capacitance violations
Area recovery
The astPostPS command uses the following techniques to

optimize the netlist and the layout:
Buffer insertion
Cell sizing
Logic restructuring
Net splitting
Gate duplication

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Inverter insertion
Cell moving
You can specify that astPostPS not add any new instances during
optimization (gate sizing and gate moving only are allowed). To
enable this behavior, enter
axSetIntParam "pds" "no_new_instance" 1
You can also use the no_new_instance parameter with the

astTranFix and astCapFix commands.
Make sure you carefully analyze your design after running
postplacement optimization phase 2 to determine whether timing
errors remain. Consider factors such as data-and-clock mixing and
case analysis so that all parts of the design are correctly optimized.
The timing report can provide clues about why certain elements in
the design cannot be optimized. Sometimes, a second iteration of
postplacement optimization can improve the design results further.
When optimizing a design at the postplacement stage of the design
flow, you can use the following methodology:
1. Run astPostPS with data-and-clock mixing set off and with the
design in the normal operating mode.
2. Run astPostPS again with the data-and-clock mixing option on
(when clock trees have been inserted).
Note:
Data-and-clock mixing might have been set previously.
Splitting it into two steps can help distinguish the changing
effects.

8-84
3. Set the other circuit mode conditions (if any), and repeat the
optimization several times.
In this way, the design is best optimized for the operating condition
but is also optimized for other operating conditions. The same
procedure can be repeated during postrouting optimization.
To begin postplacement optimization phase 2,
1. Enter astPostPS or choose PostPlace > Optimization
Post-Place Optimization.
The Post-Placement Optimization dialog box appears.

For descriptions of the astPostPS command options, see
3. Click OK.
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Critical Region Optimization. Postplacement optimization phase 2

runs a step that attempts to optimize all paths after it has minimized
the worst slack. This is called critical region optimization and is done
automatically during postplacement optimization. Critical region
optimization can be run stand-alone with the pdsCROptimization
command.
Additional Settings and Commands for Optimization. The
following settings are provided for referencein some cases these
arguments can improve timing. You must set the axSetIntParam
values prior to running the astPostPS command. Run the pds
commands from the command line. Complete the standard flow first,
evaluate the results, and then go back to the cell you saved after
postplacement optimization and try some of the following strategies:
To allow flip-flop moving (required before clock tree synthesis),

use
(axSetIntParam "pds" "large_mv_in_ppo" 0)
;;
range [0,1], default=0;
;; switch on/off large moving instance during optimization
To move cells, use the pdsMoveCell command iteratively,

followed by the astPostPS command. The command has three
effort levels that can be set. Use
(axSetIntParam: "pds" "effort" 2)
0-low, 1-medium, 2-high

Depending on the selected effort, the size of the critical region is
adjusted.
The pdsMoveIOPaths command minimizes the distance from

the I/O to the cell connected to the I/O.

8-86
To split three-state nets, use the pdsSplit3StateNet

command.
The pdsSplit3StateNet command splits three-state nets
using logical transformation. It should be used after a complete
placement is generated. The pdsSplit3StateNet command
cannot make a three-state net a non-three-state net (this would
be logically incorrect). The goal of this command is to optimize
the net by reducing the connectivity.
Improving Timing After Postplacement Optimization. After

running postplacement optimization, when you want additional
timing improvement, use
The pdsMoveCell command to move chunks of cells
The pdsCROptimization command to optimize all paths after

minimizing the worst slack when the total negative is more critical
The pdsSplit3StateNet command to fix transition violations

on three-state cells
After running each of these fixes, repeat postplacement optimization

phase 2 to further improve your design timing.
Design Rule Fixing in Astro

Astro provides a set of point commands to fix different design rules.
Design rules are fixed by the following constraints:
High-fanout net optimization
Maximum transition time and capacitance
Maximum wire length

8-87
High-Fanout Net Optimization. There are several commands in

Astro that optimize high-fanout nets. Each has its own advantages
and domains of use.
To fix the maximum fanout violations on a net,
1. Enter astFanoutSetup.
The Fanout Optimization dialog box appears.

For descriptions of the astFanoutSetup command options,
3. Click OK.
This command generates a buffer or inverter tree to minimize the
driver setup slack and the insertion delay for the tree. It can create
an unbalanced tree to compensate for the differences in the setup
slack on sink ports and use net splitting techniques for a driver when
it is a buffer or inverter. When the nontiming-driven mode is selected,
the buffer or inverter tree is always balanced by the number of levels
and by the cluster capacitances with a maximum number of sinks
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less than the maximum fanout constraint. To satisfy the hierarchy

preservation constraints, the tool uses hierarchical clustering and
employs a hierarchical approach for buffer or inverter tree
construction. Simultaneously, with maximum fanout, the cluster size
satisfies the maximum capacitance and transition time constraints.
Though this algorithm can construct inverter trees, it requires the
presence of at least one buffer in the library. The buffer is used to do
hierarchical clustering.
This algorithm is used during in-placement optimization to
resynthesize high-fanout nets and during postplacement
optimization phase 1 to perform high-fanout optimization.
Library fanout constraints and fanout load are supported only by the
topology-based fanout synthesis that is integrated with the maximum
transition time, capacitance, and length algorithms. It can be invoked
by using the astDesignRules command in any combination of the
constraints.
To create a buffer tree,
1. Enter astDesignRules.
The Design Rules dialog box appears.

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2. Select the options or keep defaults. Select the types of constraint

violations to be fixed and enter their respective constraint value.
You can also choose to report length and fanout violations.
For descriptions of the astDesignRules command options,
3. Click OK.

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The astDesignRules command creates a buffer tree that satisfies

all the selected constraints by using routing topology. The tree might
not be balanced and the insertion delay is considered in the tradeoff
with the loss of area. Only the buffer tree can be constructed. As with
any topology-based algorithm, it can be applied before routing or
after global or detail routing.
To break the high-fanout net into nets with a given number of ports,
you can use the pdsHFNOptimization command. It creates a
buffer tree with a specified number of ports on every net in the tree,
but the root net might have fewer ports. The tree is not balanced and
not optimized for insertion delay. Only buffers can be used in this
algorithm. This algorithm is used during preplacement optimization
for initial high-fanout synthesis.
Maximum Transition Time and Capacitance. Topology-based
optimization algorithms that are invoked by the astDesignRules
command or the astTopoTransCap command perform the
maximum transition time and capacitance fixing simultaneously with
the maximum fanout load and maximum wire length constraints in a
single traversal of all violated nets in the design. When several
design rule violations occur on the net, the tightest violation drives
the net optimization, so you do not need to run the optimization
multiple times to fix different design rules.
To fix the maximum transition time, maximum capacitance, and
maximum length violations,
1. Enter astTopoTransCap.
The TopoDesignRules dialog box appears.

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For descriptions of the astTopoTransCap command options,
3. Click OK.
The algorithm has a built-in debugging technology to help identify the
reasons the violations cannot be fixed. To activate this option, select
the Detailed Message Report option on the Optimization Tab in the
atTimingSetup command.
Debug message:
Cannot Insert Buffers #Times : Placement
This message indicates the optimization is limited by the placement.

It might be caused by a large placement blockage or a large
nonplaced area, or the placement overlap removal engine that
cannot resolve the cell overlapping under the maximum cell moved
and the maximum displacement restrictions. In the latter case, the
message
Rejected by OV

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also appears.
Another debug message:
Cannot Insert Buffers #Times: Hierarchy
indicates the hierarchy preservation prevents buffer insertion on the

routing topology. If it happened only during the postrouting
optimization, the buffer insertion out of the routing topology is
required. To achieve this, select Virtual_RC (next to LPE Mode:) in
the Parasitics page of the AstroTime Timing Setup dialog box
(atTimingSetup) and optimize the selected nets from the file.
You can also apply detail optimization techniques to fix the maximum
transition time and maximum capacitance violations by using the
astTransFix and astCapFix commands.
The topology-based optimization algorithm is applied during
postplacement optimization phase 1 and to all postrouting
optimization stages. The detail optimization algorithm is applied
during postplacement optimization phase 2.
Maximum Wire Length. To perform maximum wire length
optimization, you can use either the astDesignRules command,
the astTopoTransCap command, or the astLenBI command.
Use the astLenBI command to perform length-based buffer
insertion during optimizations. This command automatically selects
buffers when buffer information is not specified and inserts repeaters
when length and buffer information is not specified.

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To perform length-based buffer insertion during optimizations,

1. Enter astLenBI.
The Length Based Buffer Insertion dialog box appears.

- Enter the maximum wire length for a net in the Max Length text
box.
During optimization, buffers are added when the total driving
length of the net is less than this constraint. By selecting
Farthest Len Optimization, you can specify that only the length
from the driver to the farthest pin be considered.

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- Enter the buffer to be used during optimization in the Buffer

Name text box.
- Under Nets to be processed, select All Nets if you want to
process all nets in the design or select Net File Name (and
enter the name of the file) if you want to process nets listed in
a file.
Select Optimize coupled network to specify length-based
buffer insertion for nets that are running in parallel and close
together. Enabling this option helps to fix crosstalk violations.
The buffers are inserted so that they are positioned on
adjacent nets in a staggered formation, as shown here (B
represents a buffer).
N1 -------B--------B-------B-------B-------B-------B--------B------N2 ---B-------B-------B--------B-------B-------B-------B--------B--N3 -------B--------B-------B-------B-------B-------B--------B-------
- Select Do Global Routing to specify that global routing be run

before the astLenBI process (the global routing data is
deleted after running astLenBI). You gain the following
advantages:
The global router considers placement blockages more
accurately than astLenBI
The global router considers congestion, enabling astLenBI to
be more accurate
The global router provides better handling of complex, multiple
placement blockages
- Enter the name of the violation report file to be generated in the
Violation Report File text box. If you only want to report
violations (and not fix them), select Violation Report Only.

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- Select Farthest Len Optimization to specify length-based

buffer insertion in which buffers are added only when the
distance from the driver to the farthest pin on the net is less
than the Max Length value. Fewer buffers are inserted than
when you use regular length-based buffering, in which the total
length of the net is considered.
3. Click OK.
You might set the maximum length and a buffer, or only the maximum
length to do the optimization. If the maximum length and the buffer
are not specified, the repeater insertion is performed instead. The
target of the repeater insertion algorithm is to minimize the stage
delay that includes the delay of the driver and the interconnect delay
to the farthest pin on the net. Both buffers and inverters are used to
achieve the best results.
Maximum wire length optimization is considered as a special utility
performed for a different reason. It might be for crosstalk prevention
and optimization for long wires. Also, adding buffers along the routing
topology guides other optimization algorithms around the placement
and routing obstacles. It is used in the postplacement optimization
phase 1 and during postrouting optimization steps. Also, the
algorithm is invoked during top-level clock tree synthesis.
Hold Slack Optimization in Astro

Use the astTopoHold command to perform topology-based hold
optimization. The Hold Slack Optimization dialog box includes
optimization effort levels that you can specify. If you select low effort,
the hold slack optimization is restricted by preserving the worst
negative setup slack and total negative setup slack. No new setup
violation can be created and no setup slack might worsen. If you
select medium effort, only the worst negative slack must be
preserved, but the new setup violations can be created if they do not
8-96
exceed the worst setup slack. If you select high effort, the fixing hold
becomes the primary goal of the optimization. All netlist changes that
improve the hold slack are accepted without considering the setup
slack. The algorithm simultaneously considers the best and worst
operating conditions for cells and parasitics.
To fix topology-based hold slack violations with optimization,
1. Enter astTopoHold.
The Hold Slack Optimization dialog box appears.

8-97
For descriptions of the astTopoHold command options, see

Preserving the maximum transition time and capacitance during hold
slack fixing is supported in all the effort levels. Therefore, running the
hold slack optimization is recommended at the end of the flow when
all other violations are fixed.
Low effort optimization can be applied during postplacement
optimization phase 1 when the appropriate option is selected. During
postplacement optimization phase 2, the hold fixing is performed
twicefirst in high effort, then in medium effort. During postrouting
optimization (after global routing, track assignment, or detail routing)
the medium effort of hold fixing is performed.
You can apply the cell sizing technique during hold fixing by using the
Apply only sizing operation option in the Hold Slack Optimization
dialog box. This option can be used with both topology and nontopology-based techniques; When it is selected, hold fixing can be
done only by using the sizing operation. This option does not allow
extra buffers to be added to the current netlist.
User Specified Buffer List. You can specify the file name of a
buffer list in the Hold Slack Optimization dialog box to use specially
designed delay cells to fix hold slack violations. You list cell master
names of buffers to be used for hold fixing in the file, and only these
buffers will be used during hold fixing.
Delay cells are usually marked as DELAY_CELL in the design library,
or they are set as such by the astSetDelayCell command. In
most cases, delay cells are logically equivalent to a buffer and can

8-98
be considered as a buffer with a large internal delay. However, you

might need to distinguish delay cells to fix hold violations for specific
reasons such as
Supporting existing libraries with specially marked DELAY_CELL

cells
Requiring specially designed cells such as cells with the same

footprint
Requiring cells with large delays but with a small area optimized
only for hold time fixing
The following conditions apply to the buffer list:
Cell names can contain wildcard characters.
Only buffers are extracted from the list; inverters or other cells are
not extracted.
The DONT_TOUCH and DONT_USE attributes are overwritten

for buffers selected from the list.
Only the buffer insertion algorithm honors the buffer list you
define; the cell sizing algorithm uses logical equivalent
information for buffer sizing.
The buffers specified in the buffer list are used only by the
astTopoHold command and do not affect other commands or
optimizations.
Delay Cells (Buffers) in the Flow. A delay buffer is a buffer that

can be used exclusively to fix hold violations. These cells are marked
DELAY_CELL and are not used in any other optimization such as
setup, maximum transition, and maximum capacitance. However,

8-99
hold fixing algorithms can use other buffer cells for hold fixing. In this
instance, the cells marked as DELAY_CELL are an exclusive subset
of the buffer cells used by the hold fixing algorithm. In summary,
DELAY_CELL buffers are used only by the hold fixing algorithm;

other algorithms do not use these cells.
For hold fixing, all buffers including those marked DELAY_CELL

are used.
For setup fixing, only those buffers that are not marked as
DELAY_CELL are used.
The DELAY_CELL attribute does not overwrite the DONT_USE

and DONT_TOUCH attributes.
You use the astSetDelayCell command to set the DELAY_CELL

property on a cell.
Delay Insertion for Specified Nets. You can specify specific nets
for hold fixing by using the Nets from file option in the Hold Slack
Optimization dialog box. Hold fixing is accomplished by adding
buffers on these nets.
Flows you specify often rely on fixing special types of violations for a
particular situation. In these situations, you only need to provide a list
of nets or endpoints to be optimized. For example, you might need to
fix violated paths with back-annotated timing from a sign-off timer, or
you might need to fix scan-related violations only, rather than all
violations.
If you have two different SDC files that represent two different modes
of operation, you can fix hold violations reported with one SDC file
while preserving the setup slack with the other SDC file. Because the
timer can only recognize one SDC file at a time, it is important to

8-100
create a cut set of nets for hold fixing that does not overlap with any
setup critical path. With this cut set of nets, you can perform hold
fixing without disturbing the setup slack.
You use the astHoldGenerateCutSet command to generate
names of nets that have to be buffered for hold violation fixing. The
astHoldGenerateCutSet command gets the list of hold violated
paths from the timing report. Before running the
astHoldGenerateCutSet command, you use the timing report
options from, through, and to to get a subset of hold violated
paths that you are interested in fixing (see Using Timing Reports
on page 7-3).
The syntax for astHoldGenerateCutSet is
astHoldGenerateCutSet "file.name"
The following conditions apply to the net list:
Net names can use wildcard characters.
The last net on every hold violated path makes a default cut set.
Every net on the cut set is optimized.
The list of nets might include a second and third field for each entry,
which specify the required rise and fall delays that need to be
inserted into the net. If the optional delay numbers are specified,
optimization introduces delay equal to or greater than these values
for rise and fall, possibly with a chain of buffers. If only one delay
number is specified, that number is used for both rise and fall delays.
If no delay is specified for the net, a single buffer attempting to fix the
hold slack is inserted into the net.

8-101
You use the User specified insertion delay option in the Hold Slack
Optimization dialog box to specify whether to use the rise and fall
delays. If the User specified insertion delay option is deselected,
the rise and fall delays are ignored, and optimization tries to fix hold
by inserting one buffer into the specified net. If the User specified
insertion delay option is selected, optimization tries to honor the
delay numbers specified.
Note:
Optimization is driven by the setup and hold slack calculated by
the Astro timer, so the optimization might not completely solve
correlation problems. You might need to control target setup and
hold slack to achieve the best result for the flow.
Debugging Messages for Unfixed Violations. This section lists
debugging messages and possible causes reported for unfixed
violations.
>>Rejected by OV : Move
An action was rejected because of big cell displacement during
placement legalization. The maximum displacement is reported
in the log file as
"PRO: OV CONSTRAINT :: Maximum displacement = 69120"
where the number is in user units. The maximum displacement

value can be changed by
axSetIntParam "pds" "ov_max_displacement" 10
where the number is the maximum displacement measured in

the height of the row.

8-102
>>Rejected by OV : Number
An action was rejected because a large number of cells were
moved during placement legalization. The maximum number of
moved cells is reported in the log file as
"PRO: OV CONSTRAINT "Maximum number of moved cells = 100"
The maximum displacement value can be changed by

axSetIntParam "pds" "ov_max_displaced_cells" 50
>>Rejected by Slack : WNS

An action was rejected because worst negative setup (WNS)
slack was not preserved. This message is reported only in low or
medium optimization effort.
>>Rejected by Slack : TNS
An action was rejected because total negative setup (TNS) slack
was not preserved. This message is reported only in low
optimization effort.
>>Rejected by Slack : TNH
An action was rejected because total negative hold (TNH) slack
was not preserved.
Area Recovery
Use the astAreaRecovery command to perform area recovery on
your design. This command downsizes cells or removes buffers to
decrease the utilization of the cell while maintaining certain timing
aspects. The default behavior is to not make the setup slack worse.
You can run astAreaRecovery before or after the routing stage.
The astAutoPlace command performs area recovery during
preplacement optimization and postplacement optimization after
clock tree synthesis.

8-103
You can use the area_recovery_entire_design variable to

specify that Astro remove excessive buffers that are inserted by
other optimization steps. Enabling this variable forces area recovery
to work on all paths, including those with negative slack, and not just
on those with positive slack.
To get the best area recovery results, do the following:
1. Specify that area recovery works on all the paths in the design.
Enter,
define area_recovery_entire_design 1
2. Set the target utilization to a low value. For example, enter a

value of 20 in the Target Max Utilization box in the Optimization
page of the AstroTime Timing Setup dialog box
(atTimingSetup).
3. Perform area recovery, using astAreaRecovery.

8-104
9
Clock Tree Synthesis and Clock Tree
Optimizations
Astro clock tree synthesis solves complicated clock tree synthesis

problems, such as blockage avoidance and the correlation between
prerouting and postrouting. Clock tree optimization improves both
clock skew and clock insertion delay by performing buffer sizing,
buffer relocation, gate sizing, gate relocation, level adjustment,
reconfiguration, delay insertion, dummy load insertion, and
balancing of interclock delays.
About Astro Clock Tree Synthesis
Checking Clock Tree Data in the Design
Viewing Clock Structures in the Design
9-1
Setting Clock Tree Synthesis Common Options and Preparing

Clocks
Performing Clock Tree Synthesis After Placement
Routing Clock Nets
Chapter 9: Clock Tree Synthesis and Clock Tree Optimizations

9-2

Astro clock tree synthesis is built on top of Astro advanced
technologiesincluding parasitic extraction, delay calculation,
timing analysis, placement, and routing. Any improvement in these
Astro advanced technologies benefits clock tree synthesis as well.
Astro clock tree synthesis solves complicated clock tree synthesis
problems, such as blockage avoidance and the correlation between
prerouting and postrouting.
Astro clock tree synthesis provides the following features to achieve
timing closure:
A clock browser to view the design clock structure
Global skew clock tree synthesis
Local skew clock tree synthesis
Real clock useful skew clock tree synthesis
Ideal clock useful skew clock tree synthesis
Interactive clock tree synthesis and planning
Interclock delay balance
Splitting a clock net to replicate the clock gating cells
Clock tree optimization
Postrouting clock tree optimization with Star-RCXT extracted

parasitic view
Incremental clock tree synthesis
In-place clock tree synthesis

9-3
High-fanout net synthesis
Concurrent multiple corners (worst-case and best-case) clock

tree synthesis
Concurrent multiple clocks with domain overlap clock tree

synthesis
Editing clock tree capability
Astro clock tree synthesis supports the following design styles:
Multiple clocks with or without domain overlapping
Hierarchical design with the hierarchical timing view
Multilevel gated clocks
Chip or block design with hard macros or blockages
Nonunate gated clocks such as XOR gates
Reconvergent clock paths
Multiple voltage designs
Clocks with clock-gating cells
User-predefined clock tree structure
User-predefined clock routing rules
The timing information for clock tree synthesis is obtained from the
SDC file. Some timing information can be changed and set at the
command line or by using Astro. If you have used the timing-driven
layout capabilities of Astro, you already have most of the relevant
timing information.

9-4
The following two tables summarize many of the commands you can
use that pertain to clock tree synthesis. Table 9-1 lists Scheme
commands and Table 9-2 lists Tcl commands.
Table 9-1
Clock Tree Synthesis Scheme Commands
Task
Scheme command
Set clock options
astClockOptions
Analyze clock trees
astClockTiming
Optimize clock trees
astCTO
View clock structure
astClockBrowser
Perform interclock delay

balance
astCTOInterClocksBalance
Check to see whether

design is ready for clock
tree synthesis
astCheckDesignForCTS
Synthesize clock trees
astCTS
Perform basic clock tree

synthesis
astCTSBasic
Delete clock trees
astDeleteClockTree
Perform incremental clock

tree synthesis
astECOCTS
Set attributes for clock trees
astMarkClockTree
Perform postrouting clock

tree optimization
astPostRouteCTO
Report clock skew
astSkewAnalysis
Split a clock net
astSplitClockNet
Provide additional
constraints for transition
delay
ataSetAndPropagateMaxTransClock

9-5
Table 9-1
Clock Tree Synthesis Scheme Commands (Continued)
Task
Scheme command
Report total power

consumed by a clock tree
astReportClockTreePower
Define clock routing rules
axgDefineVarRule
Set clock routing minimum

and maximum layers
axgSetMinMaxLayer
Set clock routing rules to

nets
axgSetNetConstraint
Perform interactive clock

tree synthesis
ctiCTS
Table 9-2
Clock Tree Synthesis Tcl Commands
Task
Tcl command
Set clock options
set_clock_tree_options
Optimize clock trees
optimize_clock_tree
Perform interclock delay

balance
balance_inter_clock_delay
Synthesize clock trees
compile_clock_trees
Delete clock trees
remove_clock_tree
Perform incremental clock

tree synthesis
optimize_clock_tree -eco
Set attributes for clock trees
mark_clock_tree
Perform postrouting clock

tree optimization
optimize_clock_tree -post_route

9-6
Table 9-2
Clock Tree Synthesis Tcl Commands (Continued)
Task
Tcl command
Split a clock net
split_clock_net
Define sync/ignore pin
set_clock_tree_exceptions
Remove predefined sync/

ignore pin
remove_clock_tree_exceptions
Set buffers/inverts used in

CTS/CTO
set_clock_tree_references
Check design before CTS
check_design_for_cts
Run useful skew

optimization
useful_skew_opt
To see the clock tree synthesis flow, as it works with postplacement

optimization, see Figure 8-1 on page 8-8.
Preparing Library Data

To achieve your expected clock tree synthesis results, make sure the
cell masters in your reference libraries have the necessary timing
information. If you used the timing-driven layout capabilities of Astro,
you already have most of the relevant timing information.
Cell masters or macros used on clock paths and buffers or inverters
to be used during clock tree synthesis should have the timing
information in Table 9-3 defined in the CLF file or LM view. Use the
auDumpCLF command to write a text file for reference.

9-7
Table 9-3
Timing Information
Timing information
Defined in
Cell delay table
clfCreateTable
Transition delay table
clfCreateTable
Ignore port definition
dbDefineIgnorePort
Synchronous port delay
ataDefineSyncPort and ataDefineSyncPin
Clock port definition
dbSetCellPortTypes with input and clock
Clock-gating integrated cell

definition
dbSetLModeSubType with clock
Boolean function
defineBooleanFunction
Dont touch cell
defineCellDontTouch
Dont use cell
defineCellDontUse
Maximum capacitance
defineCellMaxCapacitance
Maximum fan-out
defineCellMaxFanout
Maximum transition delay
defineCellMaxTransition
Synchronous port delay

table
defineClockNetworkTLU
Flip-flop definition
defineFlipFlopFunction
Latch definition
defineLatchFunction
Port capacitance
definePortCapacitance
Trigger edge at a clock port
defineTimingTLU with Setup_rising,

Setup_falling, Hold_rising, Hold_falling,
Clock_rising or Clock_falling

9-8
Note:
The trigger edge (rise or fall) information is highly important in
clock tree synthesis. If there is no trigger edge information at a
clock porteven though you have defined it as a clock port with
the dbSetCellPortTypes commandit is identified as an
implicit ignore pin by the tool, because the tool does not know
whether it should be synchronized at the rising or falling edge.
If a sequential cells input port has no clock port definition but has a
constraint timing arc defined such as Setup_rising,
Setup_falling, Hold_rising, Hold_falling, it is considered
a clock port in Astro clock tree synthesis.
Use the astSetDontTouch and astSetDontUse commands to
define the dont touch and dont use cell masters. Use the
ataDumpSDC command to write these settings to a text file for
reference.
Preparing Design Data

Before running clock tree synthesis, prepare your design library with
placement already completed. Perform optimization to solve any
timing violations.
Make sure your design has the necessary timing information. If you
used the timing-driven layout capabilities of Astro, you already have
most of the relevant timing information.
The astCTS, astCTO, astHFCTS, astSplitClockNet, and
astPostRouteCTO commands all read constraints set in the Clock
Common Options dialog box (astClockOptions), such as the
Maximum Transition Delay, Maximum Load Capacitance, Maximum
Fanout, Maximum Insertion Delay, Minimum Insertion Delay, and
Maximum Buffer Level options. This common capability provides
9-9
consistency among the commands related to clock tree synthesis.

Furthermore, this common capability also applies if you use the
ataSetAndPropagateMaxTransClock and
ataSetAndPropagateMaxCapClock commands to specify
additional transition delay constraints.
See Physical Implementation Online Help for more information about
the ataSetAndPropagateMaxTransClock command.
Note:
If you specify the same constraints (maximum transition delay,
maximum load capacitance, maximum fanout, and maximum
buffer level) in the SDC, library, and in the Clock Common
Options dialog box, Astro uses the most conservative value
specified.
Your design can have the timing information in Table 9-4 defined in
the SDC or Scheme commands. You can use the ataDumpSDC
command to write a text file for reference.
For more information, see Effects of Synopsys Design Constraints
on Timing Analysis and Optimization on page 7-37.
Table 9-4
Design Preparation Timing Information
Timing information
Defined with
Clock cell
The astSetClockCell command
Delay cell
The astSetDelayCell command
Dont touch cell
The astSetDontTouch and

astSetCellInstDontTouch commands
Dont use cell
The astSetDontUse command
Default transition time
The ataSetNetCapTransAndDelayTime
command

9-10
Table 9-4
Design Preparation Timing Information (Continued)
Timing information
Defined with
Clock source
The create_clock command
Generated clock
The create_generated_clock command
Ignore pin definition
The ataDefineIgnorePin command
Synchronous pin definition
The ataDefineSyncPin command
Target insertion delay
The set_clock_latency command
Target transition time at

clock port
The set_clock_transition command
Driving resistance
The set_drive command
Driving cell
The set_driving_cell command
Input transition time
The set_input_transition command
Maximum net capacitance
The set_max_capacitance command
Minimum net capacitance
The set_min_capacitance command
Maximum transition time
The set_max_transition command
Minimum transition time
The set_min_transition command
Note:
The clock source information (the create_clock command) is
essential in clock tree synthesis. Without this information, Astro
clock tree synthesis will not insert any clock trees.
If you have defined the set_clock_latency command, Astro
clock tree synthesis tries to insert a clock tree with the delay as close
as possible to your settings so that you will have similar timing
reports for both ideal clock and real clock.

9-11
If you have defined the set_clock_transition command, Astro

clock tree synthesis tries to insert a clock tree with the transition time
at each clock port of sequential gates as close as possible to your
settings so that you will have similar timing reports for both ideal
clock and real clock.
The set_clock_transition command does not apply to the
clock source. The transition time at the clock source is calculated
based on real parasitic information.
If you want Astro clock tree synthesis to use your defined transition
time at clock source, use the set_input_transition,
set_driving_cell, or set_drive command for the clock source
at the boundary or the ataSetNetCapTransAndDelayTime
command for the clock source at the internal pin.
Astro has some default timing constraints stored in your design. Use
the atTimingSetup command to view or modify them. These
changes might not affect clock tree synthesis results if you run Astro
clock tree synthesis without CTA (clock tree analyzer).

You can check the clock tree data in your design by using the
astCheckDesignForCTS command.
To check clock tree data,
1. Enter astCheckDesignForCTS.
The Check Design For CTS dialog box appears.

9-12
2. Enter the name of the file to which design-related checks are

output.
3. Choose a report type.
- Select Detail (the default) to report all the design-related
checks.
- Select Itemized to report one or more specific checks.
4. If you select Itemized, a list of items to be checked and reported
will be activated. Select from the following items:
- Clock Tree Overview
- Sync/Ignore Pins

9-13
- Clock Domains Overlap

- Buffers/Inverters Used During CTS
- Delay Cells Used During CTS/CTO
- Dummy Load Cells Used During CTO
- LEQ Cells Used During CTO
- Dont Touch Cell Instances
- Dont Touch Clock Nets
- Clock Tree Constraints/Targets
5. Click OK or Cancel.

You can view and identify the clock structures in your design by using
the astClockBrowser command. The clock browser displays a list
of clock trees in the design and lets you highlight the clock path
structure in the design layout window. This makes it easier to analyze
the clocks in your design and debug the timing information.
To view and identify clock structures,
1. To start the clock browser, enter astClockBrowser or choose
Clock > Utility Clock Browser.
The Clock Browser dialog box appears.

9-14
Figure 9-1
Clock Browser Dialog Box
Source
Sink pin
count
Ignore pin
The clock browser loads common graph data when it is first

invoked for a design. On subsequent reloads of the clock browser
for the same design, the common graph data is not reloaded
unless it was unloaded by some other command or process. If
that occurs, the common graph data is reloaded by the clock
browser.

9-15
Note:
The time required to load the common graph data increases
with design complexity. Allow more time for larger designs.
The clock browser does not automatically refresh the common
graph data. If another command or process changes or unloads
the common graph data while the clock browser is running, the
changes are not reflected in the clock list or clock path structure.
To see the changes, click the Close button and restart the clock
browser.
2. Click Show Selected to display the path of the clock net selected
in the clock list. The clock list shows all the clocks in the design
by name.
To view more detail about a particular clock, click the expansion
(+) icon to expand the clock tree and show the next level of the
clock structure.
When you double-click a clock name in the clock browser, that
clock is highlighted in a preslected color, and the full clock path is
visible in the design layout window in the same color. Each time
you double-click another clock name in the browser and then
click Show Selected, the clock path is displayed in a different
preselected color in the design layout window.
3. Use the color option to control the color of the clock path
displayed in the clock list and design layout window. You can
enter a color to use, or you can use the preselected color.
Note:
Color appears only if the clock is highlighted, otherwise it
remains gray.
4. Click Clear All to clear all clock paths highlighted in the clock
browser and the design layout window.
9-16
5. Click Save to File to create text files of clock information, which

displays the Save to File dialog box.
Figure 9-2
Save to File Dialog Box
Select the clock information you want in written to a file and enter
a file name or use the default file name, as shown in Figure 9-2.
When you enable all the options in the Save to File dialog box,
the report generated is identical to the report generated with the
astReportClockTree command when all its options are
enabled. The clock summary generated by the
astClockBrowser command, however, reports ignored
subtrees of the clock tree, which are not reported by the
astReportClockTree commands.
6. Click Close to exit the clock browser.
For details about the astClockBrowser command options, see the
Physical Implementation online Help.

9-17

Preparing Clocks
When you have completed the library preparation and design
preparation, you are ready to set the clock common options and
synthesize your clock trees.
Setting the Clock Common Options

To set the clock common options,
1. Enter astClockOptions or choose Clock > Clock Common
Options.
The Clock Common Options dialog box appears.

9-18
Figure 9-3
Clock Common Options Dialog Box

The options are described in the sections following this
procedure.
Setting Clock Tree Synthesis Common Options and Preparing Clocks

9-19
Defining the Clock Tree Root

The clock tree root is the starting point of a clock tree. Astro clock
tree synthesis identifies all clock sources defined by create_clock
as clock tree roots.
By default, Astro clock tree synthesis synthesizes all clocks defined
by create_clock. It is not necessary to specify all of them explicitly
in the Clock Nets box of the Clock Common Options dialog box
(Figure 9-3). However, you can use the Clock Nets box to control the
tool in the following cases.
Case 1: You want to have a test run on only a few clocks.
In this case, enter the clock nets you want to test in the Clock Nets
box in the Clock Common Options dialog box. If you do not know the
net names,
1. Click the Search button next to the Clock Nets box.
The Search Clock Nets dialog box appears.
2. Click Show Root Clock Nets.
All defined clock source nets appear in the Net Name List.
3. Select the nets you want in the Net Name List.
4. Click OK.
The selected nets appear in the Clock Nets box in the Clock
Common Options dialog box.
Case 2: You want to synthesize a subtree of the defined clock, or you
want to synthesize a clock, net by net, in bottom-up order.

9-20
Enter the subtrees net name in the Clock Nets box in the Clock
Common Options dialog box. Because you have a defined clock at
the top, it is not necessary to have a clock definition for each subtree.
Note:
When you define a clock for a subtree of the defined clock, you
create multiple clocks that have a domain overlap. This might
result in increased runtime.
To find the subtrees net name,
1. Click the Search button next to the Clock Nets box.
The Search Clock Nets dialog box appears.
2. Set a pattern to Net Pattern.
3. Click Search.
All nets that match the pattern appear in the Net Name List.
4. Select the nets you want in the Net Name List.
5. Click OK.
The selected nets appear in the Clock Nets box in the Clock
Case 3: You want to synthesize clock trees in the order you expect.
You must specify the clock nets in the Clock Nets box of the Clock
Common Options dialog box. The order you provide is the order of
synthesis.

9-21
Important:
The most critical clock should be the last clock, because the
buffer that is inserted last has higher priority for the location
calculated by the placement overlap removal engine. That is,
when placed cells overlap with an inserted buffer, those cells are
moved away to place the buffer. As a result, the timing of the
latest inserted clock tree has fewer disturbances due to overlap
removal.
The Clock Nets box of the Clock Common Options dialog box can be
used for pin names or clock names. The clock name is the name you
provide when you use the create_clock command.
Synchronous Pin and Port Definition

The ataDefineSyncPort and ataDefineSyncPin commands
identify synchronous ports and pins for a cell instance and specify
the minimum and maximum phase delays for the synchronous ports
and pins at multiple operating conditions. However, the
dbDefineSyncPin and dbDefineSyncPort commands can still
be used to perform the same functions, except that only one corner
or phase delay can be defined and you have to use a scaling factor
to scale the phase delay to the other conditions.
Note:
The set_clock_tree_exceptions Tcl command can be
used instead of ataDefineSyncPin and
ataDefineSyncPort commands in Tcl scripts.
replace the phase delay scaling factor. They also allow for the
definitions of the worst, typical, and best conditions within one
command. The ataDefineSyncPort command can also define

9-22
boundary ports as synchronous ports. Similarly, the

ataPurgeSyncPort and ataPurgeSyncPin commands can
purge the defined synchronous ports and pins.
have higher priority than the dbDefineSyncPin and
dbDefineSyncPort commands. That is, when the
dbDefineSyncPin and dbDefineSyncPort commands as well
as the ataDefineSyncPin and ataDefineSyncPort
commands are in the design for the same cell, the
ataDefineSyncPin and ataDefineSyncPort commands take
precedence. This means that Astro uses the phase delay and
operation conditions defined by the ataDefineSyncPin and
ataDefineSyncPort commands, but be aware of any
dbDefineSyncPin and dbDefineSyncPort command
definitions on other cells.
Command Examples
ataDefineSyncPin cellId "instName" (("portName" "rr" /
(B_min,B_max) (T_min,T_max)(W_min,W_max))
ataDefineSyncPin (geGetEditCell()) "F13_DSPMvHBSP_512x19" /
(( "CLK" "rr" 0 0 0 ))
where rr is nonInvertRise, fr is invertRise, ff is

nonInvertFall, and rf is invertFall.
ataDefineSyncPort "cellName" (("portName" "rr" /
(B_min,B_max) (T_min,T_max)(W_min,W_max))
ataDefineSyncPort "" (( "out" "rr" 0 0 0 ))
where leaving the cellName as "" defines the top cell boundary
port as a synchronous port.
ataPurgeSyncPort "*"
ataPurgeSyncPin cellId "*"
Astro supports only the purging of all synchronous ports and pins.

9-23
Clock Tree Sink Pins and Synchronous Pins

The clock tree sinks are the synchronous points of a clock tree. Astro
clock tree synthesis identifies the following pins as clock tree sinks.
Sequential cells clock port with trigger edge information
User-defined synchronous pins with the ataDefineSyncPin or

ataDefineSyncPort command
If you are not sure whether the clock ports of sequential cells in your
libraries have trigger edge information, review your library
preparation or use the auDumpCLF command to write a text file. In
the file, you must have defineTimingTLU statements with the
following keywords for all sequential cells.
Setup_rising
Setup_falling
Hold_rising
Hold_falling
Clock_rising
Clock_falling
The following examples show that clock port CK of flip-flop

SDFFSRX2 has rise trigger information. Astro clock tree synthesis
tries to balance all rising delays to CK of any SDFFSRX2s cell
instances.
Example 1:
defineTimeTLU "SDFFSRX2" "D" "CK" "NONUNATE" "Setup_rising"
...

9-24
Example 2:
defineTimeTLU "SDFFSRX2" "D" "CK" "NONUNATE" "Hold_rising"
...
Example 3:
defineTimeTLU "SDFFSRX2" "CK" "Q" "NONUNATE" \
"Clock_rising"...
Note:
If a sequential cell is defined as a clock-gating integrated cell with
the dbSetLModeSubType command, or its output port has a
create_generated_clock defined, its clock port is not
treated as a clock sink (synchronous) pin, even if it has trigger
edge information. Astro clock tree synthesis traverses that pin
and synthesizes clock trees beyond that pin.
If you want to synchronize a nonclock pinsuch as a combination
logic gates pin, a macros pin, or a sequential gates set/reset pin
you must define it as a synchronous pin explicitly, using the
dbDefineSyncPin or dbDefineSyncPort command. The
dbDefineSyncPin command is used for the instance; whereas,
the dbDefineSyncPort command is used for the master.
Review your library preparation and design preparation to make sure
your synchronous port and synchronous pin definitions are
completed.
To verify that you have synchronous ports defined in your libraries,
use the auDumpCLF command to write a text file. In the file, you must
have dbDefineSyncPort statements for all defined synchronous
ports.

9-25
To verify that you have synchronous pins defined in your design, use
the dbDumpSyncPin command to write a text file. In the file, you
must have dbDefineSyncPin statements for all defined
synchronous pins.
Pulse-Generated Clocks
Astro supports the use of non-increasing clock edges when defining
pulse-generated clocks. The -edges option of the
create_generated_clock command allows you to define a
pulse clock.
Consider the two clocks shown in Figure 9-4.
Figure 9-4
TIME
Defining Pulse-Generated Clocks

0
10
CLK
1.5 2.5
11.5 12.5
PULSECLK
Here is the Tcl command syntax that defines these two clocks:
create_clock -waveform {0 5} -period 10
-name clock [get_port clock]
create_generated_clock -edges {1 1 3} -name pulseclk
-source [get_ports clock] [get_pins PG/z]

9-26
The latency and the duration of the pulse for the pulse clock depend
on the timing from the source point of the master clock to the source
point of the pulse clock. As with all generated clocks, Astro
automatically computes the latency from the master clock to the
pulse-generated clock.
For the clocks defined in Figure 9-4, the latency from the master
clock to the generated clock is as follows:
Clock (Rising) to PulseClk (Rising) 1.5 ns
Clock (Rising) to PulseClk (Falling) 2.5 ns
The waveform definition of the pulse-generated clock is shown in the
output that is generated with the report_clock -attribute Tcl
command.
For report_clock -attribute, the information is as follows:
****************************************
Report : clock
Design : fp
Version: 2007.03
Date
: Thu Feb 1 03:00:48 2007
****************************************
Attributes:
p - Propagated clock
G - Generated clock
I - Inactive
clock
Clock
Period
Waveform
Attrs
Sources
-----------------------------------------------------------------------------clk
10.00 {0.00
5.00}
p
clk
pulseclk
10.00 {0.00
0.00}
p G
PG/z
The waveform definition for the pulse clock is {0 0}, and the period is
10 ns. Therefore the phase relationship between the two clocks is as
follows:

9-27
Setup:
Clock -> Pulse-generated Clock : 0 -> 10
Pulse-generated Clock -> Clock : 0 -> 10
Hold:
Clock -> Pulse-generated Clock : 0 -> 0
Pulse-generated Clock -> Clock : 0 -> 0
Clock Tree Stop Pins and Ignore Pins

The clock tree stop pins, sometimes referred to as ignore pins, are
the ending points of a clock tree. Astro clock tree synthesis does not
balance delays for ignore pins.
Astro clock tree synthesis identifies the following pins as ignore pins:
User-defined ignore pin, defined with the dbDefineIgnorePin

or ataDefineIgnorePin command
Sequential gates clock port without trigger edge information
Sequential gates nonclock port, such as set/reset
Logic gates input pin without a timing arc to its output pin
Logic gates output pin without a connection to a net
Any pin, such as a boundary output pin, that makes clock tree
traversing stop
An ignore pin defined by users is called an explicit ignore pin. An

ignore pin identified by the tool is called an implicit ignore pin.

9-28
Note:
Astro clock tree synthesis reports all ignore pins in the log file.
Review the warnings in the log file carefully. If you find that a
synchronous pin or the clock port of a sequential gate is ignored,
see Clock Tree Sink Pins and Synchronous Pins on page 9-24
for information about how to fix the problems.
Note:
In the Astro CTS flow, Astro clock tree synthesis isolates ignore
pins from its clock tree by inserting a small buffer. Then you use
the pdsHFNOptNet command to fix transition and capacitance
violations for nonclock nets.
Buffers and Inverters for Clock Tree Synthesis

Astro clock tree synthesis uses buffers or inverters in clock tree
construction. The tool identifies the buffers and inverters if their
Boolean function is defined in library preparation. If you want to limit
some of them for clock tree synthesis only, use the
astSetClockCell command to define them as clock buffers or
inverters.
By default, Astro clock tree synthesis synthesizes clock trees with all
the buffers and inverters available in your libraries, except cells
marked as dont use. It is not necessary to specify all of them
explicitly in the Buffers/Inverters box in the Clock Common Options
dialog box (Figure 9-3 on page 9-19) to run Astro clock tree
synthesis. However, in the following cases, you should use the
Buffers/Inverters box to control the tool.
Case 1: You want to limit some buffers and inverters in clock tree
construction.

9-29
In this case, enter the buffers or inverters you want to use in the
Buffers/Inverters box in the Clock Common Options dialog box. If you
do not know the name of the buffers and inverters,
1. Click the Search button next to the Buffers/Inverters box.
The Search Cells dialog box appears.
2. Click Show Buffers/Inverters.
All buffers and inverters appear in the Cell Name List.
3. Click the objects in the Cell Name List to select the buffers or
inverters you want.
4. Click OK.
The selected buffers and inverters appear in the Buffers/Inverters
box in the Clock Common Options dialog box.
Important:
The more buffers and inverters you provided, the better results
and more runtime you might have.
The priority of available buffers and inverters in clock tree synthesis
is as follows:
1. Buffers and inverters entered in the Buffers/Inverters box in the
Clock Common Options dialog box
2. Buffers and inverters defined as clock buffers and inverters by the
astSetClockCell command
3. Buffers and inverters in your libraries, except cells marked as
dont_use

9-30
Case 2: You want to use the buffers or inverters with dont_use cell
attributes for clock tree construction.
In this case, enter the buffers or inverters with dont use cell attributes
in the Buffers/Inverters box of the Clock Common Options dialog
box.
The buffers or inverters with dont_use cell attributes might be
interpreted differently by different customers. In some customer
libraries, they are designed for clock tree synthesis only and not used
for logic synthesis or datapath optimization. In other customer
libraries, they are designed for simulation only and not used for real
designs.
To make sure Astro clock tree synthesis uses them for clock tree
synthesis, you must define them as clock cells by using the
astSetClockCell command or specify them in the Buffers/
Inverters box in the Clock Common Options dialog box.
For example, when buffers bufA, bufB, bufC, and bufD are defined in
the library and the dont_use attribute is set for bufA and bufB, the
following cases show how you control which buffers are used for
clock tree synthesis and clock tree optimization.
Case A:
- In the Clock Common Options Synthesis Buffers/Inverters
box, specify bufC and bufD.
- In the Clock Common Options Optimization Buffer Sizing:
LEQ Cells box, specify bufA, bufB, bufC, and bufD.
- No cells are specified with the astSetClockCell command.
Clock tree synthesis uses only bufC and bufD.

9-31
Clock tree optimization can use all four buffers.
Case B:
box, specify bufC and bufD.
LEQ Cells box, specify bufC and bufD.
- Buffers bufA and bufB are specified with the
astSetClockCell command.
Clock tree synthesis and clock tree optimization use only bufC
and bufD because the buffers defined in the Clock Common
Options dialog box take precedence over those defined with the
Case C:
box, no buffers are specified.
LEQ Cells box, no buffers are specified.
- No cells are specified with the astSetClockCell command.
Clock tree synthesis and clock tree optimization use only bufC
and bufD because they are the only buffers without the
dont_use attribute.
Case D:
box, no buffers are specified.

9-32

LEQ Cells box, no buffers are specified.
- Buffers bufA, bufB, and bufC are specified with the
Clock tree synthesis and clock tree optimization use only bufA,
bufB, and bufC.
Logically Equivalent Cells for Clock Tree Optimization

Logically equivalent (LEQ) cells are used for cell sizing in clock tree
optimization. The tool extracts logically equivalent information from
all cells in your libraries, based on the Boolean function defined in
library preparation.
By default, Astro clock tree synthesis optimizes the inserted clock
trees with the logically equivalent cells extracted. It is not necessary
to specify buffers or inverters in the LEQ Cells box in the Clock
Common Options dialog box (Figure 9-3 on page 9-19) to run clock
tree optimization. However, you might want to use the LEQ Cells box
in the following cases:
Case 1: You want to limit some of the buffers and inverters in clock
tree optimization.
In this case, enter the buffers and inverters you want to use in the
LEQ Cells box in the Clock Common Options dialog box. If you do
not know the name of the buffers and inverters,
1. Click the Search button next to the LEQ Cells box.

9-33

inverters you want.
4. Click OK.
The selected buffers and inverters appear in the LEQ Cells box
in the Clock Common Options dialog box.
Note:
When you put both buffers and inverters in the LEQ Cells box in
the Clock Common Options dialog box, it doesnt mean that
those inverters are the logically equivalent cells of the buffers.
You are specifying that you want to use only those buffers and
inverters in the LEQ class extracted from librariesyou do not
want to use the whole list of buffers and inverters in the LEQ class
in clock tree optimization.
When you put only buffers in the LEQ Cells box in the Clock
Common Options dialog box, you are specifying that you do not
want to use the whole list of buffers in clock tree optimization.
Case 2: You want to use the buffers or inverters with dont use cell
attributes for clock tree optimization.
In this case, you enter the buffers or inverters with dont use cell
attributes in the LEQ Cells box in the Clock Common Options dialog
box.
Note:
The buffers or inverters with a dont use cell attribute might be
interpreted differently by different customers. In some customer
libraries, they are designed for clock tree synthesis only and are
not used for logic synthesis or datapath optimization. In other

9-34
customer libraries, they are designed for simulation only and are
not used for real designs. For Astro clock tree synthesis to use
them for clock tree optimization, you must define them as clock
cells by using the astSetClockCell command or specify them
in the LEQ Cells box in the Clock Common Options dialog box.
Case 3: You want to limit some of the gates (such as NAND or NOR
gates) in clock tree optimization.
In this case, enter the cells you want to use in the LEQ Cells box in
the Clock Common Options dialog box. If you do not know the name
of the cells,
1. Click the Search button next to the LEQ Cells box.
2. Select a pattern in the Cell Pattern box.
3. Click Search.
All cells match the pattern that appears on the Cell Name List.
4. Click the objects in the Cell Name List to select the cells you
want.
5. Click OK.
The selected cells appear in the LEQ Cells box in the Clock

9-35
Delay Cells
Astro clock tree synthesis uses buffers or inverters as delay cells for
delay balance. The tool identifies the buffers and inverters if their
Boolean function is defined in library preparation. If you want to limit
some of them for delay balance only, use the astSetDelayCell
command to define them as delay cells.
By default, Astro clock tree synthesis balances delays with buffers
and inverters that are defined in the Clock Common Options dialog
box, with the astSetDelayCell command, with the
astSetClockCell command, and in the libraries. It is not
necessary to specify all of them explicitly in the Delay Cells box in the
Clock Common Options dialog box (Figure 9-3 on page 9-19) to run
delay balance. However, you might want to use the Delay Cells box
in the following cases:
Case 1: You want to limit some buffers and inverters in delay
balance.
In this case, you enter the buffers and/or inverters you want to use in
the Delay Cells box of the Clock Common Options dialog box. If you
do not know the names of the buffers and inverters,
1. Click the Search button next to the Delay Cells box.
All buffers and inverters appear on the Cell Name List.
inverters you want.
4. Click OK.

9-36
The selected buffers and inverters appear in the Delay Cells box
of the Clock Common Options dialog box.
Important:
The more delay cells you provide, the better results and more
runtime you might have.
Case 2: You want to use the delay cells with dont use cell attributes
for delay balance.
In this case, you put the delay cells with the dont use cell attributes
in the Delay Cells entry of the Clock Common Options dialog box.
The priority of delay cells used in delay insertion is as follows:
Cells entered in the Delay Cells box of the Clock Common

Options dialog box
Cells defined as delay cells by the astSetDelayCell

command
Cells defined as clock cells by the astSetClockCell

command
Buffers and inverters extracted by the tool, except those marked

as dont_use cells.
Dummy Cells
Astro clock tree synthesis uses buffers or inverters as dummy cells
for load balance. The tool identifies the buffers and inverters if their
Boolean function is defined in library preparation.

9-37
Note:
When the Dummy Load option in the Clock Common Options
dialog box is selected, Astro clock tree optimization inserts
dummy load with all available buffers and inverters in your
libraries by default. It is not necessary to specify all of them
explicitly in the Dummy Cells box in the Clock Common Options
dialog box to run dummy load insertion. However, you might want
to use the Dummy Cells option in the following cases.
Case 1: You want to limit some buffers and inverters in dummy load
insertion.
In this case, enter the buffers and/or inverters you want to use in the
Dummy Cells box of the Clock Common Options dialog box. If you
do not know the name of the buffers and inverters,
1. Click the Search button next to the Dummy Cells box.
inverters you want.
4. Click OK.
The selected buffers and inverters appear in the Dummy Cells
box in the Clock Common Options dialog box.
Case 2: You want to use the buffers or inverters with dont use cell
attributes for load balance.

9-38
In this case, you enter the buffers or inverters with dont use cell
attributes in the Dummy Cells box of the Clock Common Options
dialog box.
The priority of dummy cells used is as follows:
Cells entered in the Dummy Cells box in the Clock Common

Options dialog box

command
Buffers and inverters extracted by the tool
Clock Tree Configuration

The clock tree configuration file provides additional flexibility to
control the results of clock tree synthesis. It is considered a file with
predefined clock trees.
There are two types of configurations:
1. Hard configuration
In this configuration, the number of buffer levels and the number
of buffers in each buffer level of the clock tree (generated by clock
tree synthesis) are honored completely.
2. Soft configuration
In this configuration, the number of buffer levels and the number
of buffers in each buffer level of the clock tree (generated by clock
tree synthesis) will be flexible, depending on the target values,
such as target transition delay, target load capacitance, and
target fanout.

9-39
The syntax for this file is as follows:

begin_clock_tree <integer:number-of-levels>
clock_net <string:net-name>
buffer_level <string:buffer-name>
<integer:number-of-buffers>
end_clock_tree
Note:
When using a clock configuration files, macros will be connected
to the clock tree level based on the assigned phase delay of the
macros clock pin. The the phase delay is not specified or set to
zero on the clock pin, the macro will be connected to the top level
of the clock tree.
The first word on each line of the clock configuration file is a keyword.
The <integer:number-of-levels> is an integer for

specifying the number of buffer levels for the clock tree. When
this integer is 0, the configuration is regarded as a soft
configuration. The number of buffer levels and the number of
buffers in each upper buffer level (not specified in the
configuration file) are calculated by clock tree synthesis.
The <string:net-name> is a string of the clock net name that

the clock has inserted. You can specify the clock net name as a
regular expression, for example, clk.* or clk[10].*.
The buffer_level is in top-down order. The last

buffer_level is the bottom buffer level.
The <string:buffer-name> is a string of buffer names that is

used in the buffer level of the clock tree.

9-40
The <integer:number-of-buffers> is an integer that

specifies the number of buffers used in the buffer level of the
clock tree. When this integer is 0 (zero), the configuration is
regarded as a soft configuration. The number of buffers at that
buffer level is calculated by clock tree synthesis.
For even more control of clock tree synthesis, use the

buffer_level_pin statement to insert synchronous points at the
specified level. The syntax is
buffer_level_pin
<string:instance_name:pin>
Hard Configuration With Six Buffer Levels

The following example is a hard configuration with six buffer levels.
The clock tree synthesis would not change the number of buffer
levels nor the number of buffers in each buffer level.
; Hard configuration with six buffer levels.
begin_clock_tree 6
clock_net core/clk
buffer_level bufx6 2
buffer_level invx12 4
end_clock_tree
Soft Configuration With Four Buffer Levels

The following example is a soft configuration with four lower buffer
levels. All upper buffer levels are created by the clock tree synthesis.
Only one buffer or inverter can be used within a level.
; Soft configuration with four buffer levels.
begin_clock_tree 0

9-41
clock_net core/clk
buffer_level bufx12
buffer_level bufx12
buffer_level bufx12
buffer_level bufx12
end_clock_tree
7
11
48
268
Soft Configuration With Six Buffer Levels

The following example is a soft configuration with six buffer levels.
The number of buffers in buffer level 4 is calculated by clock tree
synthesis.
; Soft configuration with six buffer levels.
begin_clock_tree 6
clock_net core/clk
end_clock_tree
Synchronous Points Inserted at Specific Levels

The following example shows that the clock pin is connected to the
first level, which has two MUXs; the RAM is connected at the second
level; and all other flip-flops are connected at the fifth level. The
specified buffer_level_pin instance becomes part of the
preceding level (important when you have RAMs placed very close
to the source and other flip-flops are to be connected separately).
begin_clock_tree 5
clock_net Top/ClockNet
buffer_level scivx16 1
buffer_level_pin Top/Inst1/Inst2Mux/u5007:A
buffer_level_pin Top/Inst1/Inst3Mux/u15833:A
buffer_level_pin Top/Inst1/InstRam64x128:CKB

9-42
buffer_level_pin Top/Inst1/my_t_reg[5]:CKB
buffer_level_pin Top/Inst1/my_t_reg[4]:CKB
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
end_clock_tree
Clock Tree Constraints

Astro clock tree synthesis has the following clock tree constraints:
Maximum transition delay
Maximum load capacitance
Maximum fanout
Maximum insertion delay
Minimum insertion delay
Maximum buffer level
Having completed the library preparation and design preparation,

you have most of the timing constraints for clock tree synthesis. In
most cases, these constraints are for logic synthesis or datapath
optimization. If you do not want to modify these constraints, Astro
clock tree synthesis allows you to further constrain the constraints
that affect clock tree synthesis only.
To view or change clock tree timing constraints,
1. Click Constraints in the Clock Common Options dialog box.
The Clock Tree Constraints dialog box appears.

9-43
Figure 9-5
Clock Tree Constraints Dialog Box
2. Change any default settings you want to change.

3. Click OK or Apply to accept your changes.
Note:
The units for the constraints in the Clock Tree Constraints dialog
box are the same as in your technology file.
If you define both the transition and the capacitance constraints,
Astro clock tree synthesis checks both transition and capacitance to
make sure there are no violations.
The priority of timing constraints for clock tree synthesis is as follows:
Astro clock tree synthesis reads in all timing constraints from

different sources, including your libraries and your design and
those set by the ataSetAndPropagateMaxTransClock and
ataSetAndPropagateMaxCapClock commands. The most
restricted constraint is applied to the clock tree.

9-44
The maximum buffer-level constraint is the maximum number of

inserted buffers between any two preexisting gates in your clock
trees.
Note:
The number of delay cells inserted by Astro clock tree synthesis
is not limited by the maximum buffer-level constraint. The longest
path delay in the clock tree becomes the constraint for delay
balance.
The maximum insertion delay and minimum insertion delay you
specify in the Clock Tree Constraints dialog box are based on the
operating conditions you select in the Clock Common Options dialog
box. When the shortest path delay after clock tree synthesis is less
than the minimum insertion delay (when the minimum insertion delay
is greater than zero), clock tree synthesis inserts more delay cells at
the clock root so that the difference to that target value is at a
minimum. When the longest path delay exceeds the maximum
insertion delay (when the maximum insertion delay is greater than
zero), clock tree synthesis stops even if design rule checking
violations exist. As a result, you might encounter DRC violations,
which are reported as warnings in your log file.
When the maximum or minimum insertion delay is zero, clock tree
synthesis does not insert delay padding.
When you select only the Worst operating condition,
minimum < worst-shortest path < worst-longest path < maximum
When you select only the Best operating condition,

minimum < best-shortest path < best-longest path < maximum

9-45
When you select both the Worst and Best operating conditions, clock
tree synthesis stops when either target is reached.
minimum < best-shortest path < worst-longest path < maximum
For example, when minimum = 2, maximum = 5, and skew = 0.100,

Best => 2 -skew/2 < insertion delay < 2 + skew/2
Worst => 5 -skew/2 < insertion delay < 5 + skew/2
Worst/Best => 2 -skew/2 < insertion delay < 5 + skew/2
The results of this example are:

minimum insertion delay target range = 1.95 ~ 2.05
maximum insertion delay target range = 4.95 ~ 5.05
min/max insertion delay target range = 1.95 ~ 5.05
With both minimum and maximum insertion delay specified,

assuming an insertion delay of 3 after clock tree synthesis, for the
following cases:
For prelayout designs, you can estimate the latency of each clock
and directly set the estimated clock network delay value with the
set_clock_latency command in the SDC file.
When you set both SDC values with the set_clock_latency
command and constraints in the Clock Tree Constraints dialog box,
the SDC value set with the set_clock_latency command take
precedence. When you want to ignore the SDC values, select the
Ignore SDC option in the Clock Tree Constraints dialog box
(Figure 9-5 on page 9-44).

9-46
When you ignore SDC constraints and insertion delay is 3ns after
clock tree synthesis, clock tree optimization does the following:
Minimum insertion
delay
Maximum insertion
delay
Clock tree optimization
No delay padding occurs.
>0
Invalid values. The maximum insertion

delay cannot be lower than the
minimum insertion delay. The minimum
value will be adjusted to the same value
as the maximum insertion delay.
Clock tree optimization attempts to

lower insertion delay to 2.
No clock tree optimization is performed

because the minimum and maximum
constraints are already achieved.
Clock Tree Synthesis Specifications

Clock tree synthesis specifications are a set of parameters you can
use to control Astro clock tree synthesis to achieve the results you
want.
Astro clock tree synthesis has the following clock tree synthesis
specifications:
Target transition delay
Target load capacitance
Target fanout

9-47
Use the following commands to change clock tree synthesis

specifications:
axSetRealParam "acts" "target: transition delay rise" 0.15
axSetRealParam "acts" "target: transition delay fall" 0.15
axSetRealParam "acts" "target: load capacitance" 0.2
axSetIntParam "acts" "target fanout" 20
Note:
The units in the commands are the same as those in your
technology file.
Astro clock tree synthesis synthesizes a clock tree so that the
transition delay at any clock port of sequential cells is as close as
possible to the target transition delay.
If a clock has set_clock_transition defined, its transition delay
becomes the target transition delay. Thus, you have the target
transition delay goal for each clock. For clocks without
set_clock_transition defined, their target transition delay is
still set by the default (0.25 ps).
When you achieve the target transition delay goal, you will have
similar timing reports for both ideal clock and real clock.
It is not necessary to know which parameters provide the optimal
results, because the clock tree analyzer searches the optimal
parameter for clock tree synthesis by default.
If you want more control of the synthesis results, turn off the clock
tree analyzer:
axSetIntParam "acts" "CTA" 0

9-48
Gated and Nongated Clock Trees

By default, the tool performs gated clock tree synthesis. It traverses
through all gates along the clock paths between the clock source and
clock ports of the flip-flops and inserts clock trees for each net
traversed. If you want to insert a clock tree only into an indicated net,
deselect the Gated Clock Tree option in the Clock Common Options
dialog box (Figure 9-3 on page 9-19). The tool performs single net
When the Gated Clock Tree option is deselected and the clock
configuration file is indicated, the astCTS command works the same
as the astCTSBasic command.
Note:
When you run clock tree synthesis with the Gated Clock Tree
option deselected, make sure the lower level clock trees are
synthesized.
Splitting Clock Nets to Improve Clock Tree Results

The astSplitClockNet command replicates clock-gating cells to
reduce skew and insertion delay. Invoke the astSplitClockNet
command before running clock tree synthesis or high-fanout net
synthesis.
The following is an example of a simple gated clock with three gating
cells at the top level.

9-49
Clock
source
Gating
cell
Gating
cell
Gating
cell
2000
FFs
100
FFs
50
FFs
When you use the astSplitClockNet command to replicate each

of the gating cells in the previous example, all input ports are
connected to the same nets as the original gating cell. The
astSplitClockNet command balances the driving capacitance of
each of the replicated gating cells. The ideal result of this command
is shown in the following example.
Clock
source
Gating
cell x 200
Gating
cell x 10
Gating
cell x 5
200 gates
x 10 FFs
= 2000 FFs
10 gates
x 10 FFs
= 100 FFs
5 gates
x 10 FFs
= 50 FFs
When each gating cell drives roughly the same amount of

capacitance, the clusters are more balanced and the overall skew is
minimized by performing clock tree synthesis on the top net.

9-50
To balance the driving capacitance of the replicated gating cells, the

astSplitClockNet command determines the number of times to
replicate each gating cells.
The astSplitClockNet command honors the constraints defined
with the astCTS command.
The incremental placement engine in Astro is invoked from the
astSplitClockNet command to place the replicated gating cells
and resolve overlaps. This ensures that the skew and timing is not
disturbed after clock tree synthesis is complete.
Initially, the astSplitClockNet command places the replicated
gating cells at the clusters center of gravity. Subsequently, the
astSplitClockNet command moves those gating cells to
minimize skew. Finally, the astSplitClockNet command adds a
synthesized attribute to the lower level of the duplicated gating
cells.
Note:
If you want to move the replicated gating cells by using the
astCTS and astCTO commands, you must use the
astMarkClockTree command to reset the synthesized
attribute.
The astSplitClockNet command requires a file that contains the
instance names or the net names to be replicated. When you specify
the net names in the file, the astSplitClockNet command
replicates all the gating cells driven by the net.

9-51
To split a clock net,

1. Create a file to define the instance names to replicate. For
example,
top/block1/clk_gate_latch
You can use wildcard pattern matching. For example,

; pattern match
.*latch
Or specify net names to replicate. For example,

; replicate all gates driven by the net
clk_1
2. You need to mark the clock gating cells as LEQ cell in the
reference library using the defineLEQCell command. For
example,
defineLEQCell "GCELL8" "GCELL12"
defineLEQCell "GCELL8" "GCELL4"
defineLEQCell "GCELL8" "GCELL16
3. Define the dont use and dont touch settings for the gating cells
in the design library.
astSetDontUse "GCELL12" #f
astSetDontTouch "GCELL12" #f

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4. The Ignore User LEQs option in the astTimingSetup

command is enable by default. You need to disable this option by
entering the following in a script:
atTimingSetup
atTimingSetupGoto "Optimization"
atCmdSetField "Ignore User LEQs" "0"
atCmdSetOptModel
atTimingSetupHide
Alternatively, you can enable user-defined logically equivalent

cells by entering atTimingSetup or by choosing Timing >
Timing Setup. In the Timing Setup dialog box,
a. Select the Optimization tab.
b. Disable the Ignore User LEQs option.
c. Click Apply.
d. Click Hide.
5. Enter astSplitClockNet to display the Split Clock Net dialog
box.
6. Enter the name of the file you created in steps 1 through 5 in the
Clock Gated Cells File Name box.
7. Select the Conditions and Optimization options for your design.

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By default, the worst case is selected to minimize the timing

analysis runtime.
8. Click OK.
Setting Clock Sinks As Fixed

Set all clock sinks as fixed before running clock tree synthesis if your
design has high utilization and tight timing requirements. This is
useful to prevent your slacks from being disturbed during clock tree
synthesis.
To set clock sinks as fixed,
1. Enter the astMarkClockTree command or choose Clock >
Utilities Mark Clock Tree.
The Mark Clock Tree dialog box appears.

9-54
2. Leave the Clock Net Name(s) box blank or enter the clock net
names.
Note:
When the Clock Net Name(s) box is blank, the command
processes all clocks defined in SDC.
3. Select Fix.
4. Select Flip Flops Only.

9-55
Setting Special Routing Rules to Clock Nets

To have good correlation between prerouting and postrouting, you
must set special routing rules for each clock net before clock tree
synthesis (see Defining and Assigning Variable Routing Rules on
page 10-11).
Important:
If all nets in your clock tree have the same special routing rule,
define the rule for the root net, then use the
astMarkClockTree command utility to propagate the rule
downstream to all clock nets in the tree. Note that you must do
this before performing clock tree synthesis.
To propagate special routing rules in your clock trees,
2. Leave the Clock Net Name(s) box blank or enter clock net names.
3. Select Propagate Net Property.
You can propagate variable routing rules for a subset of the
expanded clock nets (partial variable routing rules). You can do this
by using two internal parameter controls after propagating the rule.
These are
axSetIntParam "act" "set default route rule on leaf net" 1

9-56
Setting this switch to 1 excludes any variable routing rule on the leaf
nets. Instead, the default width and spacing specified in the
technology file will be assumed and no shielding will be applied for
those leaf nets either. Leaf nets usually are the nets that connect to
one or more clock port. This switch is 0 by default.
For example, if you set the default route rule to 1, your variable route
rule does not apply to the leaf nets, if you set the default route rule to
0, your variable route rule does apply to the leaf nets.
axSetIntParam "acts" "set default route rule on bottom \
level" n
This rule applies to the buffer level only, not to the gate level. It
excludes any variable routing rule for the bottom n level of nets for
each gate level. The default width and spacing specified in the
technology file will be assumed, and no shielding will be applied for
the bottom n level of nets for each gate level. This switch is 0 by
default.
Sample Flow
If all nets in your clock tree have the same special routing rule and
you want to propagate the rule downstream to all the clock nets in
the tree except the leaf nets, do the following:
1. Define a variable routing rule by using the axgDefineVarRule
command.
2. Assign the variable routing rule to the root clock net by using the
axgSetNetConstraint command.
3. Propagate the rule in the clock tree by using the
astMarkClockTree command.

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4. Set the internal parameter. Enter

axSetIntParam "act" "set default route rule on leaf net" 1
5. Run clock tree synthesis (astCTS), and, optionally, run clock tree
optimization (astCTO).
6. Route the clock nets by using the axgRouteGroup command.
Deleting Clock Trees

To generate better clock trees, delete all clock trees before running
clock tree synthesis. All clock trees inserted without accurate layout
information should be deleted.
To delete all clock trees,
1. Enter the astDeleteClockTree command or choose Clock >
Utilities Delete Clock Tree.
The Delete Clock Tree dialog box appears.

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2. To delete all clock trees, leave the Root Clock Net Name(s) entry
blank. (To delete a specific clock net, specify a clock net name.)
When the Root Clock Net Name(s) box is blank, the command
deletes all buffers and an even number of inverters in the clock
trees defined in SDC.
3. Select Detect Buffer/Inverter Automatically.
You must select the Detect Buffer/Inverter Automatically option to
delete all clock trees including those inserted by other tools.
Note:
By default, this command only deletes the clock trees inserted by
Astro clock tree synthesis.
This command deletes only buffers and even numbers of inverters in
each clock tree. If you find some buffers or pairs of inverters that are
not deleted, they might be marked as fixed or dont touch or they
might be connected to dont touch nets. You can use the
astMarkClockTree command to reset those attributes and delete
them again.
Use the astClockBrowser command, as described in Viewing
Clock Structures in the Design on page 9-14, to report the clock
structure and clock summary. This command does not report these.
Warning Message for Clock Routed Designs

In earlier versions of Astro, you might not know that your design
already had clock trees inserted or that the clock trees were routed.
In this case, if you ran standard clock tree synthesis, Astro did not
account for clock trees that had been expanded and routed; most

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likely, clock tree synthesis was traced to the nets that had been
prerouted and then Astro performed the synthesis, which is not the
expected behavior.
To prevent this problem, clock tree synthesis now stops at the
specific net (providing its not the root clock net) and issues the
following warning:
CTS-Warning: no clock tree synthesis on routed net Net_Name
When you see this warning, you can remove the clock tree and its
corresponding routing before you run clock tree synthesis. This
behavior applies not only to the root clock net but also to specific nets
or partial nets that are being routed.
Removing Transition Defaults on Clocks

Transition defaults on clocks can be removed after the net is
buffered, to achieve more-accurate timing analysis.
Choosing the Clock Tree Synthesis Building Style

Consider a situation where two create_clock constraints are
defined as if one clock was derived from the other (see the following
Tcl syntax and figure).
create_clock -name {CLK1} -period 64 -waveform { 0
[list {CLK1}]
32 } \
create_clock -name {CLK2} -period 32 -waveform { 0

[list {CLK2}]
16 } \

9-60
CLK1
CLK2
Group A
Group B
In this situation, Astro clock tree synthesis can construct the clock
trees in two ways.
Up to is the default clock building style.

Clock trees for CLK1 are constructed by propagation up to CLK2.
That is, CLK1 stops propagating when it encounters another
create_clock source (CLK2). Clock tree synthesis balances
only delays to sinks in group B.
Through is the alternative clock building style.

Clock trees for CLK1 are constructed by propagating through
CLK2. That is, CLK1 traverses CLK2. Clock tree synthesis not
only balances delays to sinks within group B but it also balances
delays to sinks between group A and group B.
To use the Through style, you must specify the following Scheme
command prior to running astCTS:
define ataPropagateClockThruCreateClock 1
Depending on the building style you choose, clock latency

constraints might need to be adjusted accordingly.

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Note:
Using nested create_clock commands is not recommended.
Replace the second create_clock definition with a
create_generated_clock definition.

Astro clock tree synthesis can improve the timing performance of a
chip by carefully distributing clock signals to each synchronous pin,
using balanced multilevel clock trees based on accurate layout
information. The following diagram shows the structure of a simple
multilevel clock tree (see Figure 9-6).
Figure 9-6
Clock Tree
Clock
source
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF
Before running clock tree synthesis, make sure that
Your libraries are ready (see Preparing Library Data on

page 9-7)
Your design is ready (see Preparing Design Data on page 9-9)
Your clocks are ready (see Setting Clock Tree Synthesis

Common Options and Preparing Clocks on page 9-18)

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Using the Clock Tree Synthesis Dialog Box

To synthesize clock trees,
1. Enter astCTS or choose Clock > Clock Tree Synthesis
Clock Tree Synthesis.
2. Select the options you want in the Clock Tree Synthesis dialog
box.
procedure.
By default, Astro clock tree synthesis synthesizes clock trees under
the worst-case operating condition. Its function is to minimize global
skew under user-specified timing constraints.

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After running clock tree synthesis, you get the following results:
A buffer tree for each clock net. The driver of the buffer tree is a
preexisting cell or the clock source in your clock tree. There is no
buffer tree added to the small net if the driving strength of the
preexisting cell is strong enough.
The completed and legalized placement of buffers and/or

inverters without overlaps.
The connected power and ground for all inserted buffers and/or
inverters. There are no power and ground connections if your
design has more than one power line.
The same routing rules you defined before clock tree synthesis
on all newly created nets. When a buffer is added to a net, a new
net is created at the buffers output side. The new net inherits all
the routing rules of the original net (the input net).
Synthesizing Clock Trees in Worst and Best Cases

Simultaneously
When you select both the Worst and the Best options in the Clock
Tree Synthesis dialog box, clock tree synthesis minimizes skew in
both worst and best cases simultaneously. This new feature in Astro
clock tree synthesis takes care of both setup and hold time during
Having a clock tree with skew minimized in the worst case doesnt
guarantee minimum skew in the best case, and vice versa. Table 9-5
summarizes the results from a real design.

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Table 9-5
Clock Tree Synthesis Conditions Skew Results
Skew result
clock tree synthesis condition
Best
Worst
Best
51
182
Worst
216
116
Best and Worst
66
145
When clock tree synthesis synthesizes the clock tree in the worst
case only, it minimizes the skew in the worst case to 116, but the
skew in the best case becomes 216even larger than the skew in
the worst case. When the clock tree is synthesized in both the best
case and the worst case simultaneously, skews in both the best case
and the worst case are optimized.
Note:
When you select both best and worst cases, the runtime of
synthesis might increase.
Local Skew Clock Tree Synthesis

If you select the Local option in the Clock Tree Synthesis dialog box,
clock tree synthesis constructs clock trees by considering logic
relationships of all sequential cells and minimizes local skew for the
clock trees. For more information, see Synthesizing Clock Trees
With Local Skew on page 9-68.

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Useful Skew Clock Tree Synthesis

If you select the Useful option in the Clock Tree Synthesis dialog box,
clock tree synthesis constructs clock trees by increasing skew on
purpose to solve setup and hold time violations. For more
information, see Synthesizing Clock Trees With Useful Skew on
page 9-70.
Top-Level Clock Tree Synthesis

If you select the Top option in the Clock Tree Synthesis dialog box,
clock tree synthesis uses alternate algorithms during clock tree
synthesis and attempts to place buffers and inverters in better
alignment with the routing topology to improve delay and skew for
complex design floorplans.
For more information about the Top and other options, see
Synthesizing Clock Trees for Top-Level and Complex Designs on
page 9-72.
Exploring Clock Trees

When you want Astro clock tree synthesis to explore various clock
configurations, set the following switch. Enter
axSetIntParam "acts" "explore clock tree" 1
This command works the same in Tcl or Scheme. It is similar to the

aprCreateGCTSExplorer command in Apollo, but it does not
generate a Scheme command file. It immediately inserts the optimal
clock tree for each net. Note that this is a very time-consuming
approach.

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Multiple Clocks With Domain Overlap

In Astro, two clocks, such as clk1 and clk2, can be synthesized at the
same time, even though they have logic overlays. As a result, the
skew in the logic overlap area is minimized for both clocks if, for
example, a change during clock tree synthesis reduces the skew in
the clk1 domain from 100 ps to 95 ps but increases the skew in the
clk2 domain from 98 ps to 101 ps. Clock tree synthesis does not
make this change. Note, however, that if clk2 is not synthesized at
the same time, this change will be made.
Synthesize two clocks at the same time when you have logic overlap.
Preserving Clock Trees

After clock tree synthesis, if you want to preserve your clock skew
and clock insertion delay so that they are not disturbed by any later
changessuch as timing optimization or incremental placement
you can fix the clock trees as follows:
2. Leave the Clock Net Name(s) box blank, or enter clock net
names.
3. Select Fix and Clock Tree Only.

9-67
It is not always necessary to fix clock trees. Astro clock tree

synthesis provides a stand-alone clock tree optimization, the
astCTO command, for improving and recovering your clock skew
and clock insertion delay after they are disturbed. For more
information, see Optimizing Clock Trees on page 9-75.
Synthesizing Clock Trees With Local Skew

Local skew clock tree synthesisa new feature in Astro clock tree
synthesissynthesizes clock trees based on the logic relationships
of sequential cells extracted from the design. Its function is to
minimize local skew.
Global skew and local skew can be defined as follows:
global skew
Let sp and lp be the longest path delay and the shortest path
delay from a clock source to a clock sink. The global skew is
defined as lp sp.
local skew
Let dl and dc be the path delay from a clock source to a clock sink
of the starting point and ending point of a datapath. The local
skew is defined as dc dl.
The definitions of global skew and local skew imply that the local
skew is smaller than the global skew for a given clock tree. To meet
setup and hold constraints, it is more efficient to minimize local skew
than to minimize global skew. If the local skew is small enough that
there are no setup and hold violations, it doesnt matter how big the
global skew is.

9-68
Local skew clock tree synthesis constructs clock trees in a way that
puts the sequential cells with logic relationships under a common
subtree. As a result, the skew due to on-chip variation is minimized
by this kind of clock tree.
Before running clock tree synthesis with local skew, make sure
Your libraries are ready (see Preparing Library Data on

page 9-7)
Your design is ready (see Preparing Design Data on page 9-9)
Your clocks are ready (see Setting Clock Tree Synthesis

Common Options and Preparing Clocks on page 9-18)
Your design has datapaths between sequential cells
Note:
The last requirement is not necessary for global skew clock tree
synthesis.
To synthesize clock trees with local skew,
1. Enter the astCTS command or choose Clock > Clock Tree
Synthesis Clock Tree Synthesis.
2. Select the skew type Local.
Note:
When Astro clock tree synthesis runs in global skew mode, it
processes only the clock pathsnot the datapaths. This is the
main reason that global skew clock tree synthesis uses less
memory and runtime than local skew clock tree synthesis.

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Synthesizing Clock Trees With Useful Skew

Creating useful skew is a method of intentionally skewing a clock to
improve the timing on a circuit. The method has been performed
manually for many years on advanced designs. Astro automates it in
the place and route environment. In addition to providing timing
closure, useful skew can help improve design performance, reduce
power, increase the reliability margin, and reduce
simultaneous-switching problems.
Figure 9-7 shows a simple explanation of useful skew.
Figure 9-7
Useful Skew
Slack 1 -> 0
Slack 1 -> 0
F1
F2
2 -> 1
F3
T=5
CLOCK
5 ns
period
In this example, the clock period is 5 ns. Between the first and third
flip-flops, there are two clock periods of 10 ns. When the clock is built
with zero skew, it arrives at the flip-flops at the same time. This
constrains the first and second flip-flop path as well as the second
and third flip-flop paths to 5 ns. However, the logic between the first
and second requires only 4 ns, whereas the logic between the
9-70
second and third requires 6 ns. Therefore, the circuit fails. But if you
intentionally skew the clock by decreasing the arrival time of the
clock by 1 ns, the first part of the circuit is constrained to 4 ns and the
second part to 6 ns and the design meets timing.
In a simple test case (12K standard cells, RAM, ROM, PLL, 10
clocks, 200 MHz), the following results were achieved:
Designs with useful skew

- Critical clock period: 4.8 ns
- Global clock skew: 348 ps
Designs without useful skew

- Critical clock period: 5.15 ns
- Global clock skew: 129 ps
The clock period was improved by 350 ps with useful skew.

Meanwhile, the global skew was increased by 219 ps.
Consider the following points when deciding whether to run useful
skew clock tree synthesis: Assume that before clock tree synthesis,
you finished placement and timing optimization and got a timing
report under ideal clock. You do not need to run useful skew clock
tree synthesis if all timing violations are solved, but you should run
useful skew clock tree synthesis if some timing violations are not
solved. On the other hand, if you have many timing violations, it is not
possible to fix all the violations with useful skew clock tree synthesis,
because, as mentioned previously, useful skew clock tree synthesis
solves timing violations by pushing the negative slacks to adjacent
datapaths.

9-71
To synthesize clock trees with useful skew,

1. Enter the astCTS command or choose Clock > Clock Tree
Synthesis Clock Tree Synthesis.
2. Select the Useful option.
Note:
By selecting the Useful option, you set your design in useful skew
mode. This information is saved in the database until you reset it
with the ataPurgeDBUsefulSkew command. This mode
prevents other clock-related commands, such as clock tree
optimization, from deleting the useful delay cells inserted by
useful skew clock tree synthesis.
Synthesizing Clock Trees for Top-Level and Complex

Designs
Astro provides two algorithms for clock tree synthesis: block mode
and top mode. The top-mode algorithm is more sensitive to
blockages in your design and performs better than the block-mode
algorithm on the top-level design. If your design contains many hard
macro cells or blockages, use the top-mode algorithm; otherwise,
use the block-mode algorithm. By default, clock tree synthesis uses
the block-mode algorithm. To use the top-mode algorithm, select Top
as the Design Level option in the Clock Tree Synthesis dialog box
before synthesizing or optimizing the clock trees.

9-72
Note:
The clock tree synthesis algorithm that you select applies to all
clock trees. You cannot select the clock tree synthesis algorithm
on a per-clock basis.
Top-level clock tree synthesis performs clock tree global planning
based on the floorplan and distribution of synchronous pins before
construction of clock trees. The astCTS command Top mode
detects buffers that are placed far away from the desired location and
attempts to place the buffers in the corrected routing topology.
Note:
The astCTS command Top mode is enhanced to improve QOR
for clock tree synthesis in most designs by allowing buffer
insertion and flexible space buffer insertion. You can invoke the
previous Top mode behavior by setting the following parameter:
axSetIntParam "acts" "length fixed buffer insertion on
top" 1
Top-level clock tree synthesis takes advantage of topology-based

algorithms that are used throughout the Astro design closure flow. In
general, it detects buffers that are placed far away from the desired
location and placed the buffers along the routing tree. Optimizing the
buffer placement improves consistency with the topology recognized
by the extraction engine or by RC estimation. In addition, avoiding
placement blockages allow the Top mode to minimize insertion delay
and skew for design with complex topologies.
In the Clock Tree Synthesis dialog box (astCTS), you can select
Block or Top as a design-level option (Block is the default). Astro
clock tree synthesis can avoid blockages during clock tree insertion
for any option. Select the Top option when you have the following:

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A complex design with macros and blockages
A donut placement (sequential cells placed around blockages)
A large design (1 mm x 1 mm and above)
Low utilization (5 percent or less)
A low number of fanout pins (1,000 or less)
Sparse distribution of synchronous pins
The other settings in the Clock Tree Synthesis dialog box as well as
the settings for the Clock Common Options dialog box remain the
sameyou can follow the normal Astro clock tree synthesis flow
when performing top-level clock tree synthesis.
To synthesize clock trees with the Top option,
1. Enter astCTS or choose Clock > Clock Tree Synthesis Clock
Tree Synthesis.
2. Select Top.
Sample Flow
If special routing rules are to be used, they should be taken into
account when you insert the clock trees so that the consistency of
RC estimation and the extraction between prerouting and
postrouting is maintained. Follow these steps:
1. Set Skew Control in the Route Common Options dialog box. Use
the axgSetRouteOptions command.

9-74
2. Define a variable routing rule. Use the axgDefineVarRule

command.
3. Assign the variable routing rules to the root clock net or its
subnets. Use the axgSetNetConstraint command. The
subnets can have different rules from the root net.
4. (Optional) If the root clock net and its subnets have the same
routing rule and you have not assigned the rule to the subnets in
the previous step, propagate the rule to the subnets. Use the
astMarkClockTree command.
5. Perform top-level clock tree synthesis. Use the astCTS
command.

Clock tree optimization is an important procedure in Astro clock tree
synthesis.
Clock tree optimization has the following two modes:
Embedded modethe astCTS command. In this mode, clock

tree optimization improves both clock skew and clock insertion
delay after clock trees are inserted during clock tree synthesis.
Important:
By default, Astro clock tree synthesis runs clock tree
optimization in two iterations. If you want to change the number
of iterations, change Optimization Effort in the Clock Common
Options dialog box. Note that effort 3 and above include
sophisticated searches and require more runtime.

9-75
Stand-alone modethe astCTO command. In this mode, clock

tree optimization improves both clock skew and clock insertion
delay further with additional iterations. It can be executed at any
time. The typical usage is when timing optimization or
incremental placement disturbs your clock; you then use the
stand-alone mode to improve or recover your clocks.
It is not necessary to run the stand-alone clock tree optimization
after clock tree synthesis with embedded clock tree optimization.
If timing optimization or incremental placement disturbs your
clock skew or clock insertion delay, run the stand-alone clock tree
optimization to improve or recover your clocks.
Resetting Clock Attributes

Before optimizing clock trees, make sure the following attributes in
the clock trees are cleared:
Cell fixed
Cell dont touch
Net dont touch
To reset these attributes,

1. Enter astMarkClockTree or choose Clock > Utilities Mark
Clock Tree.

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2. Leave the Clock Net Name(s) box blank or enter clock net names.
3. Select Reset Dont Touch and click Apply.
4. Select Unfix and Clock Tree Only.
Using the Clock Tree Optimization Dialog Box

To optimize clock trees,
1. Enter the astCTO command or choose Clock > Clock Tree
Optimization Clock Tree Optimization.
The Clock Tree Optimization dialog box appears.

9-77
2. Select the optimization options you want, or keep the default

settings.
procedure.
Note:
When the design is in useful skew mode (see Synthesizing
Clock Trees With Useful Skew on page 9-70), the command
performs useful skew clock tree optimization.
Buffer Sizing
Astro clock tree synthesis constructs clock trees with a single type of
buffer for each buffer level. Different buffer levels might have different
types of buffers. The buffer sizing optimization function varies the
size of the buffers in the inserted clock trees, to improve both clock
skew and clock insertion delay.
If you want the same buffer type in each buffer level, to minimize the
skew due to on-chip variations, deselect the Buffer Sizing option in
the Clock Tree Optimization dialog box.

9-78
The buffers and inverters used in buffer sizing are the logically
equivalent cell lists extracted by the tool. However, you can use Astro
clock tree synthesis to limit some buffers and inverters in the logically
equivalent cell lists by doing the following:
Define the buffers and inverters as clock cells, using the

List the buffers and inverters in the LEQ Cells box in the Clock
For detailed information about logically equivalent cells for clock tree
optimization, see Setting Clock Tree Synthesis Common Options
and Preparing Clocks on page 9-18.
Buffer Relocation
Astro clock tree synthesis performs buffer placement with all the
features of Astro OVthe Astro placement enginesuch as
Legalized buffer location
Overlaps removal
Multiple voltages cell placement
When you select the Buffer Relocation option in the Clock Tree
Optimization dialog box, the buffer relocation optimization function
improves clock skew and clock insertion delay.
Except for considerations of runtime, there is no reason not to use
buffer relocation.

9-79
Gate Sizing
The gate sizing optimization function changes the size of preexisting
cells, as well as buffers inserted by the astCTS command, in your
clock trees to improve both clock skew and clock insertion delay.
If you do not want Astro clock tree synthesis to change the cell type
of preexisting cells, deselect the Gate Sizing option in the Clock Tree
Optimization dialog box.
The cells used in gate sizing are the logically equivalent cell lists
extracted by the tool. However, you can use Astro clock tree
synthesis to limit some cells in the logically equivalent cell lists by
doing the following:
Define the cells as clock cells, using the astSetClockCell

command.
List the cells in the LEQ Cells box in the Clock Common Options
dialog box.
For detailed information about logically equivalent cells for clock tree
Gate Relocation
If you select the Gate Relocation option in the Clock Tree
Optimization dialog box, the gate relocation optimization function
improves clock skew and clock insertion delay by physically moving
gates close to flip-flops.

9-80
By default, Gate Relocation is on, and you might experience a slight

increase in runtime and memory usage. Except for considerations of
runtime and memory usage, there is no reason not to use gate
relocation. If you do not want Astro clock tree synthesis to change
the location of preexisting cells, you can mark them as fixed.
Level Adjustment
If you select the Level Adjustment option in the Clock Tree
Optimization dialog box, the level adjustment optimization function
improves clock skew and clock insertion delay.
Note:
If the skew is improved by adjustment of a pin to its upper or lower
logically equivalent net, it means that the pin was connected to a
bad point during the clock tree construction. This might happen if
the delay estimation at the pin was incorrect. In other words, if
you find no improvement during level adjustment optimization, it
doesnt mean that this function doesnt work.
Reconfiguration
If you select the Reconfiguration option in the Clock Tree
Optimization dialog box, the reconfiguration optimization function
improves clock skew and clock insertion delay. The reconfiguration
optimization function is a reclustering function, which requires more
runtime, because buffer placement must be performed after
reclustering.
This function is deselected by default.
Important:
Select this function if you want more improvement for small clock
trees.

9-81
Delay Insertion
If you select the Delay Insertion option in the Clock Tree Optimization
dialog box, the delay insertion optimization function improves clock
skew. Delay insertion is for low-fanout nets where no clock tree is
inserted.
The delay cells used in delay insertion are buffers and inverters
extracted by the tool. It is recommended that you prepare some
delay cells in your libraries and define them as delay cells, using the
astSetDelayCell command. The priority of delay cells used in
delay insertion is as follows:
Cells entered in the Delay Cells box of the Clock Common

Options dialog box
Cells defined as delay cells by the astSetDelayCell

command

command
For detailed information about delay cells for clock tree optimization,
see Setting Clock Tree Synthesis Common Options and Preparing
Clocks on page 9-18.
Dummy Load Insertion

If you select the Dummy Load option in the Clock Tree Optimization
dialog box, the dummy load insertion optimization function improves
clock skew. Dummy load insertion is a load balance function, using
a cells input capacitance to increase loading. In most cases, a cells
input capacitance is 10 percent or less of wire capacitance.

9-82
This function is deselected by default.

The dummy cells used in dummy load insertion are buffers and
inverters extracted by the tool. The priority of dummy cells used is as
follows:
Cells entered in the Dummy Cells box in the Clock Common

Options dialog box
Cells defined as clock cell by the astSetClockCell command
For detailed information about dummy cells for clock tree

Note:
Do not use the cells with zero input capacitance as dummy load
cells. For more details about defining input capacitance, see
Preparing Library Data on page 9-7.
Balancing Interclock Delays

The interclock delay balance optimization function inserts delay cells
at the root of the clock to meet clock insertion delay requirements. If
you find timing violations due to an unbalanced clock insertion delay
in a different clock domain, set a clock delay requirement on the fast
clock and run interclock delay balance.
To balance interclock delays for preroute optimization,
1. Enter astCTOInterClocksBalance or choose Clock > Clock
Tree Optimization Inter-Clocks Delay Balancing.

9-83
The Astro: Inter-Clocks Delay Balancing dialog box appears.

If you want to set different clock insertion delay requirements for
each clock, set with the set_clock_latency Tcl command.
Note:
If you set a clock latency that is smaller than the insertion delay
calculated by the tool, astCTOInterClocksBalance does
not insert any delay cells into the clock.
Insertion delay requirements for clocks without the
set_clock_latency command are set by the value you
specify in the Phase Delay box.
If you want to balance all clocks to the insertion delay you specify
in the Phase Delay box, select Ignore SDC Latency.

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If the Ignore SDC Latency option is enabled and there is no set

clock latency defined, then the longest path delay among all
clocks is selected as the target latency for all clocks.
Optimizing Useful Skew Before Routing

Run the useful_skew_opt Tcl command, after clock trees are
synthesized and before you route the designthis command
accounts for both setup and hold time violations. You can use
useful_skew_opt after both global and useful skew clock tree
synthesis.
In Tcl mode, you can get brief descriptions of the
useful_skew_opt command options by using the help command
or -help option. For example, in the command window enter
Astro> useful_skew_opt -help
The following information is printed:

Usage:
useful_skew_opt
# Useful skew optimization
[-buffer_insertion]
(turn on buffer insertion at clock pin)
[-level_adjustment]
(turn on level adjustment at clock pin)
[-buffer_sizing]
(turn on recursive buffer sizing)
[-buffer_sizing_n_insertion]
(turn on recursive buffer sizing and insertion)
[-setup_target float] (specify setup target)
[-hold_target float]
(specify hold target)
[-report_only]
(report estimated delay only)
[-check_drc]
(turn on DRC checking)
[-opt_num integer]
(specify buffer insertion times)
[-cpu_time float]
(specify cpu time in hours)
[-low float]
(specify lower bound of slack to be optimized)
[-high float]
(specify higher bound of slack to be optimized)
[-default]
(non-batch mode buffer insertion)

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The optimization options are described in more detail as follows:
Use -buffer_insertion to fix the timing violations by

adjusting clock arrival time. Buffers for this option are inserted
only before the endpoints (the starting flip-flop and ending
flip-flop of the timing critical path). If no optimization technique is
specified, -buffer_insertion is automatically invoked under
the hood by default. Buffer selection follows the same rules as
global clock tree synthesis.
Use -level_adjustment (another optimization technique that

applies only to the starting flip-flop and ending flip-flop) to hook
up the pin to its upper or lower logically equivalent net. This
hookup will be validated if it helps improve timing.
Use -buffer_sizing to size clock buffers recursively along

the entire clock path from the root. Buffer selection follows the
same rules as global clock tree synthesis.
Use -buffer_sizing_n_insertion to combine buffer sizing

and insertion so that these processes operate on the whole clock
path recursively. Buffer selection follows the same rules as global
Use -default to perform buffer insertion nonrecursively. The

-default option must be used in conjunction with the
-buffer_insertion option. Do not use -default with
options other than -buffer_insertion.
Consider the following items when specifying useful_skew_opt

command options:
The default option is -buffer_insertion. That is,

useful_skew_opt

9-86
is equivalent to
useful_skew_opt -buffer_insertion
Any other option that you specify by itself disables the default
buffer insertion. For example,
useful_skew_opt -level_adjustment
triggers level adjustment only and not buffer insertion.
You can combine -buffer_insertion and

-level_adjustment in one run of optimization. For example,
useful_skew_opt -buffer_insertion -level_adjustment
triggers level adjustment and buffer insertion, consecutively. The

order specified makes no difference.
Specify both -buffer_sizing and

-buffer_sizing_n_insertion by themselvesthey cannot
be used with other options. Specify either
useful_skew_opt -buffer_sizing
or
useful_skew_opt -buffer_sizing_n_insertion
It is recommended that you not combine optimization techniques.

Typically, running each option separately yields better results.
You can run multiple command iterations. It is recommended that

you iterate buffer insertions until there is no more improvement
before specifying other optimization techniques.

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Combinations of multiple options and their expected behaviors are

as follows:
When you specify

useful_skew_opt -buffer_sizing
-buffer_sizing_n_insertion
the tool selects the mixed buffer sizing-and-insertion option

(-buffer_sizing_n_insertion) and ignores the recursive
buffer sizing option (-buffer_sizing).
When you specify

useful_skew_opt -buffer_insertion -buffer_sizing
the tool selects buffer insertion and ignores sizing because the
latter can only be applied alone.
When you use the useful_skew_opt Tcl command, the ideal
worst negative slack (WNS) is reported in the log. This is the upper
bound of the WNS that can be reached in an ideal environment. Here
is a sample excerpt from the log:
USK: finishes useful skew scheduling with 2 iterations and
WNS -0.321439.
Useful skew optimization generally cannot achieve the ideal WNS

due to the effects from other engines such as the overlap removal
engine; however, you should not see a large offset from the ideal
value.
As with useful skew clock tree synthesis, you can specify the target
slack for both setup and hold time with the useful_skew_opt
command by using the -setup_target and -hold_target

9-88
options. These two options can also define the effort level to be used
for setup and hold time violation fixing. The default for both setup and
hold time is 0.
If you want to relax hold time fixing, set the hold target to a very large
value (larger than any expected number of path violations). For
example, a -hold_target setting of 100 ns specifies that hold
time violations be ignored, while a -hold_target setting of 0.5 ns
specifies that the useful skew optimization engine direct more effort
toward setup time violation fixing.
Furthermore, you can use the -low and -high options to limit
optimization to pins that have slack between the [low high]
bounds. The number value specified with -low and -high refers to
setup slack (not the same as using the -setup_target option).
When you use the buffer sizing options (-buffer_sizing and
-buffer_sizing_n_insertion), a CPU runtime penalty is
expected for large designs due to the recursive approach. In this
case, you can choose to control the CPU runtime with -cpu_time,
specifying CPU time in hours.
Additional useful_skew_opt command options are described as
follows:
Use -report_only to report the following three important

parameters:
- The setup slack for a given clock pin
- The difference between the slack of the timing path
downstream and upstream for a given clock pin
- The hold time slack for a given clock pin

9-89
The Astro useful skew optimization engine uses these

parameters for internal calculation (useful for debugging
purposes).
Use -check_drc to enforce design rule checking (DRC) and

DRC violation fixing during the optimization. DRC during useful
skew optimization is turned off by default, to force the
optimization engine to function regardless of existing DRC
violationsthis keeps the optimization from being unnecessarily
disabled if the design is not DRC-clean after DRC violation fixing.
Use -opt_num to define the number of buffers to be inserted

before the leaf-cell flip-flops. This option provides a way to control
the buffer count (if the number of buffers is of concern).
Running Postrouting Clock Tree Optimization

Postrouting clock tree optimization improves both clock skew and
clock insertion delay for postrouted designs. Because it optimizes
clock trees with the real parasitic information, such as Star-RCXT
extracted parasitic view, the optimization result is your final result.
See Parasitics Page on page 6-38 for more details about the setup
of parasitic sources.
Astro integrates several advanced technologies to ensure the
correlation of prerouting and postrouting. The postrouting clock tree
optimization remains an important function for timing closure.
Consider a situation with 5 percent error in preroute in which the
longest and shortest path delays are both 3 ns and the skew is 0 ns.
In postrouting, if the longest path delay becomes 3.15 ns and the
shortest path delay becomes 2.85 ns, the skew becomes 300 ps.

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The basic requirement for postrouting clock tree optimization is to

limit changes in a local area to minimize impact to placement,
routing, and timing. Only buffer sizing and gate sizing are allowed in
postrouting clock tree optimization. By interacting with Astro OV
the Astro placement enginepostrouting clock tree optimization
detects how many cells are moved when the postrouting clock tree
optimization sizes up a cell.
To run postrouting clock tree optimization,
1. Enter the astPostRouteCTO command or choose Clock >
Clock Tree Optimization Post Route CTO.
The Post Route Clock Tree Optimization dialog box appears.
2. Select the optimization option (Buffer Sizing, Gate Sizing,

Dummy Load) you want or keep the default settings.
Running ECO Routing After Postrouting Clock Tree

Optimization
It is important to note that postrouting clock tree optimization is
automatically and immediately followed by a default ECO route after
postrouting clock tree optimization is done to reconnect the routing.

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If you want to control the ECO route settings, you can skip the
automatic ECO routing step and invoke ECO routing manually by
doing the following:
1. Prevent the automatic ECO route after postrouting clock tree
optimization by entering
define acoSkipECORoute 1
2. Perform postrouting clock tree optimization with the

astPostRouteCTO command.
3. Set the ECO routing options with the axgSetRouteOptions
command.
4. Complete the postrouting clock tree optimization flow by
manually invoking the ECO routing command
(axgECORouteDesign).
To run ECO routing,
1. Enter axgECORouteDesign or choose ECO > ECO Route >
Design ECO.
The ECO Route Design dialog box appears.

9-92
2. Set the following options:

Next to Phase, select detail and deselect global and track
assign.
Next to Dangling wires, click utilize, to minimally disturb the
layout.

9-93
For information about all the axgECORouteDesign command

options, see Physical Implementation Online Help. See also
Running ECO Routing on Detail-Routed Designs on
page 10-44.
To get routing to finish without DRC errors, you might need to click
normal next to CTS nets in the Route Common Options dialog
box. This setting allows the tool to move clock routes farther to clear
errors. However, ECO routing should be run with minor change
only selected next to CTS nets in the Route Common Options
dialog box, followed by search and repair. Prior to search and repair,
change the CTS nets routing option to normal.
Note:
You can automatically invoke ECO routing after
astPostRouteCTO by using the following command:
axSetIntParam "acts" "ECO Route" 1
Running Incremental Clock Tree Synthesis

A design might have some ECO changes (such as the deletion of
flip-flops, the addition of flip-flops, or the relocation of flip-flops). If
these ECO changes are made after routing, use ECO clock tree
synthesis instead of clock tree optimization, because clock tree
optimization might break many routed wires, change several cell
locations, or even change the netlist. ECO clock tree synthesis
considers routing costs while synthesizing and optimizing the clock
tree.

9-94
To run incremental clock tree synthesis,

1. Enter astECOCTS or choose Clock > Clock Tree Synthesis
Incremental CTS.
The ECO Clock Tree Synthesis dialog box appears.

For descriptions of the astECOCTS command options, see
3. Click OK.
Note:
The options in this dialog box are also selectable in the Clock
Common Options dialog box (Figure 9-3 on page 9-19).
Here is an example of when to use ECO clock tree synthesis:
Suppose some flip-flops are driven by a gate called clk_gate and
are connected to a net called clk_net. After clock tree synthesis, a
clock tree is inserted into clk_net. The flip-flops are driven by the
buffer generated by clock tree synthesis and are connected to the net
generated by clock tree synthesis. When you want to add more
flip-flops to the clock tree, you might not know which level they should
be connected to and what the net name generated by clock tree
synthesis is. You can add the new flip-flops to clk_net. In this case,

9-95
ECO clock tree synthesis searches for an optimal level in the clock
tree for the new flip-flops. When the flip-flops are not the spare cells,
ECO clock tree synthesis searches for an optimal location for them.
Using Interactive Clock Tree Synthesis

The Interactive CTS dialog box lets you view, cross-probe, and edit
the clock tree interactively. You can use interactive clock tree
synthesis either before or after the clock tree has been built.
To open the Interactive CTS dialog box,
Enter ctiCTS or choose Clock > Advanced Clock Tree

Management Interactive Clock Tree.
The Interactive CTS dialog box appears.

9-96
A brief description of the tabs included in the Interactive CTS dialog

box follows. For more information about how to use their options, see
Data
Use the Data page to load the clock tree data. You can then
manipulate the data interactively from the hierarchical clock tree
to the layout and the layout to the hierarchical clock tree.
Info
Use the Info page to report skew and path information by using
options to generate your report criteria, such as shortest/longest
paths, fastest/slowest top paths, clock overlap domains, and
delay information.
Under Node, you can select Phase Delay to show the phase
delay information for the ports shortest and longest path output
for each clock tree node in the order of worst condition, typical
condition, and best condition. As a result, you do not need to quit
the ctiCTS command to perform skew analysis to show the tree
nodes phase delay.
Browse
Use the Browse page to select and deselect various levels of a
clock tree, including all its child and leaf cells.
Cross-Probe
Use the Cross-Probe page to cross-probe between the physical
layout and the logical clock tree hierarchy.

9-97
Constraint
Use the Constraint page to query or set the SyncPin/ignore_tns
status for a clock pin.
ECO
Use the ECO page to perform ECO placement processes,
including adding cells before or after a specified reference node,
deleting buffers or inverter pairs, reparenting selected cells to a
designated node, and final ECO placement.
To analyze or change the clock skew report and path information,

1. Open the Interactive CTS dialog box and click the Data tab.
2. Set the following options:
- In the Clock Name box, enter your clock name.
- Under Mode, select worst case.
- Under Phase, select auto.
3. Click Load.
Data appears in the window, as shown in the following figure.

9-98
You can click Cancel to close the Interactive CTS dialog box.
To quickly display flylines for the entire tree, use the Browse page:
Click Select FFs, Select Buffers, Select Inverter Pairs, and so forth.
Then use the Cross-Probe page: Select output and click Highlight.
The entire tree appears with the levels displayed in various colors.
Analyzing Clock Tree Synthesis Results

After synthesizing and optimizing clock trees, analyze the results to
verify that they meet your requirements. Astro clock timing report
generates the following types of reports:

9-99
Transition delay at each pin in a clock tree
Arrival time to each pin in a clock tree from a clock source
Phase delay at each pin in a clock tree
Skew at each pin in a clock tree
Capacitance on each net in a clock tree
Cell delay from an input pin to an output pin and wire delay from
an output pin to an input pin
Detailed timings at each pin and net along clock paths
Note:
The phase delay at a pin is the longest and shortest path delay
from the pin to its transitive clock sink pins.
To obtain a clock timing report,
1. Enter astClockTiming or choose Clock > Reports Clock
Tree Timing.
The Clock Tree Timing Report dialog box appears.

9-100
2. Enter clock names in the Clock Names box, or leave it blank to

report all clocks.
3. Enter the file name in the File Name box, or leave it blank to
report to a window.
4. Enter the number of top values you want to see in the Report Top
box.
5. Select the type of report you want in the Transition Delay box, or
keep the default setting.
6. Select the operating condition you want, or keep the default,
Worst.
7. Select the sort order you want in your report, or keep the default,
Descending.

9-101
Analyzing Clock Skew

Use the astSkewAnalysis command to analyze global clock
skew, local clock skew, and interclock skew. This command
generates a report that lists skew information for a specified clock (or
for all the clocks within a design) before or after routing. You can view
the report in a text window or write it to a specified file.
In keeping with the ability to perform clock tree synthesis that starts
from an intermediate element of the clock tree, you can also perform
skew analysis that starts from this same point. Doing so helps to
avoid the creation of another clock at the intermediate point.
You can specify that skew for falling-edge flip-flops and rising-edge
flip-flops be reported in separate groups by using the
ataSkewAnalysisTriggerAware variable. Enter the following
Scheme command:
"define ataSkewAnalysisTriggerAware 1"
To analyze clock skew and generate skew reports,

1. Enter astSkewAnalysis or choose Clock > Reports Skew
Analysis.
The Skew Analysis dialog box appears.

9-102
2. In the Clock Names box, enter the names (root clock pin names
or net names) of the clocks for which skew information is to be
reported.
To specify that skew analysis is to start from an intermediate net
of the clock tree, enter the name of the net along with the clock
domain. For example, if you enter my_net(my_clock), the skew
analysis will start from my_net in the clock structure.

9-103
Note:
Do not use clock names with (" and ") special characters. For
example, for a clock name of (my_clock), do not use
my_net((my_clock)).
3. Select an operating condition (Worst, Typical, or Best).
4. Specify the type of clock skew to be analyzed and reported
(Global Clock Skew, Local Clock Skew, and Inter Clock Skew).
The default is to generate a global clock skew report. The global
clock skew is the maximum difference of clock arrival times
between any two flip-flops in a design.
Under Global Clock Skew, you can select one or more of the
following:
- Detailed Report Reports all pins in the clock tree, with global
skew sorted.
- Pulse Width Reports the active pulse width rather than the
required value.
- Skew Group Reports the rise and fall delays separately.
For descriptions of all the astSkewAnalysis command
The clock skew report contains the following four comparison
categories:
Unate state at the input port and the clock source are the same,
and the clock output signal is rising.

9-104
Unate state at the input port and the clock source are the same,
and the clock output signal is falling.
Unate state at the input port and the clock source are inverses,
and the clock output signal is rising.
Unate state at the input port and the clock source are inverses,
and the clock signal is falling.
Note:
When the detailed report does not contain enough information,
you can also try
astDumpClockTiming "fileName" "clockName"
See Figure 9-8 and Figure 9-9 for examples of global and local skew
reports.

9-105
Figure 9-8
Global Skew Report Example

9-106
Figure 9-9
Local Skew Report Example
The specified number of the largest-positive and smallest-negative

local skews are reported for the design. For example, you get the
worst local skew in the design reported. In that section of the local
skew report, you have all the local skews arriving at that particular
point. Then, you get the next-worst local skew and so on until the
number specified in the dialog box is reached.
Reporting Skew for Synthesized Nets

Use the astSynNetSkewReport command to report skew
information for synthesized nets in a design. A synthesized net is a
nonclock net synthesized with the astHFCTS command.

9-107
The report generated with astSynNetSkewReport is similar to the

global skew report generated with astSkewAnalysis, except that
no create_clock statement is required. Note that there is no local
skew for nonclock nets.
The astSynNetSkewReport command is net-based and does not
traverse logic gates. When using astSynNetSkewReport, you
must indicate whether or not the signal arrival time should be
synchronized with the rise, fall, or both edges in order to calculate the
skew.
To generate skew reports for synthesized nets,
1. Enter astSynNetSkewReport.
The Synthesized Net Skew Report dialog box appears.

9-108
Next to Net Name(s) From,

- Select Window to choose the nets in the design that you
specified in the Net Name(s) box.
- Select File to choose the nets from a net name file. The net
name file lists the synthesized nets and must be created
manually.
Next to Net Name(s), enter the name of the synthesized net for
which you want skew information. If you do not specify a net
name, a report is not generated.
Next to Output to, select where you want the report written
(Window or File).
Next to File Name, specify the name of the file to which you want
the report written.
Next to Operating Condition, select the library (Worst, Best, or
Typical) to be used during skew reporting.
Next to Sync Edge, select the arrival time (Rise, Fall, or both) to
be used to calculate the skew.
Synthesizing High-Fanout Nets

Astro clock tree synthesis can synthesize high-fanout nets by
inserting a balanced buffer tree for each high-fanout net. The
function of synthesizing high-fanout nets is to minimize both skew
and insertion delay. High-fanout nets can be clock nets, nonclock
nets, or mixed clock nets.
To synthesize high-fanout nets,
1. Enter the astHFCTS command.

9-109
The High Fanout Clock Tree Synthesis dialog box appears.
2. In the Net File Name box, enter the name of the file for
high-fanout nets.
Basically, the astHFCTS command performs clock tree synthesis.
Like astCTS, it uses most of the settings in the Clock Common
Options dialog box. The astHFCTS command is different from clock
tree synthesis in the following ways:
It is not necessary to define a clock with the create_clock

command for each high-fanout net, but you must provide the file
name for high-fanout nets in the Net File Name box in the High
Fanout Clock Tree Synthesis dialog box or enter high-fanout nets
in the Clock Nets box in the Clock Common Options dialog box.
By default, the command assumes that all fanout pins are

synchronized at their rising edge during skew balance. You can
change the sync edge to fall or both rise and fall.

9-110
If a fanout pin is a logic gates input pin, the command doesnt

traverse the gatethat is, the Gated Clock Tree option in the
Clock Common Options dialog box is ignored by the command.
Except for these differences, all the settings for clock tree
synthesisand the settings in the Clock Common Options dialog
box, such as the constraints and buffers to be usedare necessary
for high-fanout net synthesis. For more details on other settings, see
Setting Clock Tree Synthesis Common Options and Preparing
Clocks on page 9-18.
Note:
The astHFCTS command cannot be run on a net within a logical
hierarchy unless the net has a clock definition.
Reporting Clock Tree Power Consumption

Use the astReportClockTreePower command to report the
power consumed by the clock tree networks in the design (for each
instance and for the entire clock tree). Run clock tree analysis,
including the use of astReportClockTreePower, after the clock
tree synthesis stage of the design flow.
Preparing to use the astReportClockTreePower command
includes the following major steps:
1. Load clock definitions. Use ataLoadSDC.
2. Load power supplies. Use poLoadPowerSupply.
3. Load net switching activities. Use poLoadNetSwitchingInfo.
4. Perform clock tree power analysis. Use poPowerAnalysis.

9-111
To generate power consumption reports,

1. Enter astReportClockTreePower.
The Report Clock Tree Power dialog box appears.
2. Specify the clock net names for which power consumption is to

be reported.
Select Summary report (the default) to report the total power
consumption for the named clock trees.
3. Select whether to report the information to a named file or to a
text window.

9-112
Here is a sample clock tree power report.

**********************************************************************
*
*
Clock Tree Power Reports
*
*
Tool
: Astro
*
Version
:
*
Design
:
*
Date
:
*
Power unit : pw
*
**********************************************************************
--------------- Power Report for clock : 'CLK' --------------TOP/BLOCK1/BLOCK2/clk_gate_reg/latch: 1.98013e+07
TOP/BLOCK1/BLOCK2/clk_gate_w_addr_reg/latch: 1.79481e+07
TOP/BLOCK3/clk_gate_psr_read_bus_d_reg_0/latch: 1.45318e+07
TOP/BLOCK5/clk_gate_pipe1_addr_reg_2/latch: 1.86805e+07
TOP/BLOCK1/BLOCK2_dataio/clk_gate_din_reg_1/latch: 1.68019e+07
TOP/BLOCK4/clk_gate_mul_carry_reg_0/latch: 1.34786e+07
TOP/BLOCK1/BLOCK2_cadd/clk_gate_exec_ireg_reg/latch: 1.49513e+07
TOP/BLOCK5/clk_gate_address_d_reg_2/latch: 1.40598e+07
TOP/BLOCK8/clk_gate_mul_carry_reg/latch: 1.08906e+07
TOP/BLOCK1/BLOCK2_pcadd/clk_gate_N_mask_reg/latch: 1.37465e+07
TOP/U_BLOCK9/clk_gate_pipe1_addr_reg/latch: 1.2306e+07
TOP/BLOCK2/clk_gate_psr_read_bus_d_reg/latch: 2.01598e+07
BUFX12G1B2I1: 5.98266e+07
....
....
TOP/BLOCK1/BLOCK2_int/clk_gate_encval_reg/latch: 1.95007e+07
TOP/BLOCK4/clk_gate_address_d_reg/latch: 1.40966e+07
TOP/BLOCK1/BLOCK2_int/clk_gate_Nnopc1_reg/latch: 1.88757e+07
TOP/BLOCKA/clk_gate_wdata_in_d_reg_2/latch: 1.70004e+07
TOP/BLOCKC/clk_gate_sav_sumlow_reg_3/latch: 1.37768e+07
TOP/BLOCKD/clk_gate_sav_sumlow_reg_2/latch: 1.99888e+07
-----------------------------------------------------------------Power consumed by clock 'CLK': 1.09841e+09
---------------------------------------------------------------------Power consumed by all the specified clock(s): 1.09841e+09

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Routing Clock Nets

After you finish clock tree synthesis and fix all timing violations, start
to route your design with the Astro router. First route clock nets with
the balanced mode, then route other nets. For more information, see
Routing Groups of Nets on page 10-21.

9-114
10
Routing
10
After you place your design and run clock tree synthesis, and
optimize before and after clock tree synthesis, you are ready to route
your design. Routing includes global routing, track assignment,
detail routing, and search-and-repair.
Routing Flow
Routing Considerations
Setting Routing Common Options
Routing Groups of Nets
Setting Crosstalk Options
Performing Automatic Routing
Reducing Wire Length and Via Count
10-1
Performing Additional Routing Processes
Using Alternative Routing Commands
Using Distributed Routing
Chapter 10: Routing

10-2
Routing Flow
Routing includes the global routing, track assignment, detail routing,
and search-and-repair phases. You can run these routing phases by
using the axgAutoRoute command or by using alternative routing
commands (axgGlobalRoute, axgAssignToTracks,
axgDetailRoute, and axgSearchRepair).
The axgAutoRoute command simplifies the routing flow, and in
most cases, it is recommended that you use axgAutoRoute in
default mode, where the global routing, track assignment, detail
routing, and search-and-repair processes are run sequentially in one
step. You can use the axgAutoRoute command or the alternative
commands to customize the design flow. For example, you might
want to run optimization after track assignment, or break up the flow
for designs with long runtime.
The axgAutoRoute command is described in Performing
Automatic Routing on page 10-25. The axgGlobalRoute,
axgAssignToTracks, axgDetailRoute, and
axgSearchRepair commands are described in Using Alternative
Routing Commands on page 10-46.
After routing is completed, you can run wire length and via
optimization by using the axgRoutOpt command, as described in
Reducing Wire Length and Via Count on page 10-38.
Optimizations for global routing, track assignment, and detail routing
are described in Chapter 11, Postrouting Optimization.
Astro optimizes memory usage during routing by splitting
timing-driven global routing jobs and timing-driven track assignment
jobs into a router process and a timer process, under the following
conditions: when the job is run on a 32-bit machine and the number
Routing Flow
10-3
of nets, plus the number of cell instances, in the design is greater

than 500K. This lets you route a large design on a 32-bit machine as
long as the memory usage of each process is less than the
maximum process size (usually between 2 GB and 4 GB).
Note:
The peak memory usage during routing (global routing, track
assignment, detail routing, and search-and-repair) can be
reduced up to 20 percent. To get this benefit (usually on huge
designs), the CEL view must be saved, closed, and reopened
before you run the command for the next routing phase.
Astro provides a distributed routing feature, which runs Astro in
parallel on different CPUs and machines. For more information, see
Using Distributed Routing on page 10-52.
The flow for routing is shown in Figure 10-1.
Chapter 10: Routing

10-4
Figure 10-1 Routing Flow

From placement, optimization, and
clock tree synthesis
Set routing common options

axgSetRouteOptions
Route groups of nets

(clocks, special nets, and so forth)
axgRouteGroup
Perform global routing,

track assignment,
detail routing, and
search-and-repair
axgAutoRoute
Reduce wire length and via count

axgRoutOpt
To postrouting optimization
Following are points for you to consider and data to prepare before
you run the commands to route your design.
10-5
Checking the Design Before Routing

Use the axgCheckDesignForRoute command to check your
design and generate an error cell from which you can view errors,
enabling you to find problem areas in your design before you perform
routing. To view the errors, load the error cell with the
geErrorBrowser command (see Using the Error Browser on
page 13-9). You can also see pin access statistics and error
messages, as listed in the log file.
The axgCheckDesignForRoute command checks various areas
of your design, such as pin access points, cell-instance wire tracks,
pins out of bounds, minimum grids, and pin design rules and
blockages. Run this command after the placement stage of the
design flow and before detail routing.
To check the design and generate an error cell,
1. Enter axgCheckDesignForRoute or choose Route Setup >
Check Design for Routing.
The Router Check Design dialog box appears.
2. Enter the name of the error cell to be generated or keep the

default name (cell_name.err). An error cell is not generated
unless errors exist.
Chapter 10: Routing

10-6
Preroutes
When a wire is prerouted, Astro checks to see whether it is
completely connected. If the net is completely connected, Astro
treats the net as a blockage; if the net is partially connected, Astro
connects all parts of the net. Keep in mind that
Astro treats power and ground nets as blockages.
Astro treats prerouted meshes and trunks as a single connection.

Make sure you examine the routing to see whether they are
connected properly.
Net-Based Routing Rule Tables

You can correlate virtual routing to global routing and timing analysis
after course placement by using a net-based routing rule table,
which can be used during layout parasitic extraction. You use the
ekGenNetRoutingRuleTabInfo command to generate a
net-based routing rule table. The net-based routing rule table
contains routing information that includes layers used and via
counts. The table is stored as a cell attach file.
The net-based routing rule table for a given cell is generated from
another cell that has global or detail routing objects and is sharing
the same net list. The table contains two types of information per
netone for metal distribution per layer and one for via distribution
per layer, as well as via count.
The net-based routing rule table information is used during virtual
capacitance and resistance extraction. Prior to extraction, you use
the define ekUseNetRoutingRuleTabGenByGR 1 command to
use the table during extraction. Capacitance and resistance are
calculated according to the metal distribution over layers.
10-7
The net-based routing rule table can be removed from the current
cell by using the ekDeleteNetRoutingRuleTabInfo command,
and you can write the table to an ASCII file by using the
ekDumpNetRoutingRuleTabInfo command. For more
information about the net-based routing rule table commands, see
Removing Filler Cells

Astro does not automatically remove filler cells (needed to fit new
cells or move existing ones). If you try to run global routing and
postrouting optimizations with filler cells, the tool will issue an error
message similar to the following:
ERROR: Cannot place filler cell instances (e.g.
xofiller!feedth9!23784). Purge them or fix them first.
***************************************
* Thu Jul 11 20:54:56 2002
* Overlap Removal(OV) Engine Terminated
***************************************
ERROR : pdsPushParams() failed --- parameter stack empty
If filler cells contain power ground rails on metal layers only, it is

sufficient to delete them once and then add them back after all
optimizations. In this case, standard cell pin connect covers the rails
and the same metal is left in the design for the router to see. If this is
not the case, the best flow is to delete filler cells prior to the
optimization step, run the optimization, add them back, and run
search-and-repair routing with update design rule check on.
Chapter 10: Routing

10-8
Adjusting Metal Costs

By default, Astro typically routes more wires on the upper layers of
your design. If you want to influence which layers are used, you can
adjust the routing costs, by using axSetIntParam command
syntax. For example, to add additional routing cost to layer metal6,
the syntax is
(axSetIntParam "route" "m6ExtraCost" 0)
;;
range [0,20], default=0;
;;
N: additional routing cost for metal6
Set routing costs prior to running global routing and track

assignment. The costs you specify are active only in the session in
which it is loaded. Track assignment has the biggest impact on the
final routing layer.
Generally, the best routability is achieved by use of the defaults.
Adjusting the costs to use more upper layers (to use layers with more
desirable properties) might make some designs unroutable. Adjust
the parameters only after you have gotten a trial pass to route clean
or almost clean.
Note:
Do not use the following routing parameter setting:
axSetIntParam "route" "layerExtraCostByRC" 2
Although this parameter works on designs that use a process

with very high-resistance vias or with very different pitch/width/
RC for different layers, it makes designs unroutable in many
cases.
10-9
Controlling Routing Layers

Use the axgAddRouteGuide command to prohibit routing (signal
or preroutes in both) on named layers in a specific area by creating
routing guides or routing blockages.
To create routing guides or blockages,
1. Enter axgAddRouteGuide or choose Route Setup > Route
Guide Create Route Guide.
The Add Route Guide dialog box appears.
Chapter 10: Routing

10-10
- Select the options or keep defaults.

For descriptions of all the axgAddRouteGuide command
- Click Hide.
2. Create a rectangular routing area, in which routing is prohibited
for the specified routing types on the specified layers, by dragging
the pointer diagonally and clicking to finish.
Defining and Assigning Variable Routing Rules

Define variable routing rules such as width, spacing, and contact
rules, and then assign them to one or more nets, before you begin
routing. Use the axgDefineVarRule and
axgSetNetConstraint commands, respectively.
Note:
You can also define shielding rules, generally for clock nets, with
axgDefineVarRule (useful for estimating shielding wire
capacitance without real shielding wires during clock tree
synthesis).
10-11
Table 10-1 shows the commands you can use to set, edit, and get
information about variable routing rules for specific nets.
Table 10-1 Commands Pertaining to Variable Routing Rules
Task
Command
Specify the following variable routing

rules:
axgDefineVarRule or
dbDefineVarRouteRule
Minimum width of objects on a layer

Minimum spacing between objects on
a layer
Size of array to use with a contact on a
layer
Minimum shield width and spacing on
a layer
Assign a set of variable routing rules to
one or more nets
axgSetNetConstraint (using the
VarRoute Rule option) or

dbAssignVarRouteRule
Write a cells variable routing rules to a file
dbDumpAllVarRouteRules
Delete all variable routing rules in the

specified cell
dbDeleteAllVarRouteRules
Set constraints of variable routing rules,

including layer, timing, spacing, or layer
property for nets
axgSetNetConstraint
Highlight objects on a net to be queried by

a specified name
geQueryNetConstraint
You should specify variable routing rules for the root clock net in your
design before running clock tree synthesis. Clock tree synthesis
propagates the rules attached to the parent net to all the daughter
nets created during clock tree synthesis or clock tree optimization.
Alternatively, clock tree synthesis produces a file of nets for the nets
it creates (the default file name is net.acts). You can use this file to
determine which nets are part of the clock network. Make sure you
Chapter 10: Routing

10-12
rename the net.acts file before subsequent runs of the astCTS

command. These files are useful both when setting rules and when
routing groups of clock nets.
Note:
When clock tree synthesis or clock tree optimization and
interactive operations are done, you can write a file by using the
ataDumpClockNets command (useful for setting variable
routing rules).
Defining Variable Routing Rules

To define variable routing rules,
1. Enter axgDefineVarRule or choose Route Setup >
Constraints Define Var Route Rule.
The Define VarRoute Rule dialog box appears.
10-13
2. Next to Rule Name, enter the name you want for the set of rules
you are defining.
After you enter the rule name, you can click Get to update all the
data boxes.
3. For shielding,
- Select Shield associated nets to apply shielding width and
spacing rules for nets assigned this variable routing rule.
Chapter 10: Routing

10-14
- Select Snap shielding wires to track to force shielding wires

on the nearest wire tracks.
4. Set the rule values or keep default settings (the default width and
spacing values are the width and spacing specified in the
technology file).
For shielding, you can specify the wire width of the shielding
wires and the spacing allowed between shielding wires and the
signal or clock wires to be shielded.
You can click Query to open a window that lists the rules defined
with axgDefineVarRule. To display a set of rules, click the rule
name in the list.
Assigning Variable Routing Rules

You can use the axgSetNetConstraint command to assign
variable routing rules to nets.
To assign variable routing rules to one or more nets,
1. Enter axgSetNetConstraint or choose Route Setup >
Constraints Set Net Constraint.
The Set Net Constraint dialog appears (see the figure in the next
section, Setting Net Constraints on page 10-16).
2. Next to Net Name, enter the name of the net(s) for which you are
assigning variable routing rules.
3. Under Assign, select VarRoute Rule and enter the name of the
rule to be assigned to the specified nets.
10-15
Setting Net Constraints

Use the axgSetNetConstraint command to set layer,
timing-driven spacing, and top-layer probe constraints for nets.
To set constraints for one or more nets,
1. Enter axgSetNetConstraint or choose Route Setup >
Constraints Set Net Constraint.
The Set Net Constraint dialog box appears.
2. Next to Net Name, enter the name of the nets for which you are
assigning variable routing rules.
Chapter 10: Routing

10-16
3. Under Assign,
- Select MinMax Layer and enter a number that corresponds to
the minimum layer and maximum layer constraint you want to
assign to the named nets. When you click the small box to the
right of the data entry boxes, the Edit Layer Panel dialog box
appears, from which you can select a layer number.
- Select Timing-Driven Spacing to assign timing-driven spacing
controls to the named nets. This means that when crosstalk
problems occur around a named net or the intra-layer coupling
capacitance of the net is too high, Astro moves the net away
from other nets and avoids placing long, parallel wires next to
the net.
- Select Top Layer Probe to assign top-metal-layer routing
constraints to the named nets so that the top-layer segment of
the nets can be used for probing purposes.
You can choose the following:
- AnyPort (the default) to specify that a net needs to reach the
top layer only once and that location does not matter (for signal
probing only).
- Outport to specify that only the output pin on a net needs to
reach the top layer (useful for disconnecting the driving pin of
a net).
- AllPort to specify that every pin on a net needs to reach the top
layer (useful for disconnecting any pin from the net).
10-17
Deep Submicron Design Rule Support

For information about the routing design rules that Astro supports for
advanced technologies, see Appendix C, Routing Design Rules.

Before you begin routing, use the axgSetRouteOptions
command to set the routing common options for your design. The
routing options affect all routing-related commands.
Note:
The crosstalk prevention options for global routing and track
assignment that were available in the Crosstalk Route Options
dialog box (axgSetXtalkRouteOptions) were moved to the
Route Common Options dialog box. For more information, see
Assignment on page 15-11.
To set the common routing options for your design,
1. Enter axgSetRouteOptions or choose Route Setup > Route
Common Options.
The Route Common Options dialog box appears.
Chapter 10: Routing

10-18
Figure 10-2 Route Common Options Dialog Box
2. Select the options or keep defaults, depending on your

requirements.

10-19
These options control various aspects of global routing, track

assignment, and detail routing, as well as design rule checking
and poly pin connections (when poly pins are part of your cell
libraries).
Several of the controls are briefly described here; others are
described throughout this chapter and subsequent chapters with
the tasks for which they need to be set. For descriptions of all the
axgSetRouteOptions command options, see Physical
- To enable crosstalk prevention during global routing and track
assignment, select Crosstalk Prevention.
For information, see Crosstalk Prevention During Global
Routing and Track Assignment on page 15-11.
- To enable timing-driven routing, select Timing Driven under
Global Routing, Track Assign, and Detail Routing.
For global routing and track assignment, enter a number in the
weight box to indicate the importance of timing relative to the
wire length. The larger the value, the more Astro tries to meet
timing constraints by reducing wire length. The largest value
you can enter for global routing is 7 and the largest value for
track assignment is 10.
- To enable skew control, select Skew Control and enter a
number in the weight box.
Skew control applies to signal nets but not necessarily to all
signal nets. For example, Astro does not do skew control when
a net is small. It also does not do skew control when the aspect
ratio is such that the pins are almost collinear. You can control
the size of net and aspect ratio thresholds before running
global routing.
Chapter 10: Routing

10-20
Skew control increases the wire length slightly but should not
significantly affect the routability of your design.
It is recommended that you enable skew control when you
don't want to do timing-driven global routing (skew control has
an indirect effect on timing).
Note that skew control for clock nets occurs only when the
balanced clock routing style is enabled (the default is on).
- To enable incremental global routing, select Incremental
(under Global Routing).
Astro uses the global routes already created for nets during an
earlier global routing run as a guide to maintain similar
patterns. For more information, see Running Incremental
Global Routing on page 10-32.

Use the axgRouteGroup command to route specified nets as a
group. This can be useful for discovering timing problemsfor
example, you can route clock and bus pins to prerouted clock and
bus wires and then perform timing analysis on these nets. If the
timing results are satisfactory, you can route the remaining nets by
using the axgAutoRoute command or the individual global routing,
track assignment, and detail routing commands described later in
the routing flow.

10-21
Routing Clock Nets

Its important to route critical clocks nets before routing other signal
nets so that the clock nets have the most-direct routing.
Preparing to Route Clock Nets

Before routing clock nets with axgRouteGroup, open the Route
Common Options dialog box (axgSetRouteOptions) and select
Skew Control and set a weight; and then select balanced (next to
Clock Routing). This dialog box is shown in Figure 10-2 on
page 10-19.
Defining Pseudo Pins

You can define a pseudo clock pin that provides a seed for
balanced-clock routing. You use the axgLoadPseudoPinConstr
command to define the location of a pseudo pin on a clock net by
specifying its x-, y-coordinates.
The syntax is
axgLoadPseudoPinConstr "filename"
where filename is a text file in which net names are listed on a

separate line along with the x-, y-coordinates of the pseudo pin for
that net. For example,
netName1 Xlocation Ylocation
netName2 Xlocation Ylocation
Make sure the location of the pseudo pins is accessible to the router.
Do not specify coordinates that are located in blockage areas. The
coordinates are in user-defined units.
Chapter 10: Routing

10-22
When you define a pseudo pin and select balanced (next to Clock
Routing) in the Route Common Options dialog box, Astro treats the
pseudo pin as the driving pin of the net. The router connects all input
pins to the pseudo pin in a balanced style and then makes a direct
connection from the pseudo pin to the actual driver. The routing
conforms to wire-to-wire and via rules, variable routing rules, and
layer and cost controls. (The Route Common Options dialog box is
shown in Figure 10-2 on page 10-19.)
You can generate a report for all the nets with pseudo pin constraints
by using the axgDumpPseudoPinConstr command. The syntax is
axgDumpPseudoPinConstr "filename"
To ensure that the clock net pattern is maintained during detail

routing, select minor change only (next to CTS nets) in the Route
Common Options dialog box before you perform detail routing.
Using axgRouteGroup
To route a group of nets,
1. Enter axgRouteGroup or choose Route > Route Net Group.
The Route Net Group dialog box appears.

10-23
2. Select the options or keep defaults. To specify what nets are to

be routed, you can
- Select Window to route named nets from the design. You must
enter the net names in the Net Name(s) box.
- Select File to route named nets from a file. You must enter the
name of the file in the File Name box.
- Select All clock nets to route the clock nets.
- Route a named bus by entering its name in the Bus Name box.
For descriptions of all the axgRouteGroup command options,
Chapter 10: Routing

10-24

For information about the flow for preventing, analyzing, and fixing
crosstalk, see Chapter 15, Signal Integrity: Crosstalk Prevention,
Analysis, and Fixing.

The axgAutoRoute command combines the axgGlobalRoute,
axgAssignToTracks, axgDetailRoute, and
axgSearchRepair commands. The recommended flow is to use
axgAutoRoute to sequentially run global routing, track assignment,
detail routing, and search-and-repair in one step, followed by
astPostRouteOpt to optimize your detail-routed design. If you
cannot close timing with the recommended flow, you can try a
variation, where one or more routing processes (done with
axgAutoRoute) might be followed by the appropriate optimization
processes (done with astPostRouteOpt). For information about
using astPostRouteOpt, see Performing Postrouting
Keep in mind that global routing is divided into the following phases:
One initial routing phase, where all the unconnected nets are
routed
One or more rip-up and reroute phases, where for a selected set
of nets, the routing results from the previous phase are deleted
and nets are rerouted to reduce the congestion

10-25
To run global routing, track assignment, detail routing, and

search-and-repair,
1. Enter axgAutoRoute or choose Route > Auto Route
The Auto Route dialog box appears, as shown in Figure 10-3.
Figure 10-3 Auto Route Dialog Box
2. Make sure the global, track assign, and detail phases are all
selected. The default is all three.
For details about these phases, see
- Global Routing on page 10-27.
- Track Assignment on page 10-33.
- Detail Routing on page 10-36.
3. Next to Search Repair Loop, enter the number of times to perform
incremental search-and-repair. (You can disable
search-and-repair by entering 0.)
4. Specify the global routing speed by selecting one of the following:
- prototype, which runs only initial global routing
Chapter 10: Routing

10-26
- fast, which runs initial global routing and one rerouting pass
- medium, which runs initial global routing and four rerouting
passes (this is the default)
- slow, which runs initial global routing and eight rerouting
passes
5. Next to Save After Phase, select one or more options (global,
track assign, detail) to specify that the design be saved after the
global routing, track assignment, and detail routing phases.
6. Select Distributed Routing to use the distributed routing feature.
Your network must be properly setup before running this option
(see Using Distributed Routing on page 10-52). Also, enter the
number of CPUs that Astro can use (a value of 0 or 1 disables
distributed routing and Astro uses a single CPU).
Global Routing
Global routing maps general pathways through the design for each
unrouted net (signal nets and clock nets). The global router uses a
two-dimensional array of global routing cells to model the demand
and capacity of global routing. Astro uses the average height of the
standard cells to create the height and width of each global routing
cell.
During global routing, Astro assigns nets to the global routing cells
through which they pass. For each global routing cell, the routing
capacity is calculated according to the blockages, pins, and routing
tracks inside the cell. Although the nets are note assigned to the
actual wire tracks during global routing, the number of nets assigned
to each global routing cell is noted. Astro calculates the demand for

10-27
wire tracks in each global routing cell and reports the overflows,
which are the number of wire tracks still needed after Astro assigns
nets to the available wire tracks in a global routing cell.
Astro might reduce overflows by detouring nets around congested
areas and increasing the wire length. You can examine the global
routing report that appears in the command window and display
congestion maps to help you decide whether your design can be
routed. See also Displaying Global Routing Congestion Maps on
page 10-30.
The global router considers spacing and wide-wire variable routing
rules, as well as shielding variable routing rules, when calculating
congestion.
Specifying Density-Driven Global Routing

You can run global routing in density-driven mode to make the
density more uniform in your design, potentially providing better yield
during the manufacturing process without impact on the overall
timing. To use this mode, enable the densityDriven parameter by
entering the following syntax:
axSetIntParam "groute" "densityDriven" 1
RC Layer Optimization in Global Routing

The overall timing quality is improved when the longest nets in the
design are routed on the metal layers with the least RC. If the
estimated RC value of the upper metal layers is less than that of the
lower layers, the timing-critical and longer nets will be biased to be
routed on the upper layers. There should be at least two upper layers
with lower RC for the RC optimization-by-net-length mode to be
triggered. The RC optimization-by-net-length mode is always
triggered in timing-driven global routing.
Chapter 10: Routing
10-28
To use this mode for nontiming-driven global routing, enable the

rcOptByLength runtime parameter by entering the following
syntax:
axSetIntParam "groute" "rcOptByLength" 1
The design should have the delay tables that are needed to calculate
the estimated RC. If no delay tables exist, you need to set extra cost
for all layers. While in the RC optimization-by-net-length mode for
nontiming-driven global routing, Astro interprets these settings as
the estimated RC value for each layer. If you do not set extra cost for
layers and the design does not have any delay tables, the RC
optimization-by-net-length mode is not triggered.
To specify that the RC optimization-by-net-length mode not be
triggered, enable the ignoreRCOptByLength parameter by
entering the following syntax:
axSetIntParam "groute" "ignoreRCOptByLength" 1
Specifying a No Buffer Zone

If the global router creates global routes over a large placement
blockage or hard macro, post-global routing optimization cannot
insert buffers along the route that might be needed to fix timing
violations. A maximum capacitance value is internally determined
during postplacement optimization phase 1. This value is used by
the global router, and patterns are created that help post-global
routing optimization. You can also set the maximum capacitance
value by running the astGRInitBlockedCapLimit command.
This setting, in conjunction with post-global routing optimization,
improves the overall timing of the design.

10-29
Performing Global Routing

You perform global routing by running the axgAutoRoute
command. By default, global routing, track assignment, and detail
routing are all selected. If you want to run global routing only, select
the global phase in the Auto Route dialog box (Figure 10-3 on
page 10-26) and make sure to deselect track assign and detail.
Also, select a global routing speed (the default is medium), and
choose whether to save the design after the global routing is done.
Alternatively, you can perform global routing with the
axgGlobalRoute command, as described in Global Routing on
page 10-46.
When you perform global routing with astAutoRoute or
axgGlobalRoute, any previously created global routing is deleted.
Displaying Global Routing Congestion Maps

After global routing, Astro calculates routing congestion and displays
a one-dimensional or two-dimensional congestion map. Use the
congestion maps to examine the areas where wire track demand
exceeds supply. See also About Congestion Maps on page 8-28.
To display a global routing congestion map,
1. Enter axgDisplayGRCongestionMap or choose Route >
Global Route Display Congestion Map.
The Routing Congestion Map dialog box appears.
Chapter 10: Routing

10-30
2. Select the options or keep defaults. (The visibility display defaults

are 1-D, 2-D, and text.)
- 1-D Displays a one-dimensional congestion map that
consists of bars at the bottom and left edges of the design. The
red areas of the display indicate areas of the design where
routing resources are insufficient because of excessive
congestion. To view the specific areas causing the congestion,
display a two-dimensional congestion map.
- 2-D Displays a two-dimensional congestion map that
consists of a grid of global routing cells, with colors indicating
the utilization of wire tracks through each edge of each global
routing cell.
- text Displays numbers to indicate how many tracks are used
along each horizontal and vertical section of the 1-D map, as
well as numbers to indicate the demand or supply of tracks

10-31
intersecting the edges of each global routing cell of the 2-D

map. For example, 6/5 means six wire tracks are needed but
only five wire tracks are available.
For descriptions of all the axgDisplayGRCongestionMap
To disable the display of a congestion map, click Clear.
Optimizing After Global Routing

You can perform optimizations after global routing, using the
astPostRouteOpt command. For information, see Global
Routing Optimization on page 11-13.
Running Incremental Global Routing

You can enable incremental global routing by selecting Incremental
(under Global Routing) in the Route Common Options dialog box
(axgSetRouteOptions). When you select this option, post-global
routing optimization (astPostGR) calls the incremental global
routing process.
Alternatively, you can enable incremental global routing by entering
the following syntax:
axSetIntParam "groute" "incremental" 1
Incremental global routing uses the global routes already created for
nets during an earlier global routing run as a guide to maintain
similar patterns. If a new net is created because of netlist changes,
the global routing pattern of the parent net is used to route the new
net.
Chapter 10: Routing

10-32
You can specify the threshold (percentage of modified nets) at which

incremental global routing is triggered, using the
brokenNetsThreholdPercent parameter. For example, to
trigger incremental global routing when less than 25 percent of the
nets in your design are modified, enter
axSetIntParam "groute" "brokenNetsThresholdPercent" 25
The percentage value is > 0 to 100; a value of 1 (the default) means

that Astro automatically calculates the optimum percentage.
Astro performs incremental global routing automatically during
post-global routing optimization (astPostRouteOpt "GR"). You
can disable incremental global routing by selecting Skip ECO
Routing (under Flow Control) in the Post Route Optimization dialog
box. See also Global Routing Optimization on page 11-13.
Track Assignment
Before running the detail router, run track assignment to specify
which tracks within each global routing cell are to be used for each
net. Track assignment operates on the entire design at once; it can
make long routes straight and reduce the number of vias, whereas
the detail router routes a small area at a time. Track assignment
accounts for large vias that need more tracks than the wire to which
they are connected.
After track assignment finishes, all nets are routed, but not very
carefully. There are many violations, particularly where the routing
connects to pins. The detail router works to correct the violations.

10-33
Specifying Density-Driven Track Assignment

You can run track assignment in density-driven mode. In this mode,
track assignment spreads wires so that metal wires are distributed
more uniformly, potentially providing better yield during the
manufacturing process without impact on the overall timing, as well
as improving the designs routability and reducing crosstalk noise. To
use this mode, enable the densityDriven parameter by entering
axSetIntParam "trackAssign" "densityDriven" 1
Limiting Net Layer Length to Prevent Floating

Antennas
If your design has floating antenna issues, you might want wires on
certain layers to not exceed a certain length. You can specify net
layer length constraints and specify that track assignment follow
these constraints by setting parameters that are described in this
section. For information about floating antennas, see Checking and
Fixing Floating Wire Antennas on page 14-11.
For special nets with their own set of constraints, put the net layer
length information in a file named trackAssignNetLLL.file. Here is a
sample file:
NetA
NetB
NetC
M1 300000 M3 200000
M1 250000 M2 280000 M3 300000
M2 300000
where NetA is the net name, M1 is the layer name in the technology
file, and 300000 is the length limit in the user unit. Each net must
have its own line in the trackAssignNetLLL.file.
Chapter 10: Routing

10-34
To instruct the track assignment process that there is an input

trackAssignNetLLL.file to be read, enable the
netLayerLengthLimit parameter.
Enter
axSetIntParam "trackAssign" "netLayerLengthLimit" 1
For all the nets in the design that need layer length limits, except the
ones described in the trackAssignNetLLL.file, set parameters, as
shown in the following sample commands:
axSetIntParam "trackAssign" "m0LayerLengthLimit" 200000
.
.
.
Performing Track Assignment

You perform track assignment by running the axgAutoRoute
routing are all selected. If you want to run track assignment only,
select the track assign phase in the Auto Route dialog box
(Figure 10-3 on page 10-26) and make sure to deselect global and
detail. Also, choose whether you want to save the design after the
track assignment is done. Alternatively, you can perform track
assignment with the axgAssignToTracks command, as described
in Track Assignment on page 10-48.
Optimizing After Track Assignment

You can perform optimizations after track assignment, using the
astPostRouteOpt command. For information, see Track
Assignment Optimization on page 11-14.

10-35
Detail Routing
Detail routing uses the general pathways suggested by the global
routing and track assignment processes to route the nets (paths and
contacts).
Performing Detail Routing

You perform detail routing by running the axgAutoRoute
routing are all selected. If you want to run detail routing only, select
the detail phase in the Auto Route dialog box (Figure 10-3 on
page 10-26) and make sure to deselect global and track assign.
Also, choose whether you want to save the design after the detail
routing is done. Alternatively, you can perform detail routing with the
axgDetailRoute command, as described in Detail Routing on
page 10-48.
Handling Misaligned Tracks and Off-Grid Pins

During detail routing, in an effort to speed up the routing time, Astro
automatically enables a turbo mode when it finds misaligned tracks
between layers. However, If your design has a high number of
off-grid pins, you might want to disable the turbo mode so that the
off-grid pins can be connected with unified grids. To disable the turbo
mode, set the noOffGridRouting parameter to -1. The syntax is
axSetIntParam "droute" "noOffGridRouting" -1
;; Range: [-1,3], Default = 0;
;; -1: Disable turbo mode, so all unified grids can be used
;; for routing
For a design with off-grid pins, you can set the maxOffGridTrack
parameter to help resolve DRC violations as they are worked on
during detail routing with search-and-repair. You can manually cycle
Chapter 10: Routing
10-36
through the maxOffGridTrack parameter values (0 to 4), or you

can specify that the different values be automatically cycled by
setting maxOffGridTrack to -1. The syntax is
axSetIntParam "droute" "maxOffGridTrack" -1
;; Range [-1, 4], Default = 0
;; -1: Combination of 0 - 4
Optimizing After Detail Routing

You can perform optimizations after detail routing, using the
astPostRouteOpt command. For information, see Detail Routing
Search-and-Repair
After the detail routing phase, you can run incremental
search-and-repair routing passes. During these routing passes,
Astro searches for DRC violations and reroutes wires in an effort to
avoid violations. The Astro router does not add metal stubs on frozen
nets to fix DRC violations even when the nets have DRC violations.
You can perform search-and-repair by running the axgAutoRoute
command in detail routing mode. Simply select the detail phase in
the Auto Route dialog box (Figure 10-3 on page 10-26) and enter the
number of times to perform incremental search-and-repair.
Alternatively, you can perform search-and-repair with the
axgSearchRepair command, as described in
Search-and-Repair on page 10-50.

10-37
Reducing Wire Length and Via Count

After detail routing, use the axgRoutOpt command to reduce wire
length and the number of vias in your design. This command should
have to be run only once. It can produce long runtimefor
information about setting a runtime limit, see step 2 in the following
procedure.
To reduce wire length and via count,
1. Enter axgRoutOpt or choose Route > Detail Route Detail
Route Wirelength Optimization.
The Routing Optimization dialog box appears.

- Next to Search & Repair Loop, enter the number of times to
perform incremental search-and-repair. If you do not want to
run search-and-repair, enter 0.
- Next to Run Time Limit (min), enter the number of minutes for
the routing optimization to be performed. A value of 1 (the
default) means no limitation.
Chapter 10: Routing

10-38
- Select Distributed Routing to use the distributed routing

feature. Your network must be properly setup before running
this option (see Using Distributed Routing on page 10-52).
Also, enter the number of CPUs that Astro can use (a value of
0 or 1 disables distributed routing and Astro uses a single
CPU).

You can run additional routing processes, as described in the
following sections.
Removing Unnecessary Stubs

You can free up routing resources and provide cleaner routing by
removing unnecessary stubs. To enable this feature, enter the
following syntax:
axSetIntParam "droute" "removeObsoleteStub" 1
Filling Notches and Gaps

It is recommended that you perform notch and gap filling during the
search-and-repair process. This enables the router to correct DRC
violations as it fills notches and gaps, including violations for 90-nm
rules. First, make sure you set the following options in the Route
Common Options dialog box (axgSetRouteOptions):

10-39
Next to Same Net Notch, deselect ignore.

(When this option is selected, the router ignores same-net notch
violations.)
Next to Same Net Notch, select check and fix.
These options instruct the router to fix same-net notch violations

during the search-and-repair process.
Alternatively, you can specify that metal wire be used to fill notch or
minimum edge violations by entering the following syntax:
axSetIntParam "droute" "fillNotch" 1
You can also use geNewFillNG command to fill notches and gaps,
but this command does not check 90-nm rules. To use
geNewFillNG, make sure ignore, next to Same Net Notch, is
deselected in the Route Common Options dialog box. The
geNewFillNG command fills notches and gaps that are smaller
than the minimum distance allowed between objects of the same net
on the same layer. It generates notch-and-gap-filling information that
is stored in the FILL view cell and can be used when you translate
your design data to GDSII format with the auStreamOut command
(with fill options selected).
For descriptions of the geNewFillNG command options, see
Shielding Nets
You can shield routed nets with axgAutoShieldRoute or by using
the Shield Net option in the Quick Signal Route dialog box
(axgQuickSignalRoute). Because these commands only
generate shielding wires that do not cause DRC violations, whenever
Chapter 10: Routing
10-40
there might be DRC violations, the target net might not be shielded.
The router attempts to drop as many contacts as possible between
the shielding wires and power and ground preroutes. Shielding is
added after detail routing is performed.
The axgAutoShieldRoute command uses shielding rules defined
with axgDefineVarRule (see Defining Variable Routing Rules on
page 10-13); whereas, the shielding option for quick signal routing
uses default spacing rules. Use axgAutoShieldRoute because
you get the benefit of Astro honoring the shielding rules during clock
tree synthesis.
Shielding With Rules Defined As Variable Routing

Rules
To shield nets with rules defined as variable routing rules,
1. Enter axgAutoShieldRoute or choose Route > Auto
Shielding.
The Auto Shield Route dialog box appears.

- Next to Shield with, select ground to tie the shielding wires
to ground or select specify to tie them to a net you specify in
the box.
10-41
- Select Do not connect to shielding net pins to keep shielding

wires from being connected to pins.
- Select Do not connect shielding to standard cell rails to
disable all shield tie-downs to standard cell rails (and allow
shielding wires to connect to the power mesh only). Use this
option to disable connections to the standard cell rails that
overlap standard cell pins.
Ignoring Shielding During Detail Routing

During layout parasitic extraction, Astro looks for the nearest
neighbor up to the defined intralayer capacitance lookup distance or
the varRouteRule shield distance, whichever is smallest, and
assumes a grounded geometry at that point, even if a real geometry
is not found. For 90-nm designs, you can use the
ekIgnoreShieldNDRinDR command to ignore shielding during
detail routing.
In your Astro command file, enter the following syntax:
define ekIgnoreShieldNDRinDR 1
Shielding With Default Spacing Rules

To shield nets with default spacing rules,
1. Open the Quick Signal Route dialog box (enter
axgQuickSignalRoute or choose Route > Quick Route).
2. Under High Performance Option, click Shield net.
The window expands, and the options for shielding nets appear.
Chapter 10: Routing

10-42
3. Specify the names of the target nets to be shielded.

4. Select shielding options, depending on your requirements.
You can click Custom width/spacing (expands the window
further) to specify nondefault width or spacing for the shielding
wires on one or all of the poly and metal layers in your design.
For descriptions of the shielding options, see the
axgQuickSignalRoute command in Physical Implementation
Online Help.

10-43
Running ECO Routing on Detail-Routed Designs

Use the axgECORouteDesign command to reconnect routing after
making interactive changes or after making netlist ECO changes.
You can run ECO routing on the entire design or on specific regions.
To run ECO routing on detail-routed designs,
1. Enter axgECORouteDesign or choose ECO > ECO Route
Design ECO.
The ECO Route Design dialog box appears.
Chapter 10: Routing

10-44

Next to Phase, you can
- Select Auto to specify that Astro first uses detail routing to
connect broken or new nets. If detail routing fails to connect
broken or new nets (because the change scope is too large),
Astro uses global routing to connect only broken or new nets,
and then performs track assignment or detail routing to
complete the ECO routing process. Because, in this mode,
Astro performs incremental global routing on the modified
nets, rather than the whole design (like when global is
selected), the process is faster and does not introduce new
timing violations.
- Select global, track assign, and detail to specify that Astro
perform global routing, track assignment, and detail routing in
sequence to complete the engineering change order process
(the default). You can also select global to complete global
routing, and then stop. Depending on your design
requirements, you might want to select both global and track
assign or detail only.
Select Region Based to enable region-based ECO routing.
- Astro performs ECO routing in the areas of the design that are
defined by the net names you specify, rather than in the entire
design. Region-based ECO routing is available only when you
select Auto (next to Phase). Make sure you enter the name of
the input file that contains the list of net names to be routed.
- If you want to use the distributed routing feature for
region-based ECO routing, select Distributed Routing. Your
network must be properly set up before you run this option (see

10-45
Using Distributed Routing on page 10-52). Also, enter the

number of CPUs that Astro can use (a value of 0 or 1 disables
distributed routing and Astro uses a single CPU).
Next to Scope, you can
- Select global (the default), to specify that the router not only
connects or routes the nets modified by the engineering
change but also works to fix DRC violations in the design.
- Select local when your design is almost DRC-clean to specify
that the router connects or routes the nets modified by the
engineering change order but does not work on fixing DRC
violations (faster runtime).
For descriptions of all the axgECORouteDesign command

You can use the axgGlobalRoute, axgAssignToTracks,
axgDetailRoute, and axgSearchRepair commands to perform
global routing, track assignment, detail routing, and
search-and-repair. Note that the preferred methodology is to use
astAutoRoute.
Global Routing
The axgGlobalRoute command considers spacing and wide-wire
variable routing rules, as well as shielding variable routing rules,
when calculating congestion.
Chapter 10: Routing

10-46
To perform global routing,

1. Enter axgGlobalRoute or choose Route > Global Route
Global Route.
The Global Route dialog box appears.
2. Next to Speed, select one of the following:

- prototype, which runs initial global routing only
- fast, which runs initial global routing and one rerouting pass
- medium (the default), which runs initial global routing and four
rerouting passes
- slow, which runs initial global routing and eight rerouting
passes
3. Display a congestion map by selecting one of the following:
- congestion map only, which creates a congestion map based
on global routing, without creating global wires, to evaluate
placement (see also Evaluating Automatic Placement on
page 8-28)
- display congestion map, which displays a congestion map after
the global routing is done
10-47
You can also display congestion maps with the

axgDisplayGRCongestionMap command. For information,
see Displaying Global Routing Congestion Maps on
page 10-30.
When you run axgGlobalRoute, any previously created global
routing is deleted.
Track Assignment
To perform track assignment,
Enter axgAssignToTracks or choose Route > Track Assign !

During track assignment, Astro displays a Progress Report
window that reports how long the process has run and projects
how much longer the track assignment will take.
Detail Routing
To perform detail routing,
1. Enter axgDetailRoute or choose Route > Detail Route
Detail Route.
The Detail Route dialog box appears.
Chapter 10: Routing

10-48

- Next to Track Assignment, select Auto to automatically perform
track assignment during detail routing or select Skip to prevent
Astro from assigning tracks during detail routing.
- Next to Search & Repair Loop, enter the number of times to
perform incremental search-and-repair. If you do not want to
run search-and-repair, enter 0.
- Next to Run Time Limit, enter the number of minutes for detail
routing to be performed. A value of 1 (the default) means no
limitation.
CPU).

10-49
Search-and-Repair
After detail routing, you can run incremental search-and-repair
routing passes. During these routing passes, Astro searches for
DRC violations and reroutes wires in an effort to avoid violations. The
Astro router does not add metal stubs on frozen nets to fix DRC
violations even when the nets have DRC violations.
To perform search-and-repair,
1. Enter axgSearchRepair or choose Route > Detail Route
Detail Route Search & Repair.
The Search & Repair dialog box appears.

- Next to Search Repair Loop, enter the number of times to
perform incremental search-and-repair (the default is 50).
Chapter 10: Routing

10-50
- Next to Run Time Limit, enter the number of minutes for

search-and-repair routing to be performed. A value of 1 (the
default) means no limitation.
- Click reset width to reset any wire width rules that were
changed if you defined variable routing rules
(dbDefineVarRouteRule) after running detail routing.
- Click reset Min/Max layer to remove all the layer constraints
for the cell that you set with the axgSetMinMaxLayer
command.
- Click rerun DRC to rerun DRC if you added or edited wires or
changed net spacing rules after running detail routing.
- Click Trim antenna of users wire to trim unnecessary wire
segments of prerouted wires.
- Click connect tie off to connect signal pins to power and
ground rings and straps or to connect clock rings and straps.
Deselect this option if you did not route power and ground and
clock nets.
- Click connect open nets to connect nets that are not fully
connected.
CPU).

10-51

You can initialize distributed routing to decrease runtime for many
routing operations in the design flow. Distributed routing divides the
design into several routing partitions, based on size and congestion.
These partitions are then routed on separate CPUs, in parallel,
greatly reducing the overall runtime. One CPU is used to reassemble
the partitions. For example, with four CPUs available, a typical
runtime improvement would be a 3.5 times reduction in overall
routing time.
These are the commands that use distributed routing:
axDrouteOptimizeContact (no GUI)
axgCreateStraps (PreRoute > Straps)
axgPrerouteStandardCells (PreRoute > Standard Cells)
axgRouteGroup (Route > Route Net Group)
axgAutoRoute (Route > Auto Route)
axgDetailRoute (Route > Detail Route Detail Route)
axgRoutOpt (Route > Detail Route Detail Route Wirelength

Optimization)
axgSearchRepair (Route > Detail Route Detail Route

Search and Repair)
axgOptimizeContact (Route > Detail Route Detail Route

Contact Optimization)
axgRouterVerify (Route Utility > Router Verify Router

Verify)
Chapter 10: Routing

10-52
On small designs, distributed initial detail routing and

search-and-repair might not be needed. On most designs,
distributing the routing optimization improves runtime linearly.
Initializing, Setting Up, and Running

You can specify that the distributed operations in Astro use either a
package called jp to set up the communication between jobs on a
network, or use resources under the control of the LSF network.
When you choose LSF, you are no longer limited to running only
Astro (the parent process) as a submitted job; all of the child
processes are submitted also, as batch jobs.
The flow for initializing, setting up, and running a distributed routing
operation includes these major steps:
1. Open a library (minimum requirement).
2. Initialize distributed routing by entering jpParallelJob or
choosing one of the following:
- Route Setup > Distributed Routing Setup
- PreRoute > Distributed Routing Setup
The Distributed Routing Setup dialog box appears.

10-53
3. Set up and use the jp mode (the default), or use LSF.

To set up and use the jp mode, do the following:
- Set up the machines, by specifying machine names, CPU limit,
bin path, and library path.
- Click Connect to connect to the network.
- Click Hide.
To use the LSF mode, click Use LSF and select the options in the
shorter window that appears.
- Select Default or Advanced to control how the child processes
are submitted to the LSF network.
Chapter 10: Routing

10-54
When you select Default, the child process is submitted to the

default queue and the default method is used to pick up an
execution host.
When you select Advanced, you can specify syntax that
controls the submission of the child process.
- Click Hide.
4. Run a distributed operation (see the list of commands that run
distributed operations, preceding this flow). In the dialog box that
opens for that command, select Distributed Routing and specify
the number of CPUs.
5. Open the Distributed Routing Setup dialog box, and click
Disconnect to disconnect the network.
6. Close the cell and library.
To connect across machines, use rsh and the ~/.rhosts file. If you go
across the network, edit the library path because it might not be the
same from the remote machine.
Errors and Causes for Failure to Connect

A list of errors and possible causes follows:
ERROR : Machine: <machineName>. Unexpected

output.
- This error can be caused by an incomplete or missing ~/.rhosts
file. An ~/.rhosts file is required for using processors on other
machines. You might need the complete host name, including
the domain name. After you log in (rlogin) to the machine
you want to use, you can use the finger -l UNIX command

10-55
to determine the host name that must be in the ~/.rhosts file.

To be safe, you can always add both, as shown in the following
sample file (one entry per line):
machineName1
machineName1.domain.company.com
machineName2
machineName2.domain.company.com
- This error can be caused by an attempt to mix platforms such

as Sun, HP, and Linux. You cannot mix platforms.
- Another common error is to call stty in noninteractive
sessions: stty requires a controlling terminal, and
noninteractive sessions do not use a terminal.
- Because rsh is used, have your.cshrc file print the tool
messages only or have use the terminal facilities for interactive
sessions. An easy way to find out is to test if the prompt
variable (for csh shells) or the PS1 variable for Bourne shells
(sh, jsh, bash, ksh, zsh, ash) is defined.
For a multiple-system .cshrc file, you can use the following
syntax:
setenv OS uname
if ( "$OS" == "SunOS" ) then
if ($?prompt) echo "This is a SUN os"
source "$HOME/.cshrc.sun"
endif
if ( "$OS" == "Linux" ) then
if ($?prompt) echo "This is a LINUX os"
source "$HOME/.cshrc.linux"
endif
if ( "$OS" == "HP-UX" ) then
if ($?prompt) echo "This is a HP os"
source "$HOME/.cshrc.hp"
endif
Chapter 10: Routing

10-56
ERROR : Reference lib cannot be seen from machine

<xxx>
The reference library paths for the main library are hard-coded to
be machine specific. Use /net/machineName/... when making
reference library links.
ERROR : Machine: <machineName>. Invalid path: /

path/to/working/directory/libraryName
If the working directory is not mounted on a remote machine,
modify the library path in the Distributed Routing Setup dialog
box (jpParallelJob). For example, enter /net/machineName/
path/to/working/directory/libraryName and attempt to reconnect.
ERROR : timed out on waiting for a connection

from machineName. Check bin path and the log
file.
To fix this error, do the following:
- Check the path to the bin directory.
- There might be an incompatibility between the operating
system and Astro, so check that Astro can be started
stand-alone on the machine to which you are trying to connect.

10-57
Chapter 10: Routing

10-58
11
Postrouting Optimization
11
After global routing, track assignment, or detail routing, you can

optimize your design for timing and crosstalk.
Postrouting Optimization Flow
Performing Postrouting Optimization
Optimizing Power After Detail Routing
Filler Cell, Power, Ground, and Standard Cell Considerations
Using Alternative Postrouting Optimization Commands
11-1

The postrouting optimization flow includes post-global routing
optimization, post-track assignment optimization, and post-detail
routing optimization. You can run these processes by running
astPostRouteOpt after global routing, track assignment, and
detail routing by selecting the appropriate routing phase in the Post
Route Optimization dialog box.
The astPostRouteOpt command provides simpler and better
crosstalk fixing than alternative commands, such as astPostGR,
axgAdvRouteOpt, and astPostRT. For more information, see
Fixing Crosstalk With astPostRouteOpt on page 15-53.
The equivalent Tcl command for astPostRouteOpt is
post_route_opt. (Use the Tcl mode online Help
post_route_opt -help command to list all options.)
The astPostRouteOpt command is described in Performing
Postrouting Optimization on page 11-4. The astPostGR,
axgAdvRouteOpt, and astPostRT commands are described in
Using Alternative Postrouting Optimization Commands on
page 11-18.
After routing is completed, you can run wire length and via
optimization by using the axgRoutOpt command. For information,
see Reducing Wire Length and Via Count on page 10-38.
For certain designs, you might want to optimize clocks as a
postrouting operation after routing is completed. After running
postrouting clock tree optimization, run ECO routing to reconnect the
Chapter 11: Postrouting Optimization

11-2
routing. For more information, see Running Postrouting Clock Tree

Optimization on page 9-90 and Running ECO Routing After
Postrouting Clock Tree Optimization on page 9-91.
You can optimize power after detail routing as well as after
postplacement optimization phase 2. When you run power
optimization after detail routing, footprint matching can be done to
minimize the extent of the design changes. For information, see
Optimizing Power After Detail Routing on page 11-15.
You can run optimization with the Astro tool at every point in the
physical design process, from preplacement through postrouting.
Astro works to accurately predict the routing capacitance, providing
slightly pessimistic results that are likely to improve after routing.
Generally, there is no significant increase in slack between placed
timing results and routed timing results. Postrouting optimizations
usually create small changes in your design, such as buffer sizing,
whereas optimizations performed early in the placement flow, such
as high-fanout net optimization, create a larger amount of change.
Astro can support larger designs during in-routing optimization by
splitting timer and routing processes. To specify that the processes
be split based on internal criteria, enter the following:
axSetIntParam "droute" "splitTimer" -1
The default is -1. You can specify that the processes always be split,
rather than spit depending on internal criteria, by setting a value of
1. To specify that they not be split, set a value of 0.
Astro uses topology-based optimization, which interacts with
placement and routing. For more information, see Topology-Based
Methodology on page 8-74.

11-3
The flow for postrouting optimization is shown in Figure 11-1.

Figure 11-1 Postrouting Optimization Flow
From routing
Perform optimization after detail routing

astPostRouteOpt

astPowerRecovery
To design finishing and

interactive changes
The flow for crosstalk prevention and fixing, using

astPostRouteOpt for crosstalk fixing, is shown in Figure 15-1 on
page 15-4.

The astPostRouteOpt command combines the astPostGR,
axgAdvRouteOpt, and astPostRT commands and includes some
new features, specifically to optimize crosstalk effects. Use
astPostRouteOpt to optimize the timing and crosstalk on a global
routed design, a design with track assignment, or a detail routed
design.

11-4
If you select Enable Crosstalk Effects in the Environment page of the

AstroTime Timing Setup dialog box, astPostRouteOpt will
optimize for crosstalk-induced delay. Select Crosstalk Noise
Violations in the Post Route Optimization dialog box to fix static or
switching noise violations.
The astPostRouteOpt command uses the Astro common
extraction, timer, and crosstalk analysis engines. Select DB or
DB_then_LPE as the parasitic source in the Parasitics page of the
AstroTime Timing Setup dialog box (see Parasitics Page on
page 6-38) when you require astPostRouteOpt to use the PARA
view that is generated with the Astro layout parasitic extraction or
Star-RCXT. However, when astPostRouteOpt performs in-route
optimization, it uses its own extraction.
A global cost function is available that you can set before you run
astPostRouteOpt. When enabled, postrouting optimization
generally produces improved transition fixing as well as improved
setup and hold worst negative slack (WNS). To enable the global
cost function, enter
axSetIntParam "pds" "use_global_cost" 1
By enabling the new replace_backslash parameter, you can

specify that the backslash (\) in the net local names created during
optimization (astPostRouteOpt) is to be replaced with an
underscore (_). This enhancement allows the net names generated
by Astro to be easily identified in PrimeTime.
Enter
axSetIntParam "cg" "replace_backslash" 1
The default is off (0).

11-5
Optimization Histogram Reports

As you run optimization commands, including astPostRouteOpt,
a histogram report is printed in the log file. The histogram report
starts at the target slack value and ends at the worst setup slack
value. The delta value for the histogram is determined by distributing
the worst setup slack value and the target slack value into 10 bins. A
sample histogram report follows:
PDSHIST: Total Paths = 29
PDSHIST: Total Negative Slack Paths = 22
PDSHIST:
Slack
Paths
Target=0.1000
PDSHIST:
-0.0729
13
PDSHIST:
-0.0537
0
PDSHIST:
-0.0345
5
PDSHIST:
-0.0152
1
PDSHIST:
0.0040
3
PDSHIST:
0.0232
3
PDSHIST:
0.0424
0
PDSHIST:
0.0616
1
PDSHIST:
0.0808
0
PDSHIST:
0.1000
3
If you want to control the delta value used in reporting the slack
histogram, use the pds_histogram_delta_value parameter
with the define command. For example, enter
define pds_histogram_delta_value 0.02
If a valid delta value is defined, an additional line will be printed to

indicate this value:
PDSHIST: User defined delta value: 0.02
With a delta value defined, the histogram starts from the target slack
value, steps to the worst negative slack (WNS), and stops at the
smallest slack before reaching the WNS. For example, if the target

11-6
slack is 0.1, the delta value is 0.02, and the WNS is -0.075, the top
slack in the histogram will be -0.06 (because the step to the WNS is
-0.08, which is less than -0.075). In this case, where the
pds_histogram_delta_value is defined as 0.02, the following
sample histogram report is printed:
PDSHIST: Total Paths = 29
PDSHIST: Total Negative Slack Paths = 22
PDSHIST: User defined delta value: 0.02
PDSHIST:
Slack
Paths
Target=0.1000
PDSHIST:
-0.06
x
PDSHIST:
-0.04
x
PDSHIST:
-0.02
x
PDSHIST:
0.00
x
PDSHIST:
0.02
x
PDSHIST:
0.04
x
PDSHIST:
0.06
x
PDSHIST:
0.08
x
PDSHIST:
0.1000
x
Inverter-Only Optimization
You can use an inverter-only (that is, no buffers) library set and
perform inverter-only prerouting and postrouting optimization
(without making use of any buffers). The inverter-only algorithms are
included in the astPostRouteOpt command, as well as the
astAutoPlace command and topology-based stand-alone
optimization commands, such as astTopoHold, astTopoSetup,
astTopoTransCap, and astFanoutSetup.
To perform inverter-only optimization, you must set the
inverter_mode parameter to 1. For example, enter
axSetIntParam "pds" "inverter_mode" 1

11-7
If your reference libraries have buffers, make sure you assign the
dont_use attribute to all of them before you run optimization
processes, using the astSetDontUse command. The syntax is:
astSetDontUse objectName #t
After you put the specified astSetDontUse commands in a file, you

can load the file to confirm that only inverters are used during the
optimization.
To make sure that only inverters are used, run the
axgListPRSummary command to list all the types of cells in the net
list before and after optimization.
Using the Recommended Flow

The astPostRouteOpt command performs several types of
optimizations, depending on when in the routing flow you run it and
on the effort you select. The recommended flow is to run optimization
on a design that is already detail routed. For information about
varying the flow, see Using the Customized Postrouting
Optimization Flow on page 11-11.
To perform postrouting optimization on a detail-routed design,
1. Enter astPostRouteOpt or astPostRouteOpt "DR" or
choose Route > Detail Route Detail Route Placement/Route
Optimization.
The Post Route Optimization dialog box appears.

11-8
Figure 11-2 Post Route Optimization Dialog Box

11-9
2. Make sure the Detail Route routing phase is selected.

In this mode, astPostRouteOpt performs detail routing
optimization, making both netlist changes and RC reduction in
the detail-routed design.
See also Global Routing Optimization on page 11-13 and
Track Assignment Optimization on page 11-14.
3. Select the effort level to be used during the detail routing
optimization (the default is MEDIUM). Use these efforts to control
the tradeoff between QoR and runtime.
4. Select the options or keep defaults that are appropriate for the
detail routing optimization.
- Use the Optimization Target area to specify the final slack that
Astro attempts to achieve the global constraints for maximum
transition and maximum capacitance allowed. You can set
these values in the AstroTime Timing Setup dialog box (see
Optimization Page on page 6-31). Any changes you make in
this area of the Post Route Optimization dialog box are
reflected in the Optimization page.
- Use the Optimization Mode area to select what types of timing
violations are to be fixed during optimization. If you select Hold
Slack Violations, you can also preserve the worst negative
setup slack or the total negative setup slack by selecting WNS
(the default) or TNS, respectively. You can also control whether
maximum capacitance, maximum net length, and crosstalk
noise violations are to be fixed.
- Use the Optimization Control area to specify that netlist
changes are to be performed during optimization (you can also
specify that the netlist changes involve gate sizing only) and to

11-10
specify that optimizations are to work to reduce intralayer

coupling capacitance on critical paths after detail routing or
track assignment.
- Use the Flow Control area to control whether standard filler
cells are deleted (Purge Filler) and whether DRC fixing or
search-and-repair is performed (Skip ECO). You can also
control the number of search-and-repair loops to be run after
optimization, the runtime of the combined optimization
process, and the number of optimization loops to be run.
The number of search-and-repair loops should not be too large
(5 to 20 loops is usually sufficient). You can use the
axgSearchRepair command separately if needed.
Using the Customized Postrouting Optimization Flow

For many designs, you can use the recommended flow, where you
run axgAutoRoute to perform routing, followed by
astPostRouteOpt to optimize your detail-routed design. If you
cannot close timing with the recommended flow, you can try a
variation, where one or more routing processes (done with
axgAutoRoute) might be followed by the appropriate optimization
processes (done with astPostRouteOpt). For information about
axgAutoRoute, see Performing Automatic Routing on
page 10-25.
For example, you might first run axgAutoRoute to sequentially
perform global routing and track assignment, and then run
astPostRouteOpt to perform track assignment optimization. After
completing these steps, return to axgAutoRoute to perform detail
routing (with search-and-repair), and then return to
astPostRouteOpt to perform detail routing optimization.
11-11
The incremental postrouting optimization flow is shown in

Figure 11-3. You use all or some of these steps depending on your
design requirements.
Figure 11-3 Customized Postrouting Optimization Flow
From placement, optimization, and
Perform global routing

axgAutoRoute
Perform optimization after global routing

astPostRouteOpt "GR"
Perform track assignment

axgAutoRoute
Perform optimization after track assignment

astPostRouteOpt "TA"
Perform detail routing

axgAutoRoute

astPostRouteOpt "DR"

astPowerRecovery
To design finishing and

interactive changes

11-12
Following are separate procedures for performing global routing

optimization, track assignment optimization, and detail routing
optimization, using astPostRouteOpt.
Global Routing Optimization

To run astPostRouteOpt in global routing mode, you must have a
global-routed design (see Global Routing on page 10-27).
To perform global routing optimization,
1. Enter astPostRouteOpt "GR" or choose Route > Global
Route Global Route Optimization.
2. Make sure that the Global Route routing phase is selected.
In this mode, astPostRouteOpt performs global routing
optimization, making incremental changes in the global-routed
design.
3. Select the options or keep defaults. Most of the default settings
are as shown in Figure 11-2 on page 11-9, with the following
exceptions:
- The Crosstalk Noise Violations optimization mode is not
available.
- The R/C Reduction optimization control is off by default.
- The Search & Repair Loop flow control is not available.

11-13
Track Assignment Optimization

To run astPostRouteOpt in track assignment mode, you must
have a design that has track assignment (see Track Assignment on
page 10-33).
To perform track assignment optimization,
1. Enter astPostRouteOpt "TA" or choose Route > Track
Assign Track Assign Optimization.
2. Make sure that the Track Assign routing phase is selected.
In this mode, astPostRouteOpt performs track assignment
optimization, making netlist changes with no RC reduction in the
design.
3. Select the options or keep defaults. Most of the default settings
are as shown in Figure 11-2 on page 11-9, with the following
exceptions:
- The R/C Reduction optimization control is off by default.
- The Skip ECO Routing flow control is not available.
- The Search & Repair Loop flow control is not available.
Detail Routing Optimization

To run astPostRouteOpt in detail routing mode, you must have a
detail-routed design (see Detail Routing on page 10-36).

11-14
To perform detail routing optimization,

1. Enter astPostRouteOpt "DR" or choose Route >
Detail Route Detail Route Placement/Route Optimization.
2. Make sure that the Detail Route routing phase is selected.
In this mode, astPostRouteOpt performs detail routing
optimization, making both netlist changes and RC reduction in
the detail-routed design.
In detail routing mode, the defaults are as shown in Figure 11-2
on page 11-9.

You use the astPowerRecovery command to perform power
optimization after detail routing, as well as after placement and
prerouting. For information about postplacement and prerouting
power recovery, see Optimizing Power on page 8-35.
At the postrouting stage of the design flow, Astro provides a special
power recovery methodology that works to replace cells that do not
vary in size. This methodology depends on the availability of
footprint-equivalent cells.

11-15
To perform power optimization after detail routing,

1. Enter astPowerRecovery or choose PostPlace >
Optimization Power Recovery.
The Power Recovery dialog box appears.

Make sure Use FootPrint Classes is selected. For details, see the
information following this procedure.
For descriptions of the astPowerRecovery command options,
3. Click OK.
Two cells are defined as footprint equivalent when they are the same
size and have identical pin locations, vias, and blockages, and differ
only in power consumption. Assuming that there is footprint
equivalence, Astro can replace cells without doing any rerouting and
still reduce leakage power in the design. Footprint-equivalent cells
must also belong to the same LEQ class.
11-16
Astro does not check whether the size and pin location are
identicalyou must guarantee this. Astro checks that cells defined
as footprint equivalent belong to the same LEQ class.
Note:
It is recommended that crosstalk constraints be ignored during
power recovery at the postrouting stage. This approach is
recommended because the crosstalk cost function is pessimistic
compared to full-blown crosstalk analysis, which could produce
long runtimes and lower QoR.
Because the number of footprint-equivalent cells is usually less than
the number of logical-equivalent cells, footprint-based power
recovery should have lower runtimes than power recovery based on
logical equivalence.
You define footprint equivalence with the
defineFootPrintEQCell command. The syntax is
defineFootPrintEQCell "cell1" "cell2"
Use this command to build footprint-equivalent classes.

Footprint-equivalent cells can span multiple libraries and are stored
in the design library.
Associated commands are
dbDumpFootPrintEQ, which writes out current

footprint-equivalent cell information from the design library
dbClearCellFootPrintEQClass, which clears all existing

footprint-equivalent cell classes from the design library

11-17
Filler Cell, Power, Ground, and Standard Cell

Considerations
If you have deleted filler cells and have not added them back after
optimizations, add them at this point.
In addition, after all optimizations are completed, you might need to
update the power and ground connections. Normally, this is
necessary only for designs with multiple power and ground nets
specified, because the tool might not be able to automatically update
these connections during optimization. To update all power and
ground connections, enter aprPGConnect or choose PreRoute >
Connect Ports to PG.
Also, depending on design style, some cells added during
optimization might not be covered by power and ground standard cell
straps. This can occur on designs that do not use filler cells in all
available standard cell locations or do not cover all the placeable
area with standard cell straps.
If you delete filler cells or update standard cell pin connect, run
search and repair with rerun DRC selected in the Search & Repair
dialog box (axgSearchRepair) to locate the few violations that
might occur as a result of these processes.

You can use the astPostGR, axgAdvRouteOpt, or astPostRT
commands to run postrouting optimizations. The preferred
methodology is to use astPostRouteOpt.

11-18
Routing Optimization After Global Routing

The astPostGR command performs optimizations following global
routing. Make sure you save a backup copy of your global-routed
design before you run this command. Global routing optimization
might not always improve timing, but it can help on some designs.
To optimize the design after global routing,
1. Enter astPostGR.
The Post-Global Route Optimization dialog box appears.

11-19

- Next to Num Loops, enter the number of loops of optimization
and ECO routing (when ECO Route is enabled) to be
performed. The default is 1.
- Next to Max Iterations, enter the number of detailed fixing
iterations to be performed. The default is 100.
- Enable Topology-Based Fixing to perform optimizations by
sizing cells and inserting buffers along the routing topology.
You can choose the types of violations to be fixed, including
maximum length, transition and capacitance, setup, and hold
violations.
- Enable Detailed Fixing to perform detailed optimizations with
cell sizing and buffer insertion. You can choose the types of
violations to be fixed, including setup, hold, maximum
transition, and maximum capacitance violations.
You can select Preserve Current Timing to preserve the
current timing for each fixing process. This means that while
fixing one set of violations, optimization attempts to not
increase any other violations. It might be helpful to deselect
Preserve Current Timing when focusing on a single violation
type that you want fixed. The default is on.
You can select Area Recovery to perform area recovery during
the optimization while still maintaining all the other timing
constraints. The default is off.
- Select ECO Route to update global routing when finished. This
is needed because during optimization nets can be broken and
new nets created. The default is on.

11-20
You can use incremental global routing to reconnect these nets

without significantly changing the routing pattern. If you dont
enable ECO Route, you must run incremental global routing
separately. For information, see Running Incremental Global
Routing on page 10-32.
3. Click OK.
Routing Optimization After Detail Routing

The axgAdvRouteOpt and astPostRT commands provide two
approaches for optimizing a detail-routed design.
Using axgAdvRouteOpt
The axgAdvRouteOpt command optimizes timing and crosstalk
the design must be fully routed and include the necessary timing
information. Advanced postrouting optimization calls the timer to
analyze the critical paths and then the optimization uses various
techniques to improve timing and minimize crosstalk problems. It
attempts to fix the crosstalk problems by using spacing controls and
layer adjustment as well as buffer insertion and gate sizing. For more
information, see Fixing Crosstalk With axgAdvRouteOpt on
page 15-56.
The axgAdvRouteOpt command uses built-in, quick extraction.
The extraction is approximately 5 percent more pessimistic than the
normal Astro postrouting extractiontherefore, you should run
axgAdvRouteOpt before astPostRT. (The preferred methodology
is to use axgAdvRouteOpt after astPostRouteOpt.)
To run advanced postrouting optimization,
1. Enter axgAdvRouteOpt.

11-21
The Advanced Route Optimization dialog box appears.

- Use the Optimization Mode area to do the following: Set the
target slack value for setup timing; choose an effort (optimize
or preserve); choose the types of violations to be fixed,
including transition time and maximum capacitance violations;
and enable crosstalk noise constraints to be fixed.

11-22
The optimize effort means that the router tries to improve the
slack timing based on the slack target. The preserve effort
means that the router ignores the slack target setup and
attempts to not make the slack timing any worse than the
existing result during the optimization process.
- Use the Optimization Operations area to choose the types of
fixing to be performed, including buffer insertion and bypass
and gate sizing. You can also instruct the router to reduce the
intralayer coupling capacitance on the critical path.
- Next to Search & Repair Loop, enter the number of search and
repair loops to run after the optimization to clean up the
remaining DRC violations. The default is 5.
- Next to Run Time Limit (min), specify the number of minutes
Astro can perform the in-routing optimization process. A value
of 1 (the default) means no time limitation.
- Select Skip ECO Routing to specify that the axgAdvRouteOpt
command does not perform DRC fixing or search and repair.
The default is off.
- Select Rerun Timer after finished to specify that the timer is
called to check the timing of the design.
You might want to fix crosstalk noise only, without buffer insertion,
using axgAdvRouteOpt. To do so, select Crosstalk Noise
Constraints and R/C Reduction. Also, adjust the setup effort
setting when you want to fix crosstalk only, besides preserving
timing.

11-23
Note:
Running in this mode can be useful at the end of the design
flow, when you might need to run minor routing steps on a
design that already meets timing and crosstalk requirements.
The additional routing steps must consider crosstalk to be able
to prevent the creation of new crosstalk violations.
Using astPostRT
The astPostRT command optimizes setup, hold, transition, and
capacitance constraints on a routed design. (These optimizations
are similar to postplacement optimizations.)
The astPostRT command makes small, localized changes to the
routing, working to repair timing violations that remain after the
design is fully routed. Such changes include cell sizing and buffer/
inverter insertion.
To run postrouting optimization,
1. Enter astPostRT.
The Post-Route Optimization dialog box appears.

11-24
2. Select the options depending on your requirements. Among the

options are
Fast Extraction uses real R and virtual C (based on actual
routes). This is the default extraction in Astro. It uses the Astro
TLUPlus capacitance models and uses the resistance from the
TLUPlus file.

11-25
You can use the cmAttachStarRCXT command to attach

parasitic models to the library for each of the operating conditions
(process corners) that are relevant to the postrouting
optimization process.
For descriptions of all the astPostRT and cmAttachStarRCXT
3. Click OK.

11-26
12
Design Finishing and Interactive Changes12
After routing and postrouting optimization, you can optimize contacts
and perform design finishing processes to improve the reliability of
your design. You can also make interactive routing changes.
Optimizing Contacts
Preventing Isolated Vias
Performing Design Finishing Processes
Optimizing Yield
Interactively Cleaning Up Routing DRC Errors
Engineering Change Order Methods
12-1
Using Edit-In-Place
Working With Astro Interactive Ultra
Chapter 12: Design Finishing and Interactive Changes

12-2
The flow for performing design finishing and interactive changes is

shown in Figure 12-1.
Figure 12-1 Design Finishing and Interactive Changes Flow
From postrouting optimization
Optimize contacts
axDrouteOptimizeContact
or
axgOptimizeContact
Perform design finishing processes,

such as metal density filling and wide metal slotting
axgFillWireTrack
axgSlotWire
Perform interactive changes
To verification and back-annotation
Optimizing Contacts
The axDrouteOptimizeContact and axgOptimizeContact
commands replace the specified single-cut via or ContactCode with
a multiple-cut via array or a different ContactCode that has the same
metal layer. You can specify multiple target vias for one via type;
Astro tries all the target vias in the order specified. These commands
work on all the nets except the frozen nets. For
axgOptimizeContact, the default is to replace vias on all the nets,
but you can also specify particular net names for via optimization.
Optimizing Contacts
12-3
The axDrouteOptimizeContact and axgOptimizeContact

commands select a target via, and replace a single via, only if doing
so does not introduce any new DRC violations. By default, after via
optimization, the commands automatically run one loop of
search-and-repair. However, it is recommended that you run
axDrouteOptimizeContact and axgOptimizeContact with
zero search-and-repair loops and then decide whether to run
search-and-repair loops after via optimization.
For axgOptimizeContact, you can change the number of
search-and-repair loops by entering a number in the Search Repair
Loop box in the Optimize Contact dialog box. For either
axgOptimizeContact or axDrouteOptimizeContact, you can
use the optViaSrLoop parameter. The syntax is
(axSetIntParam "droute" "optViaSrLoop" 1)
;; range [0,100], default=1;
;; N: Conduct 'N' search-repair loops after optimize contact.
#t
Via optimization honors the antenna checking parameter. That is, if

the doAntennaConx parameter is set to enable antenna checking,
double vias will be rolled back to single vias, because of their
potential to cause antenna violations. In this case, the log file will
print a message similar to the following:
Rolled back 144 contacts due to antenna violations
Via optimization can also be run in timing-driven mode (the default is

non-timing driven mode). To enable timing-driven mode, use the
optViaTimingDriven parameter. The syntax is

12-4
(axSetIntParam "droute" "optViaTimingDriven" 0)

;; 0: regular opt via,
;; 1: try to preserve timing critical nets with hold
;; violations.
In timing-driven mode, the timing-critical nets (nets that traverse the

negative setup and hold slack timing paths) are excluded from via
optimization. You identify the timing-critical paths by setting
thresholds, using the optViaHoldTimeThreshold and
optViaSetupSlackThreshold parameters. The syntax is
(axSetRealParam "droute" "optViaHoldTimeThreshold" 0.000)
;; range [-1000000.000,1000000.000], default=0.000;
;; N: Do not opt via for nets whose hold time is worse than N.
(axSetRealParam "droute" "optViaSetupSlackThreshold"
-0.100)
;; range [-1000000.000,1000000.000], default=-0.100;
;; N: Do not opt via for nets whose setup slack is worse than N.
For axgOptimizeContact, you can run via optimization in

distributed mode (that is, run Astro parallel on different CPUs and
machines) by setting the Distributed Routing and Number of CPUs
options in the Optimize Contact dialog box. You must set up your
network properly (see Using Distributed Routing on page 10-52)
before running this feature. For either axgOptimizeContact or
axDrouteOptimizeContact, to enable the distributed mode, set
the distributedViaOptimization parameter. For example,
enter
axSetIntParam "droute" "distributedViaOptimization" 1
Optimizing Contacts
12-5
Also, set the viaOptimizationNumCPUs parameter to specify the

number of CPUs to be used. For example, enter
axSetIntParam "droute" "viaOptimizationNumCPUs" 4
Using axDrouteOptimizeContact
The axDrouteOptimizeContact command (no GUI) performs
the same functionality as axgOptimizeContact, with the
exception of not having the capability to specify particular nets for via
optimization.
The syntax is
(axDrouteOptimizeContact "cellId"
((fromContactName toContactName
) #t|#f 1
cellId
toContactSize)...)
ID of the cell that you want to check for contact DRC

violations.
Valid values:
ID of any cell in the open library. If the cell is open, you
can substitute the following for cellId: geGetEditCell.
fromContactName
The name of the contact to be replaced.
toContactName
The name of the new contact to be created. In most

cases, this should be the same as fromContactName.
If it is different from fromContactName, the layer
definition of the two contacts must be the same.
toContactSize
The number of cut rectangles in the newly created

contact array.
#t
Forces the command to adhere to the specified 1xN

pattern.

12-6
#f
Allows 1xN and Nx1 patterns.
Specifies that the command try a few more possible

ways to replace single vias.
Using axgOptimizeContact
The axgOptimizeContact command provides a GUI for
performing the same functionality as
axDrouteOptimizeContact. In addition, with
axgOptimizeContact you can specify particular net names for via
optimization (the default is to replace vias on all the nets).
To optimize contacts,
1. Enter axgOtpimizeContact or choose Route > Detail Route
Detail Route Contact Optimization.
The Optimize Contact dialog box appears.
Optimizing Contacts
12-7

12-8

- Choose whether the command applies to all nets (All) or
named nets (Selected). When you choose Selected, either
select Window and enter the net names, or select File and
enter the name of the file that contains the net names.
- Enter a number in the Search Repair Loop box to control the
number of search-and-repair loops to be performed during
contact optimization.
CPU).
- Select Double all contacts to enable the via-doubling
process.
- Select Dont touch other nets to specify that the router modify
only the selected nets when fixing DRC violations caused by
via array replacements. No other nets are modified, even when
there are DRC violations on other nets.
- Specify the name of the contact to be replaced (From) and the
name of the new contact to be created (To), as well as the
number of cut rectangles allowed for the newly created contact
array (Size).
You can use this dialog box to specify up to 20 pairs of
contacts. To optimize more than 20 pairs, define them with the
axgOptimize parameter. The maximum number of pairs
allowed is 60.
Optimizing Contacts
12-9
Preventing Isolated Vias

Use the axReportIsolatedVia command to report isolated via
rule violations, and use the axFixIsolatedVia command to
check and fix the violations. The axFixIsolatedVia command
fixes violations by performing one-side floating via insertion.
An isolated via violation occurs when one of the following conditions
exists:
There is an adjacent via located less than N microns from the via.
You use the isolatedViaSpacing parameter to define this
constraint. The syntax is
isolatedViaSpacing range
; range 0 to 5.0 default 1.0 micron
There are adjacent vias that cover all four quadrants located less
than N microns from the via.
You use the isolatedViaQuadrantSpacing parameter to
define this constraint. The syntax is
isolatedViaQuadrantSpacing range
; range 0 to 50.0 default 10.0 micron
To apply via isolation rules to specific layers rather than all layers,
use the checkIsolatedViaPerLayer parameter. Enter
axSetIntParam "droute" "checkIsolatedViaPerLayer" 1

12-10
After enabling this parameter, specify both the isolated via spacing
and quadrant spacing for each layer. For example,
axSetIntParam "droute" "via1IsolatedViaSpacing" 5.0
axSetRealParam "droute" "via1IsolatedViaQuadrantSpacing"
10.0

The design finishing processes you can perform include metal
density filling and wide metal slotting.
Metal Density Filling

Use axgFillWireTrack to fill empty tracks in your design with
metal wires to meet metal density rules required by most processes.
If minimum/maximum density rules are defined in the technology file,
Astro tries to fill metals within the specified ranges. You should run
axgFillWireTrack after routing is complete and before DRC and
connectivity verification.
When you run axgFillWireTrack in timing-driven mode, Astro
works to create fills that meet both timing and metal density rules by
adjusting the fill spacing, length, and location as needed.
Note:
Fill tracks are connected by vias only. They are no longer joined
to each other by wrong-way metals.
Defining Data Types

You can set the data type for the fill objects to be used during filling
by using the following settings:
12-11
To define the fill data type, enter

axSetIntParam "droute" "fillDataType" n
To define the fill-via data type, enter

axSetIntParam "droute" "fillViaDataType" n
Using axgFillWireTrack
To perform metal density filling,
1. Enter axgFillWireTrack or choose Route Utility > Fill Wire
Track.
The Fill Wire Track dialog box appears.

12-12

Select Timing Driven to specify that Astro consider timing during
metal fill by keeping a wider spacing for fill metal around the
timing-critical wires. This avoids timing changes caused by
adding metal fill.
Select Use Floating Vias To Meet Density Rule to allow floating
vias to be added to meet via density rules.
You can specify the global spacing allowed between metal fill and
wires by entering a number in the Spacing to routing box. The
number you enter is multiplied by the minimum spacing of the
12-13
metal layer. For finer control, you can specify layer-based

fill-to-wire spacing, by clicking Custom Pattern. In the expanded
window that appears, enter a number in the Space to Route
column for one or all of the metal (or poly) layers in your design.
Layer-based spacing uses the technology file unit. If the specified
layer-based spacing is not consistent with the global spacing for
a given layer, the larger value takes precedence.
For descriptions of all the axgFillWireTrack command
Wide Metal Slotting

Use the axgSlotWire command for slotting wide wires and contact
arrays for specified or selected nets. This command is used primarily
for slotting preroute wires. Signal nets can also be processed for
slottingrun axgSlotWire after detail routing is complete and
before DRC checking and verification.
You can select DMode in the Slot Wires dialog box to enable the
dimension rule mode. In this mode, slotting must meet the following
dimension rule constraints:
Create the number of slot rows as n = wire_width/cutWidth
Center the rows at multiples of wire_width/(n+1)
Astro issues a warning if it cannot find a valid slotting solution for a

particular wire, using these constraints.
To perform wide metal slotting,
1. Enter axgSlotWire or choose PreRoute > Slot Wires.

12-14
The Slot Wires dialog box appears.
2. Next to Select Wires, select Do Signal Net.

3. Specify the names of nets or select the nets to be processed for
slotting.
4. Select the options for specifying slotting parameters.
For descriptions of the axgSlotWire command options, see

12-15
Optimizing Yield
Manufacturability and yield-related issues become increasingly
important in deep submicron designs. At the post detail-routed
design stage, you can perform wire spreading and display critical
area heat maps to help reduce critical areas in the layout.
You can also run density-driven global routing and track assignment
to potentially improve yield. For more information, see Specifying
Density-Driven Global Routing on page 10-28 and Specifying
Density-Driven Track Assignment on page 10-34.
Performing Wire Spreading

Use the route_spreadwire Tcl command to perform wire
spreading on a detail-routed design. This command increases the
average spacing between wires and, therefore, improves yield. It can
make the following changes to the layout:
Widen the spaces between wires (moves wires on the same

layer)
Move wires to the upper or lower metal layers as needed, to

resolve DRC violations caused by widening spaces
During the wire spreading process, a piece of the original wire is

broken and pushed away, creating jog wires. To control the minimum
jog length allowed in the preferred routing direction, use the
wireSpreadMinJogLength parameter. The syntax is
axSetIntParam "droute" "wireSpreadMinJogLength" 2
;; range: [2,100], default = 2

12-16
Reporting Critical Areas and Displaying Heat Maps

Use the report_critical_area Tcl command to report layout
critical areas that are susceptible to random particle defects (that
cause shorts and opens) during the fabrication process. The syntax
is
report_critical_area
-particle_distr_func_file {distr_functn}
-input_layers {m2 m3 m4}
-fault_type {short|open}
-multi_particle_report_format
Option
Description
-particle_distr_func_file
distr_funct
Inputs a particle distribution function.
-input_layers layer
Specifies the layers for which critical area is to

be calculated.
-fault_type type
Specifies whether shorts or opens are

reported.
-multi_particle_report_format
Outputs a report containing the critical area

analysis result of each individual particle size;
use this option when you need the critical area
analysis result of each particle size instead of
normalized results.
The particle probability function is considered sensitive data. When

security for a sensitive particle distribution file from a foundry is of
concern, you can use the
process_particle_probability_file Tcl command, which
provides a way to encrypt and decrypt the particle probability
function. Critical area analysis can work with the encrypted particle
probability function.
Optimizing Yield
12-17
You use a secret key to encrypt the particle probability function. The
encrypted file cannot be decrypted without the key. Critical area
analysis takes the encrypted file as its input and processes it without
the key. The output will be the heat map based on the encrypted
particle probability function; it will be in text format. The text format of
the particle probability function is still accepted as input to critical
area analysis. If an encrypted file is given as input, the file is
internally decrypted and used.
The syntax is
process_particle_probability_file
-key string
-input_file fileName
[-output_file fileName]
Option
Description
-key string
The key used to encrypt and decrypt the

particle probability function. The string can
be a combination of alphabets and
numbers. The key specified for the
encryption of a file must be identical to that
specified for decryption. The command
fails if they do not match. The key must be
a minimum of eight characters long.
-input_file fileName
Specifies the name of the input file. If it is a

text file, the output will be an encrypted file.
If it is an encrypted file, the output will be a
text file.
-output_file fileName
Specifies the name of the output file. If

none is specified, an output file name will
be created based on the name of the input
file (inputFileName_out).

12-18
Use the axgDisplayCritAreaHeatMap command to display heat

maps for the critical areas. The maps indicate where a chip might fail
due to particle defects. Use this command on a detail-routed design.
To display critical area heat maps,
1. Enter axgDisplayCritAreaHeatMap.
The Critical Area Heat Map dialog box appears.
2. Select the type of defect to display (Short or Open).

3. Select the metal layer for which critical area shorts or opens are
to be displayed.
4. Select text to make text visible in the map.
Optimizing Yield
12-19
5. Enter and select the appropriate values for the map and select a
color to represent the value.

Run the axgQuickSignalRoute command to interactively clean
up errors. Use this command when your design does not route clean
and a few trouble errors remain.
When you are running axgQuickSignalRoute, the router is
initialized only once. This means that for multiple edits, the command
runs quickly after the first time.
To interactively clean up errors,
1. Enter axgQuickSignalRoute or choose Route > Quick Route.
The Quick Signal Route dialog box appears.

12-20

For descriptions of the axgQuickSignalRoute command
options, see Physical Implementation Online Help. See also
Shielding With Default Spacing Rules on page 10-42.
3. Click Initialize.

12-21

Astro supports various ECO methods for the design, while still
maintaining hierarchy preservation information. Use these methods
when you want to make an interactive change, after your design is
routed and optimized. You can
Use astEdit to interactively change the critical paths or

problem cell (this command is graphically based).
Use astChangeNetlist to interactively remove or insert

buffers, size cells, or replace masters (this command is name- or
file-based).
Interactively create a change file and then use

auECOByChangeFile to update the design (see Using the
ECO-by-Change-File Method on page 12-23).
Output a hierarchical netlist from Astro, edit it, and use

auECOByNetCmp to update the design (see Using the
ECO-by-Net-Compare Method on page 12-24).
Use other individual functions, including

- astLenBI to perform length-based buffer insertion (see
Maximum Wire Length on page 8-93).
- axRouteAddBufferByFile to evenly split nets by using
buffer insertion after routing.
- astECOCTS when deleting, adding, or relocating flip-flops for
clock tree synthesis (see Running ECO Routing After
Postrouting Clock Tree Optimization on page 9-91).

12-22
Maintaining Hierarchy Preservation Information During

ECO
You can use the ECO-by-change-file and the ECO-by-net-compare
methods and still maintain hierarchy preservation information.
Because the astRepairHierPreservation command repairs
hierarchy preservation, these ECO changes are not limited to buffer
and inverter insertion and cell sizingyou can insert buffers and
inverters, rename cells, insert or remove cells, and insert or remove
nets.
Using the ECO-by-Change-File Method

You can interactively create a change file and then use
auECOByChangeFile to update the design by using the flow in the
following diagram.
For detailed information about the auECOByChangeFile command
auECOByChangeFile
astRepairHierPreservation
astDumpHierVerilog

12-23
The ECO-by-change-file method includes these major steps:

1. Make ECO changes to the cell that contains hierarchical
information.
For information about creating the change file with the
auECOByChangeFile and cmCmdECODump commands, see
2. Open the design library, and run
3. Run astDumpHierVerilog, and check if all the ECO changes
appear in the generated Verilog file.
4. Open the cell, and continue with the flow.
Note:
Observe the limitations of astRepairHierPreservation
(see Repairing Hierarchy Preservation and Deleting Hiconn
Nets on page 4-23) when implementing the ECO change file in
this flow.
Using the ECO-by-Net-Compare Method

You can output a hierarchical netlist from Astro, edit it, and use
auECOByNetCmp to update the design by using the flow in the
following diagram.
For detailed information about the auECOByNetCmp command

12-24
NETL1 CEL1 EXP1
NETL1 CEL2 HP2 HVO2

Modify HVO2 to HVO3 and generate EXP3.
NETL1 CEL2 EXP3 HVO3
EXP3 copied to the design .lib; ready for ECO.
auECOByNetCmp
After ECO, CEL2 -> CEL3.
NETL1 CEL3 EXP3 HVO3
Relink NETL3 and init HP3.
NETL3 CEL3 HP3 HVO3
A typical flow for ECO changes with hierarchy, using an edited netlist,
includes these major steps:
1. Perform netlist in, bind the netlist, and initialize hierarchy
preservation for the original netlist. The view in the database is
represented by the following:
NETL1
CEL1
HP1
2. Perform optimization that changes the CEL1 and HP1. You now
have
CEL2
HP2

12-25
3. Do an ECO on this cell. You need to

- Output a netlist with astDumpHierVerilog to produce a
hierarchical netlist (HVO2). You now have
CEL2
HP2
HVO2
- Make the changes to HVO2 to create HVO3.

4. Back up the original cell before proceeding further. Pay special
attention to the NETL views so that the NETL views created when
you read in the original netlist and those created when you read
in the ECO netlist (HVO3) cannot be mixed up. There are several
ways to do this. One method is as follows:
- For simplicity, back up the entire design library. Then delete all
cells (CEL views) except for the design-Cell.CEL. Also delete
all NETL views, because you use the new NETL view created
by Verilog-in during the ECO process. Delete all EXP cells as
well.
- Read the new netlist into a new library by creating the library,
adding reference libraries, and then reading in the netlist with
the same settings as when the original netlist was read in. This
creates the topModuleName.NETL. Expand the netlist by
using the same settings as the original expansion. This creates
the topModuleName.EXP view.
- Copy the topModuleName.EXP into the original design library.
You might want to rename it to keep the original EXP view and
the eco.EXP view distinctthis is necessary if you did not
delete all the EXP cells.

12-26
- Delete the hierarchy preservation, HP2, from CEL2. Perform

the ECO change-by-compare process (auECOByNetCmp) on
CEL2, given the expanded cell derived from HVO3
(topModuleName.EXP or whatever name you specified in the
previous step) to produce CEL3. You now have
CEL3
HVO3
This cell is successfully updated with netlist changes.

5. Update the hierarchy preservation. The NETL view needed for
this is the one created when you read in the ECO netlist. A
similarly named NETL view might exist in the original library that
existed when the original netlist was read in if you did not delete
all the NETL views.
- To update the reference to the NETL view, be sure the original
NETL views cannot be found by the tool, by either deleting
them or breaking the reference link (if they are contained in the
reference library); then add the reference library link from the
design library to the ECO netlist library that was read in.
- To update the hierarchy preservation, perform the initialize
hierarchy preservation process
(astInitHierPreservation). You should now have
NETL3
CEL3
HP3
HVO3
6. To perform hierarchical Verilog out from the updated cell, all

macro NETL cells read in during the ECO need to be found by
the tool. The easiest way to do this is to use a reference library
link for all the NETL cells read in during the ECO. The tool needs
these to correctly re-create bus information to the macros.

12-27
Using Edit-In-Place
Edit-in-place can help you fix difficult DRC problems across the
hierarchy (useful for going down one level to see cell geometries). It
also lets you fix hierarchical antenna problems by allocating a lower
module error spot and then performing overall antenna analysis
without hopping along different hierarchies.
To use edit-in-place,
Choose Cell > Edit-In-Place, and select one of these commands:

- Edit Selected ! (eipPush)
- Up One Level ! (eipPop)
- Quit EIP ! (eipQuit)
You should select an object prior to using Edit Selected !. For
descriptions of these commands, see Physical Implementation
Online Help.

The Astro Interactive Ultra tool is a netlist and routing editor that
combines both semiautomated and interactive routing and editing
capabilities. Some of its features are interactive bus and net routing
and custom shielding and wire spreading. Open a Milkyway library
and design cell before issuing Astro Interactive Ultra commands.
These sections provide an introduction to Astro Interactive Ultrafor
complete information, see the Astro Interactive Ultra User Guide.

12-28
Point-to-Point Routing
Use the Astro Interactive Ultra tools point-to-point routing feature to
help complete the routing of your design. Access this feature from
the Route Utility menu in Astro. This replaces the Astro point-to-point
routing feature.
To activate point-to-point routing,
1. Enter leaPointToPointRoute or choose Route Utility >
Interactive Ultra Point-to-Point Route.
You can also activate point-to-point routing by choosing Tools >
AstroIU > Interactive Ultra > Interactive Routing Point-to-Point
Route.
The Point To Point Route dialog box appears.

12-29

12-30
2. Select the options or keep defaults. You can control the metal
layer preference, the guidance point, and other settings such as
the following:
- Select Honor Variable Net Rules to observe variable routing
rules.
- Select Snap To Track to route on track. The default is off
(routes off track).
For detailed information about the leaPointToPointRoute
command options, see the Astro Interactive Ultra User Guide and
3. Perform point-to-point routing with global guidance.
Using the Control Panel

Use the Control Panel (trPanel) to select options that affect Astro
Interactive Ultra as well as the Astro shape-based router. For
example, you can use these options to control the interactive
commands for bus routing, length-resistance matched routing,
area-based wire spreading, violation cost, and area-based ripup and
rerouting.
To access the Control Panel,
Enter trPanel or choose Tools > AstroIU > Auto Ultra > Control
Panel.
The Control Panel dialog box appears.

12-31
The Control Panel dialog box includes the Net, Rule, Cost, Option,
Global, Bus, PreRoute, Utility, DFM, and Advanced tabs that you can
use to control all aspects of routing.
For detailed information about the trpanel command options, see
the Astro Interactive Ultra User Guide and Physical Implementation
Online Help.

12-32
13
Verification and Back-Annotation
13
You can verify your design by performing design rule checking (DRC)
and connectivity verification. You can also generate output for
back-annotation.
Performing Design Rule Checking and Connectivity Verification
Generating Output for Back-Annotation
13-1
The flow for verification and back-annotation is shown in Figure 13-1.

Figure 13-1 Verification and Back-Annotation Flow
From design finishing and
interactive changes
Perform DRC and connectivity verification

geAdvDRC for 90 nm and below design rules or geNewDRC
geNewLVS
Generate output for back-annotation
Performing Design Rule Checking and Connectivity

Verification
Run DRC and connectivity verification prior to running full verification
in the Hercules tool. The DRC/LVS operations in Astro do not check
the design as completely as a sign-off DRC/LVS tool such as
Hercules.
See also Appendix C, Routing Design Rules.
Design Rule Checking

You can run design rule checking with the geAdvDRC or geNewDRC
commandsboth these operations create an error cell, from which
you can request a summary of errors or highlight errors of specific
Chapter 13: Verification and Back-Annotation

13-2
types (see Using the Error Browser on page 13-9). Also, you can
run design rule checking and verification with the
axgRouterVerify command.
Use geAdvDRC and axgRouterVerify when your design
technology is 90 nm and below. When working with technologies that
are 0.13 microns and above, you might choose to perform DRC with
geNewDRC.
Running Design Rule Checking for Advanced

Technologies
Use geAdvDRC to detect 90-nm process design rule violations. This
command automatically generates the Hercules DRC runset based
on the Astro technology file, calls Hercules to check DRC violations,
and returns the results to Astro. A Hercules license is required to use
the geAdvDRC command.
To run advanced design rule checking,
1. Enter geAdvDRC or choose Verify > Advanced DRC.
The Advanced DRC dialog box appears.

13-3

For descriptions of the geAdvDRC command options, see
Note:
You must have a Hercules license to do metal density checking
(Density option).

13-4
Running Basic Design Rule Checking

Use geNewDRC to check design rule violations, such as
Errors pertaining to width, spacing, enclosure, and notch rules
Errors between stacked vias and between two blockage objects
The exact via dimension as specified in the technology file
To run design rule checking,

1. Enter geNewDRC or choose Verify > DRC.
The DRC dialog box appears.

13-5

For descriptions of the geNewDRC command options, see
Running Design Rule Checking and Verification

Use axgRouterVerify to check, verify, and report the following
information for a routed design:
DRC violations
Opens
Charge-collecting antenna violations
Top-layer probe constraints
For information about the design rules that axgRouterVerify

honors, and the technology file attributes that define them, see the
Milkyway Environment Data Preparation User Guide.
To run design rule checking and verification,
1. Enter axgRouterVerify or choose Route Utility > Router
Verify Router Verify.
The Router Verify dialog box appears.

13-6
2. Select the types of information to be checked, depending on your

requirements.
You can select Distributed Routing to use the distributed routing
feature. Your network must be properly setup before running this
option (see Using Distributed Routing on page 10-52). Also,
enter the number of CPUs that Astro can use (a value of 0 or 1
disables distributed routing and Astro uses a single CPU).
For detailed descriptions of the axgRouterVerify command
Connectivity Verification
Use geNewLVS to verify the connectivity of your designthis
process creates an error cell, from which you can request a
summary of errors or highlight errors or specific types (see Using
the Error Browser on page 13-9).

13-7
To run connectivity verification,

1. Enter geNewLVS or choose Verify > LVS.
The NewLVS dialog box appears.

For descriptions of the geNewLVS command options, see

13-8
Using the Error Browser

Use the error browser (geErrorBrowser) to display errors that are
stored in error cells that you create with Astro routing, DRC, and
connectivity verification commands, and with other tools as well. The
error browser provides options that let you specify the type of errors
to be loaded and control how those errors are sorted. It also provides
cross-probing, from the browser to the graphics window, which can
help you analyze and resolve errors in your design.
Note:
The geErrorBrowser command takes the place of other error
cell viewing commands, such as geLoadErrorCell and
geLoadDetailRouteErrCell.
The Error Browser dialog box includes Data and Error-Probing tabs,
two panes, and a Hide button, as described in the following
procedure.
To use the error browser,
1. Enter geErrorBrowser or choose Verify > Error Browser.
The Error Browser dialog box appears.

13-9
The Error-Probing page is shown in the next figure.

13-10
(The options in the Error-Probing page are described in step 5.)

2. In the Data page (Error-Type area), you can
- Choose the type of errors to be displayed in the error tree pane
(lower-left) by selecting one or more of the following:
Detail Route, which shows the errors generated by the
axgRouterVerify command. The errors from the top cell
are loaded.
LVS, which shows the errors generated by the geNewLVS
command. The named error cell is loaded.
DRC, which shows the errors generated by the geNewDRC
command. The named error cell is loaded.
Advanced DRC, which shows the errors generated by the
geAdvDRC command. The named error cell is loaded.
Unknown, which shows the errors generated by another tool.
- For any of the error types, use the sorted by list box to select
various combinations of sorting methods (by error type or error
number or by the layer that the errors appear on).
- For any of the error types, in the Cell Name box enter the name
of the error cell for which you want information displayed. The
boxes are populated with the default error cell names
(cellName_lvs.err, cellName_drc.err, and cellName_adrc.err).
You can click Browse to view and select your files.
- In the File Name box, enter the name of the file in which you
want to save the error results.
- Click Save to File to save the error results to the named file.

13-11
- Click Load to load the error tree in the pane located at the lower
left. This displays the errors stored in the named error cells in
a tree-style graphic.
3. In the error tree pane, select the error types for which you want
to list error objects in the pane located at the lower right.
4. In the error object pane, which reports the number of errors at the
top of the pane, you can
- Use the sorted by list box to select a sorting method for the
error objects (none, type, layer, info). The default is none,
which means the errors are listed in numerical order.
- Use the Maximum errors box to enter the maximum number
of error objects to be listed.
5. In the Error-Probing page (Error-Operation area), you can
- Select show error object by click to choose what error objects
are to be highlighted in the graphics window by selecting them
from the list in the error object pane.
- Select query error in layout window to get information about
highlighted error objects. After you select objects in the
graphics window, the information is printed in the message
area of the Astro application window.
- Select flash to specify that the errors to be highlighted in the
graphics window, flash.
- Use the Zoom Scale box to enter a number at which the
graphics window is zoomed.
- Click Show Errors to enable the highlighting of errors in the
graphics window.

13-12
- Click Turn Off Errors to turn off the highlighting of errors in the
graphics window.
6. Click Hide. (The dialog box can be nested with other dialog
boxes.)

When your design is complete, you can generate output to be used
for back-annotation. There are two types of back-annotation:
Output used by Astro at another hierarchy level
Output for data exchange modeling
Creating Parasitic Views

It is useful to create a PARA (parasitic) view, so that if additional
timing or skew information needs to be generated or used, the
routing capacitances do not have to be reextracted.
To create a parasitic view,
1. Enter astGenPV or choose Timing > Parasitic Output Generate
Parasitic View.
The Generate Parasitic View dialog box appears.

13-13
2. Select the options, depending on your requirements. Some of the

options are:
- Under Content mode,
Basic Saves single capacitance and resistance values in the
database.
Geometry Saves single capacitance and resistance values,
as well as layer and bounding box information for edges and
nodes in the database.
MinMax Saves triplet capacitance and resistance values in
the database. This information is needed for concurrent setup/
hold analysis/optimization.
Analysis Saves single capacitance and resistance values,
layer and bounding box information, current, and temperature
in the database.
TopoMinMax Saves detailed geometry information for both
minimum and maximum extraction in the database. This
information is needed for Astro to correctly consider topology
during postrouting optimization (astPostRouteOpt).

13-14
- Store coupling mesh

Stores the full RC mesh in the database. This information is
needed for crosstalk analysis using parasitic views.
The equivalent Star-RCXT syntax for enabling storing coupling
mesh is
COUPLE_TO_GROUND: NO
Creating Timing Views (Models)

Use the astTimingModel command to model the timing in the
block so that the block can be used in other levels of the hierarchy.
To model the timing in the block,
1. Enter astTimingModel or choose Timing > AstroTime
Generate Timing Model.
The Generate Timing Model dialog box appears.

13-15
2. Next to File Name, enter the name of the file that contains the
timing functions.
3. Next to Table Template File Name, enter the name of the Scheme
file that contains the table template format to be used during the
timing model generation.
Here is a sample template file:
defineTableTemplate "tablex1" "CellDelayAndTransTable"
(("OutputCapacitance" (0.004 0.12 0.3 0.6 1.2 ))
("InputNetTransition" ( 0.02 0.5 1 2 3 )))
defineTableTemplate "tablex2" "ConstraintTable"
(("ConstrainedPinTransition" (0.02 0.5 1 2 3))
("RelatedPinTransition" (0.02 0.5 1 2 3)))

5. Click OK.
Creating a timing model for three operating points and loading them
into the tool includes the following major steps. (The Library and
Parasitic pages are accessed from the AstroTime Timing Setup
dialog box.)
1. Set the timing options to worst case, typical case, and best case;
and generate a file for each case.
For worst case,
- In the Library page, click Worst (next to Design Operating
Conditions).
- In the Parasitic page, click Max (next to Operating Cond:).

13-16
For typical case,

- In the Library page, click Typical (next to Design Operating
Conditions).
- In the Parasitic page, click Nom (next to Operating Cond:).
For best case,
- In the Library page, click Best (next to Design Operating
Conditions).
- In the Parasitic page, click only Min (next to Operating Cond:).
2. Load the three files, using auLoadCLF.
These steps are needed to get the correct clock insertion delay for
both setup and hold time constraints.
Other Output After Completion

Astro outputs information in different formats for data exchange. You
can
Translate connectivity information contained in a top-level cell to

a file in EDIF netlist format
Enter auEdifOut, or choose Tools > Data Prep > Output > Edif
Out.

a file in Verilog format
Enter auVerilogOut, or choose Tools > Data Prep > Output >
Verilog Out.

13-17

a file in VHDL format
Enter auVhdlOut, or choose Tools > Data Prep > Output >
VHDL Out.
Export a Milkyway design cells library technology and reference

cell information to a LEF file
Enter auNLOApi, or choose Tools > Data Prep > Output > LEF
Out.
Export a Milkyway design cell to a DEF file

Enter auNDOApi, or choose Tools > Data Prep > Output > DEF
Out.
Translate a design from Synopsys format to GDSII Stream format

Enter auStreamOut, or choose Tools > Data Prep > Output >
Stream Out.
Note:
Use the astDumpHierVerilog command to generate a
hierarchical Verilog netlist for a given flat cell when the cell
contains hierarchical information. For more information, see
Generating Hierarchical Verilog on page 4-19.
In addition to a hierarchical or flat netlist, Astro outputs the following
RC and delay information in different formats for back-annotation:
RC and delay extraction in Astro format

Enter astLPEOut, or choose Timing > Parasitic Output LPE
Out.

13-18
RC extraction in DSPF format

Enter astDSPFOut, or choose Timing > Parasitic Output DSPF
Out.
RC extraction in SPEF format

Enter astSPEFOut, or choose Timing > Parasitic Output SPEF
Out.
RC extraction in SPICE format

Enter astSPICEOut, or choose Timing > Parasitic Output
SPICE Out.
Cell and interconnect delays in SDF format

Enter ataDumpSDF, or choose Timing > Parasitic Output SDF
Out.

13-19

13-20
14
Antenna Checking and Fixing
14
At the end of the detail routing phase, search-and-repair can check

for antenna violations, as well as fix them. For most top-layer metal
antenna violations, and some violations that cannot be fixed by
search-and-repair, Astro can insert diodes to fix them.
Antenna Checking and Fixing Flow
Preparing Antenna Data
Inserting Diodes on Prerouted Nets
Checking and Fixing Antennas During Search-and-Repair
Inserting Diodes to Fix Remaining Violations
Deleting Diodes
14-1
Reporting Antenna Violations
Importing Hercules Antenna Reports
Chapter 14: Antenna Checking and Fixing

14-2

In Astro, the detail router checks and fixes antenna violations the
placer, global router, and track assignment operation do not account
for antenna effect.
Generally you should first run place and route operations with
search-and-repair to clean up all DRC violations; then enable
antenna checking in search-and-repair to clean up antenna
violations.
For most top-layer metal antenna violations, and some violations that
cannot be fixed by search-and-repair, Astro can insert diodes to fix
them. Based on the diode-protection mode/value and the antenna
mode/ratio, Astro automatically selects diodes and calculates the
number of the diodes needed to fix the violations. The diodes are
inserted on the wires, close to the input pins that have antenna
violations. A layer constraint is assigned to each diode pin to force
the router to connect the routing to the diode that has layers only
below the layer with the antenna violation.
The flow for antenna checking and fixing is shown in Figure 14-1.

14-3
Figure 14-1 Antenna Checking and Fixing Flow

Prepare antenna data
Insert diodes on preroute nets (optional)

axgAddDiodeForPreroute
Connect power and ground afterward.
Route the design

Obtain 0 router design rule check violations
Optimize the design
Set antenna mode

axgSetHPORouteOptions or
(axSetIntParam "droute" "doAntennaConx" <mode>)
Set antenna rules

For mode 4:
dbDefineAntennaRule
dbAddAntennaLayerRule
Mode = 0 4
It is recommended that you use mode 4.
Run search-and-repair
Router lists violations in the log file
For runtime speed:
(axSetIntParam "droute" "topAntennaFixRange" n)
Insert diodes for remaining violations

axgInsertDiode
Check remaining antennas

axReportAntennaRatio cellId
Not OK
OK
Antenna fixing complete

14-4
Connect power and ground afterward.

In general, the router's antenna computation engine computes
metal-area, gate-area, and diode-protection properties for all layers
and for every pin with a gate that needs to be protected. For antenna
modes 2 and 5, the router also needs to compute the partial ratio
underneath each layer.
For standard cells, usually only simple antenna properties (gate area
and diode protection) are needed for antenna checking. The pin area
is also included in the metal area for antenna computation.
For macro cells, hierarchical antenna properties are needed. These
properties provide the information for the child cells that is used for
calculating antenna ratios. For detailed information about the model
for hierarchical antenna properties, including how these properties
are used in calculating antenna ratios, see the Hierarchical Process
Antenna Methodology document.
For macro cell pins with a gate inside (nonzero gate size), the
antenna checker treats the cell pins as input pins. At first, the
hierarchical antenna properties (metal area, gate area, diode
protection, and partial ratio) for these pins are included, and then
they are accumulated with all the top-level routing and pins.
For pins at the top level, when the antenna computation engine sees
a pin with hierarchical antenna properties, it also accumulates the
metal area, gate area, diode protection, and partial ratio stored on
the pins and includes them when computing the total antenna ratio.
After violations are located, they can be fixed by search-and-repair
and diode insertion.

14-5
Cell Library Format

The cell library format (CLF) requirements for standard cells are
defineGateSize, which defines the gate size for a specific port

on a cell
defineAntennaArea (optional), which defines the metal area

considered by antenna checking for a specific port on a cell, if it
is not reflected correctly by the geometry in the cell
defineDiodeProtection, which defines the values used in

computing the allowable ratio when an antenna is protected by a
diode
Top Design Format

The external antenna properties in Top Design Format (TDF) are
used for place and route soft macros. These properties fix antenna
violations by adding extra antenna information from outside the
macro to all the pins within the macro. The external antenna
properties provide an antenna summary of a top-level cell and
provide data that is used for the antenna calculation of the place and
route macro.
The external antenna properties are
defineExtDiodeProtection
defineExtAntennaArea
defineExtGateSize

14-6
Hierarchical Antenna Data

The hierarchical antenna properties are used for antenna calculation
for the top-level cell.
The commands to generate hierarchical antenna data are
axComputeHierAntennaProp (for Astro DB)

This command generates the hierarchical antenna properties for
routed blocks in Astro.
hmiHierAntenna (for GDSII)requires a Hercules license

This command generates the hierarchical antenna properties for
hard macros. It creates a new run set so that the
accumulated-ratio antenna properties can be computed in
Hercules (must be Hercules version U-2003.03 or later).
In previous releases, two of the advanced process antenna modes

(2 and 5) were based on the accumulative area mode. Now they are
based on the accumulative ratio modethis is the accumulation of
the ratios for the layer and the layers belowto have better accuracy
during the hierarchical process antenna calculation.
The axComputeHierAntennaProp and hmiHierAntenna
commands generate properties that are required for antenna
checking. These commands calculate hierarchical antenna
properties that are consistent with the Hercules calculations.
The hierarchical antenna properties are described in the CLF file as
defineHierAntennaProp statements.

14-7
Use the axImportAntennaReport command to input the antenna

report file created by Hercules. You can then use this report for fixing
antenna violations in Astro. For more information, see Importing
Hercules Antenna Reports on page 14-18.
Diode Cell
To prepare the diode cell, do the following:
If it is not already in the library, read in the diode cell, by using

auStreamIn, auGenCellBndry,
auExtractBlockagePinVia, and auSetPRBdry.
Define the diode port, by using dbConvertPortToDiodePort.
Define the diode protection, by using

defineDiodeProtection.
Technology File
If a sidewall is used for antenna calculations, define the thickness by
specifying the following in the technology file:
unitMinThickness
unitNomThickness
unitMaxThickness

14-8

Before you check for antenna violations and add diodes at the end of
detail routing, you can insert diodes on the preroute nets in your
design by using the axgAddDiodeForPreroute command. This
command inserts diode cells under preroutes, primarily for clock
rings and straps. The preroutes (rings and straps) are ignored by the
Astro antenna checker.
To insert diodes on prerouted nets,
1. Enter axgAddDiodeForPreroute or choose Route Utility >
Charge-Collecting Antenna Insert Diode for Preroute.
The Add Diode For Preroute dialog box appears.

14-9

- Enter the diode master cell name.
- Enter a number to specify the maximum and minimum
protection area per diode.
- Choose whether the command applies to all clock nets or to
specific nets. Select all clock nets; select specified and
enter the net names; or select from file and enter the name of
the file that contains the net names.
- Specify the wire layer by entering its layer number in the first
data box. You can also click in the adjacent box (?:?) to open
the Edit Layer Panel dialog box and select a layer. This
populates the two data boxes with the layer number and layer
name, respectively.
- Select the wire routing type (ring, strap, or user). Astro allows
diode insertion for these types of power and ground meshes,
as well as for clock meshes.
- Select Complete Routing to finish routing from the added diode
cell instances to the preroute wires.
Checking and Fixing Antennas During

Search-and-Repair
During search-and-repair, Astro checks for antenna violations and
then tries to fix most antenna violations by breaking the antenna with
a higher-layer metal. When the antenna violation is at the top-metal
layer, Astro might also try to move some routing from top-layer metal
to lower-layer metal to fix the violation. Because it is expensive to

14-10
move routing from top-layer metal to lower-layer metals, you can set
a threshold specifying that Astro move routing to lower layers only
when a small amount of wires needs to be moved.
Checking and Fixing Floating Wire Antennas

You can check floating wire antennas (also known as dot short
antennas) and fix the violations during search-and-repair. Dot short
is a phenomenon where the static charge collected by a floating wire
causes an electric shock to a neighboring path that is connected to
a gate.
Floating wire antenna violations are fixed during search-and-repair
by breaking the longest wires and jumping to the top layers based on
the checking results. To fix floating wire antennas, you must enable
the floating wire antenna mode by setting the floatingWireMode
parameter. When this mode is enabled, all other antenna checking
and fixing is disabled. For example, enter
(axSetIntParam "droute" "floatingWireMode" 1)
The syntax is
(axSetIntParam "droute" "floatingWireMode" 0)
;; range [0,2], default=0, stored in cell;
;; 0: fixing based on antenna conx (if any)
;; 1: fixing based on floating antenna conx only
;; 2: fixing based on floating antenna conx only (ignore
;; violations on user routes)
Following is the syntax for the detail routing parameters that you can
set for checking floating wire antennas:

14-11
axSetIntParam "droute" "ignoreFloatingWireSpacing" 0)

;; 0: check spacing for the floating wire antenna,
;; 1: dont check spacing for the floating wire antenna QoR
(axSetIntParam "droute"
"ignoreFloatingWireToBlockageSpacing" 0)
;; 0: check spacing to blockages for the floating wire
;; antenna,
;; 1: dont check spacing to blockages for the floating wire
;; antenna
(axSetRealParam "droute" "accumFloatingWireArea" 0.000)
;; range [0.000,1000000.000], default=0.000, stored in cell;
;; N: maximal allowable accumulated area for the floating
;; wire antenna
(axSetRealParam "droute" "m1FloatingWireArea" 0.000)
;; N: maximal allowable metal1 area for the floating wire
;; antenna
(axSetRealParam "droute" "m1FloatingWireSpacing" 0.000)
;; N: metal1 spacing for the floating wire antenna
(axSetRealParam "droute" "floatingWireIsGateDischarge" 1)
;; range [0,1];
;; 0: gate is not discharge path (is floating);
;; 1: gate is discharge path (is not floating)
After setting the parameters, run the search-and repair operation

with the axgSearchRepair command.
See also Limiting Net Layer Length to Prevent Floating Antennas
on page 10-34. The net layer length parameters are set at the track
assignment stage.

14-12
Setting the Antenna Mode

Use the axgSetHPORouteOptions command to select the mode
to be used for checking the charge-collecting antenna. Astro
provides four antenna modes. Modes 1, 2, and 3 include preset ways
to calculate the antenna area; mode 4 is advanced and lets you
specify your own rules. For descriptions of these modes, see step 2
of the following procedure.
To specify the charge-collecting antenna mode,
1. Enter axgSetHPORouteOptions or choose Route Setup >
HPO Signal Route Options.
The HPO Signal Route Options dialog box appears.

14-13
2. Under Charge-Collecting Antenna,

Select the antenna mode (1, 2, 3, or 4) to be used for subsequent
routing operations, or select ignore. The choices are
- ignore
Does not check or fix the charge-collecting antenna.
- ............. (Mode 1) or ignore lower-layer segments
Calculates the maximum ratio for checking the antenna, by
using the top mask layer only as the wiring area.
- __........ (Mode 2) or include lower-layer segments to
pins
using the area from the input port to the closest top layer as the
wiring area.
- ____... (Mode 3) or include all lower-layer segments
using the area from the input port to the topmost layer as the
wiring area.
- Mode 4 or advanced
Instructs the router to use the antenna rule as defined by
dbAddAntennaLayerRule and dbDefineAntennaRule
instead of the ratio specified in the dialog box or in
axSetIntParam.
For modes 1, 2, and 3, all output ports are assumed to provide
unlimited diode protection.

14-14
Next to Max. Ratio, enter the maximum allowable ratio of wiring

area to gate area for checking the antenna.

Use the axgInsertDiode command to insert one or more diodes
into the design to fix antenna violations. First this command runs the
internal antenna checker or uses Hercules output to identify the
antenna violations. Then a diode cell (or multiple diodes when the
antenna ratio requires the protection of more than one diode) is
placed for each violation. See also Importing Hercules Antenna
Reports on page 14-18.
To insert diodes into the design to fix remaining violations,
1. Enter axgInsertDiode or choose Route Utility >
Charge-Collecting Antenna Insert Diode with Checking.
The Insert Diode for Antenna Violation dialog box appears.

14-15

Select Floating Wires to enable checking for the floating-wire
antenna rule. During the chemical mechanical planarization
(CMP) process, the static charge collected on the temporary
floating wires can discharge through the adjacent wires and
cause shorts. (Temporary floating wires are those wires not
connected to a diffusion or gate area during the manufacturing
process.) This means that excess charge will be passed to
adjacent wires that are possibly connected to the gate. This
phenomenon can break the gate and cause the device to
14-16
malfunction. To avoid shorting issues, the floating-wire antenna

rule sets the maximum values allowed for metal areas on the
temporary floating wires. The rule includes settings for the metal
area for each layer (so that each layer has its own threshold) and
for the total metal area that is applied to all layers.
You can select Freeze existing placement to freeze placement
and routing for all the existing cells so that the diode cells are
placed only in existing empty spaces, to minimize the impact on
the existing placement and routing. You can also choose to let
axgInsertDiode complete the routing of the diode cells when
the cell placement is already frozen. Whenever possible, Astro
attempts to tie the diode cells to the existing wires without ripping
up and rerouting the entire net.
For descriptions of all the axgInsertDiode command options,
Deleting Diodes
Use the axgDeleteDiode command to delete all diode cells or
specific diode cells that were inserted to fix antenna violations. This
command does the following:
1. Disconnects all the diode port on the named nets.
2. Deletes the named diode cells that are fully disconnected. A fully
disconnected cell instance contains no connected port (except
power and ground) and no connected diode port.
3. Deletes all dangling wires (when you select this option in the
Delete Diode dialog box).
Deleting Diodes
14-17
For information about the axgDeleteDiode command options, see

Reporting Antenna Violations

Use the axReportAntennaRatio command to run the antenna
checker and to write a detailed report of antenna violations into the
log file.
The syntax is
axReportAntennaRatio cellId

Use the axImportAntennaReport command to import the
Hercules antenna report directly into the Milkyway database (library)
for use with axgInsertDiode. The axImportAntennaReport
command attaches the antenna report as a private version of the top
cell under the CEL view with respect to the cell ID.
The syntax is
axImportAntennaReport dbId string
cellId fileName
where dbId is the name of the Milkyway database, cellId is the cell
window ID of the active cell, and fileName is the name of the antenna
report generated by Hercules with the antenna run set.

14-18
For example,
axImportAntennaReport (geGetEditCell) "herc.ant.rpt"
Be aware that if an antenna report already exists in the Milkyway

database, the newly imported report overrides it.

14-19

14-20
15
Signal Integrity: Crosstalk Prevention,
15
The Astro-Xtalk tool prevents, analyzes, and fixes crosstalk

violations to ensure signal integrity.
Crosstalk Features and Flow
Preventing Crosstalk
Analyzing Noise
Fixing Crosstalk Violations
Additional Information About Crosstalk Circuit Models
For information about signal electromigration analysis and cell

electromigration checking, see Chapter 16, Signal Integrity: Signal
and Cell Electromigration.
15-1

Signal integrity is the ability of an electrical signal to carry information
reliably and to resist the effects of high-frequency electromagnetic
interference from nearby signals. Crosstalk is the undesirable
electrical interaction between two or more physically adjacent nets
due to capacitive coupling. The two major effects of crosstalk are
crosstalk-induced delay and static noise.
Crosstalk can affect signal delays by changing the times at which

signal transitions occur. That is, it can either speed up or slow
down the transition time of the victim net. These changes occur
when both the victim and the aggressor nets are switching at the
same time. When both are switching in the same direction, the
transition time of the victim net decreases and delay is reduced.
When the victim and aggressor nets are switching in opposite
directions, the transition time of the victim net increases and
delay is increased. Therefore crosstalk can affect both setup and
hold times. The noise on the victim net is referred to as switching
noise.
Static noise occurs when the victim net is in a steady state of

either a high or low, and the aggressor net is switching. This
causes a glitch on the victim net. If a glitch is of sufficient height
and width, and if it occurs at the input of a latching structure
during a latching operation (possibly as the result of an earlier
glitch propagated through combinational logic), then a functional
failure will result.
Astro-Xtalk prevents, analyzes, and fixes crosstalk violations to

ensure signal integrity. It first attempts to prevent crosstalk violations
from happening during the placement and placement optimization
phases, and it continues with further crosstalk prevention techniques
during the global routing and track assignment phases. After you
Chapter 15: Signal Integrity: Crosstalk Prevention, Analysis, and Fixing

15-2
perform detail routing, Astro-Xtalk performs crosstalk-induced noise

and delay analysis to identify any remaining violations, and it fixes
these violations during the postrouting optimization phases.
During placement and placement optimization, Astro-Xtalk

estimates congestion based on coupling capacitances. The
optimization processes use buffer insertion and cell sizing to
avoid crosstalk problems.
During timing-driven and crosstalk-aware global routing, the

router attempts to spread the wires that have noise.
During timing-driven and crosstalk-aware track assignment,

Astro-Xtalk minimizes the crosstalk effects by assigning long,
parallel nets to nonadjacent tracks. It runs a simplified noise
analysis to make sure the noise level from aggressor nets is
minimized.
After detail routing is complete, Astro-Xtalk repairs the remaining

problems, first by analyzing the coupling capacitance effects of
the circuit and then by crosstalk removal with postrouting
optimization.
In crosstalk analysis, for each net Astro-Xtalk extracts parasitic
capacitance to the ground as well as any coupling capacitance
with neighboring wires. Astro-Xtalk also invokes static timing
analysis, using the extracted parasitics to obtain the transition
times as well as the arrival time windows of every signal net in the
design. Using this information, Astro-Xtalk evaluates the noise
metric, based on specified crosstalk circuit model.
Astro-Xtalk facilitates manual debugging processes by providing
query functions for dissecting the noise contribution from each
neighboring wire on a net-by-net basis and offering graphical
displays.

15-3
The flow for crosstalk prevention, analysis, and fixing is shown in

Figure 15-1.
Figure 15-1 Crosstalk Prevention, Analysis, and Fixing Flow
Set crosstalk options
atTimingSetup - Environment page and Xtalk page
Perform crosstalk prevention during placement

and placement optimizations
astAutoPlace
Perform clock tree synthesis,

followed by clock tree optimization
astCTS, astCTO
Enable crosstalk prevention options

axgSetRouteOptions
Perform crosstalk prevention during global routing

and track assignment
axgAutoRoute
Perform detail routing and clean up DRC violations

axgAutoRoute
Perform crosstalk analysis

and report crosstalk violations
xtXTalkAnalysis
Perform crosstalk fixing during postrouting optimization

(with crosstalk noise violations enabled)
astPostRouteOpt

15-4
As shown in Figure 15-1, the flow for crosstalk prevention and fixing
includes these major steps:
1. Set crosstalk options. Use atTimingSetup.
In the Environment page, turn on Enable Crosstalk Effects. In the
Xtalk page, specify crosstalk filtering thresholds, specify global
noise thresholds, and select the crosstalk circuit model to be
used during analysis.
See Environment Page on page 6-20 and Xtalk Page on
page 6-45.
2. Perform crosstalk prevention during placement and placement
optimization. Use astAutoPlace.
See Using astAutoPlace to Prevent Crosstalk on page 15-7.
3. Perform clock tree synthesis, followed by clock tree optimization.
Use astCTS and astCTO, respectively.
See Performing Clock Tree Synthesis After Placement on
page 9-62 and Optimizing Clock Trees on page 9-75.
4. Enable crosstalk prevention options (for global routing and track
assignment). Use axgSetRouteOptions.
See Crosstalk Prevention During Global Routing and Track
5. Perform crosstalk prevention during global routing and track
assignment. Use axgAutoRoute.
See Crosstalk Prevention During Global Routing and Track

15-5
6. Perform detail routing and clean up DRC violations. Use

axgAutoRoute.
See Performing Automatic Routing on page 10-25.
7. Perform crosstalk analysis and report crosstalk violations. Use
xtXTalkAnalysis.
See Running Crosstalk Analysis on page 15-25.
8. Perform crosstalk fixing during postrouting optimization. Use
astPostRouteOpt and turn on Crosstalk Noise Violations.
See Fixing Crosstalk With astPostRouteOpt on page 15-53.
Sometimes it is useful to add an extra step, before step 8, to run
postrouting optimization (astPostRouteOpt) without crosstalk
effects enabledturn off Enable Crosstalk Effects in the
Environment page of the AstroTime Timing Setup dialog box
(atTimingSetup). If you do this optional step, make sure you turn
Enable Crosstalk Effects back on before you fix crosstalk by running
astPostRouteOpt with Crosstalk Noise Violations turned on.
Astro works to prevent crosstalk as early as the placement and
placement optimization stages of the design flow, where
congestion-based coupling capacitances are estimated. Further
crosstalk prevention occurs during global routing and track
assignment.
It is recommended that you use the astAutoPlace command for
crosstalk prevention during placement and placement optimizations.
Alternatively, you can use the stand-alone astPostPS1 command.

15-6
These optimizations use the global noise thresholds that you set in
the Xtalk page of the AstroTime Timing Setup dialog box
(atTimingSetup).
Another crosstalk prevention approach is to use shielding, where
strong aggressor nets can be shielded by ground wires.
Using astAutoPlace to Prevent Crosstalk

During placement, the astAutoPlace command works to prevent
crosstalk by reducing utilization. During placement optimization,
astAutoPlace identifies potential crosstalk problems by estimating
the future coupling capacitances and considering the drive strength
of the cell driving the net. Astro uses this information to fix nets that
might be susceptible to crosstalk problems.
To prevent potential crosstalk problems,
1. Enter astAutoPlace or choose InPlace > AutoPlace.
The Astro Auto Place dialog box appears.
15-7
2. Next to Stage, make sure In-Place and Post-Place are selected.

3. Under Placer Options, make sure Congestion Driven and Timing
Driven are selected, and select Prevent Crosstalk. During
in-placement optimization, these options perform
congestion-driven placement and timing-driven placement while
at the same time preventing crosstalk effects.
4. Click Detail Options.
An expanded window appears.

15-8
Under Post-Place Optimization, select Prevent Crosstalk. (You

must have enabled the Post-Place stage; otherwise the options
under Post-Place Optimization are not available.)
5. Click OK.
15-9
Using astPostPS1 to Prevent Crosstalk

You can use the stand-alone astPostPS1 command to prevent
crosstalk. Note that the preferred methodology is to use
astAutoPlace.
The astPostPS1 command uses design rule checking and avoids
potential crosstalk problems by using buffer insertion and cell sizing.
To prevent potential crosstalk problems,
1. Enter astPostPS1 or choose PostPlace > Optimization
Post-Placement Optimization Phase 1.
The Post-Placement Optimization Phase 1 dialog box appears.

15-10
2. Make sure Design Rule Fixing is selected.

3. Under Design Rule Checking, select Prevent Xtalk.
When this option is enabled, Astro computes noise by estimating
aggressors and estimating coupling capacitance between the
aggressors and victim nets. Astro uses this information to fix
violating nets by increasing the driver strength or by buffering the
net. This technique attempts to preserve the current timing of the
design, and skips prevention when the change causes too much
timing degradation.
4. Click OK.

Assignment
Astro can prevent crosstalk during the global routing and track
assignment stages. First, open the Route Common Options dialog
box (enter axgSetRouteOptions or choose Route Setup > Route
Common Options) and do the following:
Select Crosstalk Prevention.
Under Global Routing, select Timing Driven and enter a weight

value or keep the default.
Under Track Assign, select Timing Driven and enter a weight

value or keep the default.
When these options are enabled, because timing has a higher cost
than crosstalk, Astro attempts to reduce crosstalk while it preserves
timing. (The Route Common Options dialog box is shown in
Figure 10-2 on page 10-19.)
15-11
Then continue with the normal global routing and track assignment
settings and execution (for more information, see Performing
Automatic Routing on page 10-25). Fifty to ninety percent of
crosstalk problems can be prevented by use of crosstalk prevention
during global routing and track assignment.
Global Routing
During global routing, the axgAutoRoute command uses a wire
spreading approach to prevent crosstalk. You can enhance crosstalk
avoidance by decreasing the global noise threshold valuesuse the
Xtalk page of the AstroTime Timing Setup dialog box
(atTimingSetup).
Track Assignment
Track assignment is the initial phase of detail routing, and it
determines the locations of most long wires. Because most crosstalk
problems occur on long, parallel wires, track assignment can be
effective in reducing crosstalk problems by assigning long wires
differently.
To minimize crosstalk-induced delay, the axgAutoRoute command
avoids putting long, parallel wires on adjacent tracks during track
assignment. To minimize noise, track assignment estimates the
potential noise with a simplified crosstalk checker and reassigns
wires to reduce the potential noise. Track assignment uses the noise
threshold you specify in the Xtalk page of the AstroTime Timing
Setup dialog box (atTimingSetup). For most designs, a noise
threshold of 0.30 to 0.35 is recommended (the default is 0.35).

15-12
Using Shielding to Prevent Crosstalk

You can help prevent crosstalk by using ground wires to shield strong
aggressor nets, which are nets with high frequency, such as clock
nets. You can shield routed nets by using the
axgAutoShieldRoute command or by using the Shield Net option
in the Quick Signal Route dialog box (axgQuickSignalRoute).
For information, see Shielding Nets on page 10-40.
Analyzing Noise
You can perform crosstalk analysis on a design that has global
routing, track assignment, or detail routing completed. The minimum
requirement is a global-routed design.
Preparing to Analyze Crosstalk

Before you run crosstalk analysis or timing analysis to report static
noise and crosstalk-induced delay, you need to set up the design.
This includes creating a PARA view (optional), setting
crosstalk-related timing setup options, and specifying supply
voltages.
Generating a PARA View (Optional)

Use the astGenPV command to generate a PARA view where
analysis is based on the parasitics stored in the PARA view (which
includes distributed coupling capacitances). For descriptions of the
astGenPV command options, see Creating Parasitic Views on
page 13-13 or Physical Implementation Online Help.
Analyzing Noise
15-13
You can run crosstalk analysis with the medium-effort crosstalk

circuit model that is based on runtime layout parasitic extraction
you no longer have to generate a PARA view before running the
analysis. This feature is supported only for designs that use the
TLUPlus model.
Setting Timing Setup Options

Use the AstroTime Timing Setup dialog box (atTimingSetup) to
set crosstalk-related options in the Environment, Model, Parasitics,
and Xtalk pages. In the Xtalk page, also specify the filtering
thresholds and global thresholds.
In the Environment page, select Enable Crosstalk Effects.
In the Parasitics page,

- If you generated a PARA view, set the parasitic source to
DB_then_LPE.
- Set the capacitance model to TLU+ (when you are using
TLUPlus files).
In the Model page,

- Set the operating condition. It is recommended that timing
analysis with crosstalk effects be done with one operating
condition at a time. This approach is not required for all
designs.
- Set the net delay model (low, medium, or high effort).
You can specify the high effort for better correlation with
PrimeTime SI, but you get faster iterations by using the
medium-effort (the default).

15-14
In the Xtalk page,

- Set the crosstalk filtering mechanisms. To achieve accurate
results in a reasonable amount of time, Astro-Xtalk filters victim
nets, aggressor nets, and capacitors that it considers to have
too small an effect on the final results.
Parasitic filtering eliminates victim nets, aggressor nets, and
individual cross-coupling capacitors based on the absolute
and relative sizes of capacitors. These filters are used by the
Astro extraction engine.
Electrical filtering eliminates aggressors based on the size of
the voltage bump induced on the victim net by the aggressor
net. These filters are used by crosstalk analysis for
consistency with PrimeTime SI.
- Set the global noise thresholds. A crosstalk violation occurs
when the crosstalk-induced noise voltage exceeds the
specified noise threshold voltage (at or above which a false
transition is likely to be triggered). Crosstalk analysis uses the
noise threshold to report static noise violations.
Note:
Specifying global noise thresholds in the Xtalk page
provides the convenience of only one setup, to be used by
placement and postrouting optimizations as well as
crosstalk analysis.
- Set the noise type to static or switching.
For static noise, crosstalk analysis reports noise violations
(above_low and below_high) that are caused by aggressor net
transitions. Global noise thresholds, noise constraints from a
CLF file, and noise response information from noise libraries
are used for reporting static noise violations.
Analyzing Noise
15-15
For switching noise, crosstalk analysis reports switching noise

violations, where crosstalk-induced delay is a function of
switching noise height and the transition time. Global noise
thresholds only are used for reporting switching noise
violations.
- Choose whether to include timing windows.
The effect of crosstalk between two nets depends largely on
the overlap of timing windows between the two nets. For
example, if the aggressor switches when the victim is in steady
state, it will induce a noise bump on the victim. If the aggressor
switches when the victim is also switching, it can cause the
victim to switch faster or slower. If more than one aggressor
switches in the same timing window, the effect of the two will
be the accumulated effect of each on the victim net.
Timing windows at a particular pin are calculated with the early
and late arrival times of the signal at that endpoint, through
multiple paths. If there is only one path to that endpoint, the
timing window width will be zero.
You can specify that a high-effort timing window calculation be
used during crosstalk analysis. Enter
axSetIntParam "xt" "xtTimingWindowHighEffort" 1
This setting can cause longer runtime. High-effort timing

window calculation cannot be used with optimization.
- Set the crosstalk circuit model (low or medium effort).
You can specify the medium effort for better accuracy during
crosstalk analysis, but you get faster iterations using the low
effort (the default). The medium-effort crosstalk circuit model
cannot be used with optimization.

15-16
Excluding Nets From Crosstalk Analysis

Tie-high and tie-low nets are static nets, which means they cannot
be aggressors to other nets. Also, because they do not switch, they
are not part of the timing paths. Therefore they can be analyzed for
static noise only. You use the xtIgnoreTieHighLowNet command
to control whether tie-high and tie-low nets are to be ignored as
victim nets during static noise analysis. The syntax is
xtIgnoreTieHighLowNet 1 | 0
where a value of 1 (the default) specifies that tie-high and tie-low

nets are ignored as victim nets and static noise is not calculated on
these nets; and a value of 0 specifies that tie-high and tie-low nets
are not ignored as victim nets (static noise is calculated on these
nets).
You can prevent Astro from analyzing clock nets during crosstalk
analysis (also excludes delta delay on clock nets from the timing
report) by using the xtEnableDeltaDelayOnClockNet
parameter. The syntax is
(axSetIntParam "xt" "xtEnableDeltaDelayOnClockNet" 0)
You can exclude nets as victims or aggressors from noise analysis

and from delta delay analysis, as follows:
Use the set_si_analysis command to exclude certain nets

from noise analysis. The syntax is
set_si_noise_analysis [-display] [-exclude] [-victims
vnets] [-aggressors anets]
Analyzing Noise
15-17
When a net is excluded as a victim, it is excluded from static

noise analysis. However, switching noise analysis and delta
delay analysis include the net. Similarly, when a net is excluded
as an aggressor, it is excluded from static noise analysis but
included during switching noise and delta delay analysis.
Use the set_si_delay_analysis command to exclude

certain nets from delta delay analysis. The syntax is
set_si_delay_analysis [-display] [-exclude] [-victims
vnets] [-aggressors anets]
When a net is excluded as a victim, it is excluded from switching

noise and delta delay analysis, but included in static noise
analysis. If this net is part of a timing path, the net will have no
delta delay effect. However, it will have static noise calculated
and reported.
Specifying Power Supply

When your design has multiple power supplies, you should load the
same power supply voltages that are specified in the Astro-Rail tool.
This is necessary because crosstalk analysis reports noise in units
of VDD; that is, noise metrics are percentages of the power supply
voltage. When no power supply voltage information is available, the
voltages of all the power nets are assumed to be identical. It is not
necessary to load the power supply information when there is only
one power supply or all the power supplies have the same voltage.
To load power supply voltages, first prepare a file, such as the
following:
tdfSetPowerSupply "VDD1" 1.8

15-18
Then load the file by entering poLoadPowerSupply or choosing

Power > Data Preparation Load Power Supply.
Note:
These steps are only required when you are using TIM views;
they are not required for LM views.
Guidelines
Make sure that the input transition time for all the cells in the design
is reasonable (less than 1 ns). This is to avoid pessimism in the
calculation of peak noise and crosstalk-induced delta delay.
The boundary conditions you specify for the input pins determine the
driving resistance calculated for the nets assigned to the pins. It is
recommended that you specify the driving cell instead of the input
transition for each input pin, using the set_driving_cell SDC
command. This approach enables Astro to estimate the driving
resistance more accurately and to correlate better with
PrimeTime SI.
Input From CLF Files and Noise Libraries

Besides the global noise thresholds, Astro-Xtalk can use noise
constraints from a CLF file and noise response information from
noise libraries.
The noise thresholds that you set in the Xtalk page of the AstroTime
Timing Setup dialog box (atTimingSetup) are global values; these
settings apply to all the nets. However, some nets can have a higher
or lower noise threshold, depending on the driven cells, so the global
values might not be suitable for all nets. Astro-Xtalk has cell- and
Analyzing Noise
15-19
pin-based noise margin constraints in addition to the global noise

threshold, so different nets can have different noise thresholds (for
the peak).
CLF Constraints
Astro-Xtalk includes both height and width noise constraints for cells
or pins of the cells to further reduce the pessimism of noise analysis.
The noise heights and widths are estimated and compared with the
noise constraints. When the noise widths are smaller, even if the
noise peak is higher than the noise threshold, the nets are filtered
out.
You can input cell- and pin-based noise pulse widths and noise
height (margin) constraints with a cell library format (CLF) file. These
constraints overwrite global noise constraints on the specified cells
or pins. For more information, see the
defineStaticNoiseMargin and defineStaticNoiseWidth
commands in Physical Implementation Online Help.
Noise Libraries
When you specify the medium-effort crosstalk circuit model in the
Xtalk page (atTimingSetup), Astro-Xtalk can use the noise
immunity characteristics of the cell inputs from the noise library to
detect noise violations. Astro-Xtalk first checks for the presence of
noise immunity curves in the noise library. When not available, it
checks for CLF constraints. When CLF constraints are not available,
it uses the global noise thresholds that you specify (in the Xtalk
page).
When you specify low effort, Astro-Xtalk checks for CLF constraints
and when CLF constraints are not available, it uses the global noise
thresholds.

15-20
Noise libraries contain the following types of noise response

information:
The noise immunity characteristics of the cell inputs, either in

terms of allowable noise height and width (noise immunity
curves) or in terms of noise height alone. This information is
needed to determine whether a noise bump of a given size at the
input will cause a logic failure at the output.
Astro-Xtalk uses the noise immunity curves to detect noise
violations at the input pins of each cell instance in the design.
Astro-Xtalk uses the noise immunity curves from the noise
library, if available, in the medium effort only.
The steady-state current-voltage (I-V) characteristics of the cell

outputs. This information is needed to determine the size of the
noise bump that results from crosstalk.
Astro-Xtalk uses the I-V characteristics to determine the static
driver resistance, which is used to calculate the noise height.
Astro-Xtalk uses the I-V characteristics from the noise library, if
available, in both the low and medium efforts.
You can obtain noise libraries from your library vendor. Noise
libraries that are in the .lib format, can be loaded into your reference
libraries. For more information, see Creating LM Views for Timing
and Power Analysis on page 3-29.
Note:
When you attach noise .lib files to reference libraries, make sure
the noise library file is the first .lib file in the list. Astro picks up the
first cell definition that appears in the list of .lib files. If you have
the same cell definition in the first and last .lib file, and the noise
immunity and I-V characteristics are in the cell definition in the
last .lib file, that cell definition will not be loaded into Astro.
Analyzing Noise
15-21
For multi-VDD flows, where each .lib file is characterized at

different voltages, when you have the same cell definition with
noise libraries in multiple .lib files, Astro picks up all the cell
definitions.
Besides detecting noise violations, the use of noise libraries
produces better correlation with PrimeTime in terms of calculation of
noise height.
Reporting Noise Information From Reference

Libraries
You use the xtReportNoiseLibInfo command to report noise
information that is available in the reference libraries (its
recommended that you use LM views) to an output file. This
command first checks for the presence of noise immunity curves,
I-V characteristics, and other data related to noise calculation in the
noise library.
Reporting noise information includes these major steps:
1. Open the design cell.
2. Generate a timing report. Use astReportTiming.
3. Generate a noise information report. Use
xtReportNoiseLibInfo. The syntax is
xtReportNoiseLibInfo filename
For each cell master, Astro writes out the noise information present
in each of the reference libraries linked to that design.

15-22
Sample Report
Following is the sample report:
---------------------------------------------------------noise1/foo
pin: noise1/foo/a
hyper_noise_high: (0.200000 0.300000 0.400000)
hyper_noise_low: (0.100000 0.200000 0.300000)
from noise1/foo/a to noise1/foo/y
si_has_immunity_below_high true
si_has_immunity_above_low true
si_has_iv_below_high true
si_has_iv_above_low true
si_has_resistance_below_high
si_has_resistance_above_low
---------------------------------------------------------CORELIB/CLOCKTREE
pin: CORELIB/CLOCKTREE/A
hyper_noise_high:
hyper_noise_low:
from CORELIB/CLOCKTREE/A to CORELIB/CLOCKTREE/Z
si_has_immunity_below_high false
si_has_immunity_above_low false
si_has_iv_below_high false
si_has_iv_above_low false
si_has_resistance_below_high false
si_has_resistance_above_low false
---------------------------------------------------------CORELIB/FD1
pin: CORELIB/FD1/D
hyper_noise_high:
hyper_noise_low:
pin: CORELIB/FD1/CP
hyper_noise_high:
hyper_noise_low:
from CORELIB/FD1/CP to CORELIB/FD1/D
from CORELIB/FD1/CP to CORELIB/FD1/Q
Analyzing Noise
15-23
Specifying Noise Immunity Characteristics With Tcl

Commands
Use the set_noise_lib_pin Tcl command to set equivalent
noise library pins for a driver or load. For output pins, setting an
equivalent noise library pin means that the I-V curves of the
equivalent noise library pin will be used for the specified pin. For
input pins, the noise immunity information for the equivalent noise
library pin is used.
The syntax is
set_noise_lib_pin pins lib_pin
The set_noise_lib_pin command allows you to specify noise

immunity and I-V curve information in the library.
Specifying Noise Constraints

You can specify noise constraints in the following ways:
Use the global noise threshold settings in the Xtalk page of the
AstroTime Timing Setup dialog box
Provide net-based constraints in a text file
Provide cell- and pin-based constraints in a CLF file
Provide noise library information in the .lib file

15-24
Running Crosstalk Analysis

Use the xtXTalkAnalysis command to analyze and report noise
levels in your design.
Analyzing Crosstalk With the Low-Effort Crosstalk

Circuit Model
Generating a crosstalk report with the low-effort crosstalk circuit
model includes these major steps:
1. Use atTimingSetup to set crosstalk-related timing setup
options. In the Xtalk page of the AstroTime Timing Setup dialog
box, do the following:
- Specify the global noise threshold.
- Next to Noise Type, click Static or Switching.
- Select Include Timing Window.
- Next to Circuit Model, select Low Effort.
2. Use xtXTalkAnalysis to run crosstalk analysis.
Using the low-effort model, xtXTalkAnalysis calculates noise
height and estimates noise width. The report it generates shows
noise height. Noise width is not reported, and slack is not
reported.
Analyzing Noise
15-25
Analyzing Crosstalk With the Medium-Effort Crosstalk

Circuit Model
Generating a crosstalk report with the medium-effort crosstalk circuit
model includes these major steps:
1. Use atTimingSetup to set crosstalk-related timing setup
options. In the Xtalk page of the AstroTime Timing Setup dialog
box, do the following:
- Specify the global noise threshold.
- Next to Noise Type, click Static or Switching.
- Select Include Timing Window.
- Next to Circuit Model, select Medium Effort.
2. Use atTimingSetup to set the parasitic source to LPE. In the
Parasitics page, next to Parasitic Source click LPE.
3. (Optional) Generate a PARA view. Use astGenPV.
- In the Content mode area, select MinMax.
- Select Store coupling mesh.
Note:
For designs that use the TLUPlus model, you no longer have
to generate a PARA view before running the analysis. You can
run crosstalk analysis with the medium-effort crosstalk circuit
model that is based on runtime layout parasitic extraction.
4. (Optional) If you have generated a PARA view, use
atTimingSetup to set the parasitic source to DB. In the
Parasitics page, next to Parasitic Source select DB.
5. Use xtXTalkAnalysis to run crosstalk analysis.

15-26
Using the medium-effort model, xtXTalkAnalysis calculates

noise height and noise width and calculates slack in terms of
area. The report it generates shows noise height, noise width,
and slack.
The following capabilities help crosstalk analysis to provide more
accuracy:
Noise width adjustment, which attempts to reduce the pessimism

in noise width calculation. This adjustment is performed only on
nets for which the noise height is greater than a default threshold
of 0.2. This threshold is the same one that PrimeTime SI uses.
Effective slew calculation, which replaces the noise-affected

waveform by an equivalent standard-transition waveform. This
effective waveform can be used to calculate cell delay and to
output slew, using lookup tables.
Using xtXTalkAnalysis
The xtXTalkAnalysis command sorts the nets to be reported
according to their noise levels and reports those with the highest
values. You can modify the number of nets to be reported, and when
you know which net is most susceptible to crosstalk problems, you
can specify its name. Use a comma to separate the net names for
multiple nets, or use pattern matching for analysis on several nets.
To perform crosstalk analysis,
1. Enter xtXTalkAnalysis or choose Crosstalk > Crosstalk
Analysis.
The Crosstalk Analysis dialog box appears.
Analyzing Noise
15-27

- Next to Object Name, specify the objects to be analyzed for
noise. Enter the net names or the name of the file containing
the port master names that drive the net, depending on
whether you select Net or Port Master File next to Object Type.
- Next to Object Type, select Net if you want named nets to be
analyzed or select Port Master File if you want port master
names from a named file to be analyzed.
- Select Re-Initialize Timing Info to force Astro to recompute all
timing information. When this option is not selected and the
timer is currently active and contains noise information, the
current timing values are used. The default is off.

15-28
If you change any of the crosstalk parameters since the last

timing analysis, you must enable Re-Initialize Timing Info to
generate updated noise values that use the new values set
with the parameters.
- Select Show Noise Histogram to specify that a Noise
Histogram section be included in the report (for examples, see
Noise Analysis Reports on page 15-31).
- Under Report Nets, you can set one of the following limits (to
keep the report from being too large):
Number Sorts the nets according to their noise levels and
lists them in descending order. You can specify the number of
nets to be reported (the default is 200 nets).
Noise Value Reports the nets with noise levels equal to or
greater than the specified value (the default is 0.35). The
specified value is in terms of percentage of voltage.
Important:
Astro calculates noise height in terms of absolute voltage.
The threshold that is specified in terms of percentage of
voltage is therefore scaled so as to be represented in terms
of absolute voltage as well. For example, when you specify
a threshold of 0.35 and the supply voltage is 1.2, the noise
constraint shown in the report is 0.420 (0.35 times 1.2).
- Next to Output To, you can output the crosstalk analysis report
to either a window or a file. If you select File, enter the file name
for the report.
Noise analysis statistics are listed in the log file and a noise
analysis report is generated.
Analyzing Noise
15-29
Noise Analysis Statistics

Here is a sample listing of noise analysis statistics, located at the end
of the log file. It includes the number of rise and fall noise violations
and the noise slack for each.
***** Noise Analysis Statistics *****
Timing Window in noise analysis: OFF
956 / 10057 ( 9.51%) nets are xtalkfree (empty net or no coupling cap)
499 / 10057 ( 4.96%) nets are filtered by small total coupling cap
8498 / 10057 (84.50%) nets are pruned by peak noise
1559 / 10057 (12.53%) nets exceed violation noise voltage (0.20xVDD, 0.20xVDD)
*************************************
NOISESUM:
static noise slack type: height
NOISESUM:
Rise(0.200xVDD)
Fall(0.200xVDD)
NOISESUM:
Slack
Num
Total
Slack
Num
Total
NOISESUM:
-0.315
105
-6.538
-0.430
1559 -126.345
XT: reported 10057 nets for noise region above_low
XT: reported 10057 nets for noise region below_high
These sample noise statistics provide the following information:
The total number of nets in the design is 10,057.
956 nets have no coupling capacitance with any neighboring nets

and are crosstalk free.
499 nets are pruned because the total coupling capacitance is

very small.
8,498 nets are filtered because the peak noise value is below the
noise threshold.
The 956 crosstalk-free nets and the 499 pruned nets are included
in the 8,498 filtered nets, which leaves 1,559 nets (10,057 minus
8,498) with a peak noise value above the noise threshold.
Of the 1,559 nets, some might have rise violations, fall violations,
or both rise and fall violations.

15-30
For NOISESUM,
- 1,559 of the 1,559 nets have fall violations and 105 of the 1559
nets have rise violations.
- The Slack column indicates the worst noise violator and the
Total column indicates the sum of noise slack for each violator.
Noise slack for each net is calculated as follows:
noise threshold (scaled by supply voltage) minus peak noise
reported on net
Noise slack is reported in terms of voltage.
For XT, reported 10057 nets for noise region above_low

indicates the number of nets that are taken into account,
according to what you specified in the Crosstalk Analysis dialog
box. That is, the top N nets or nets above the threshold value.
Noise Analysis Reports

The noise analysis report that xtXTalkAnalysis generates
reports noise values for nets, depending on the settings you make in
the Xtalk page of the AstroTime Timing Setup dialog box
(atTimingSetup). This report includes static noise or switching
noise computation results, using the low-effort or medium-effort
crosstalk circuit model. For low effort, the report separates the noise
violating nets and the nonviolating nets (those nets that have noise
but are not violations) with a line. Nets that have either an above_low
or below_high violation are flagged as a violation in both tables in the
report. For medium effort, the reported slack indicates the violating
nets (there is no need for a separation line in the report).The noise
analysis report is a less detailed report than the one generated using
xtXTalkReport (see Example 15-3 on page 15-39).
Analyzing Noise
15-31
For static noise, xtXTalkAnalysis reports noise violations

(above_low and below_high) that are caused by aggressor net
transitions. Above_low noise violations occur when the victim net is
at the steady state of logic 0 and the aggressor net is switching from
logic 0 to logic 1. Similarly, below_high noise violations occur when
the victim net is at a steady state of logic 1 and the aggressor is
switching from logic 1 to logic 0. When the above_low (rise) and
below_high (fall) noise violations exceed the logic thresholds of the
technology, they can cause logic failures.
For switching noise, xtXTalkAnalysis reports switching noise
violations, where crosstalk-induced delay is a function of switching
noise height and the transition time. This information gives you an
estimate of the crosstalk-induced delay in the design. Not all
switching noise violations need to be fixed. For example, it is not
necessary to fix switching noise on a net that causes induced delay
on a noncritical path.
The noise analysis report includes data called User Peak, which is
used only when the design does not have noise libraries. When this
is the case, the User Peak value is reported as noise_value times
supply voltage, where the noise value is the threshold specified in
the Xtalk timing setup page (atTimingSetup) or the CrossTalk
Analysis dialog box (xtXTalkAnalysis). When the design has
noise libraries, the constraint is taken from the noise library and the
noise threshold values specified in the dialog boxes is not used.
Note:
Noise immunity curves can only be used with the medium-effort
crosstalk circuit model.

15-32
Noise Analysis Report Examples

Example 15-1 is a sample noise analysis report for static noise,
using the low-effort crosstalk circuit model. With this model,
xtXTalkAnalysis reports noise for each net and noise height; it
does not report noise width and slack. The constraint types reported
are constraints from either the CLF or the global noise threshold.
This sample includes the optional Noise Histogram section.
Example 15-1
Static Noise and Low-Effort Model Report
--------------------------------------------------------------------------------------------------------------Astro Noise Report

Tool
: Astro
Version : W-2004.12 - Development for IA.32 - Nov 24, 2004
Design : postroute
Date
: Tues Dec 7 12:35:24 2004
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Design Setup
Parasitics Source: from LPE
Simulation Model : Low Effort
Noise Type
: Static noise
Timing Window
: ON
- Unit of Height: volt
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Noise Histogram
--------------------------------------------------------------------------------------------------------------Rise
Fall
Range(%Vdd)
#net #net(accu.)
%net
#net #net(accu.)
%net
--------------------------------------------------------------------------------------------------------------0.50 <= X < 0.55
0
0 0.00%( 0.00%)
1
1 0.00%( 0.00%)
0.45 <= X < 0.50
0
0 0.00%( 0.00%)
4
5 0.00%( 0.00%)
0.40 <= X < 0.45
1
1 0.00%( 0.00%)
23
28 0.01%( 0.01%)
0.35 <= X < 0.40
4
5 0.00%( 0.00%)
151
179 0.04%( 0.05%)
0.30 <= X < 0.35
25
30 0.01%( 0.01%)
538
717 0.14%( 0.18%)
0.25 <= X < 0.30
139
169 0.04%( 0.04%)
1663
2380 0.43%( 0.61%)
0.20 <= X < 0.25
553
722 0.14%( 0.19%)
4430
6810 1.14%( 1.75%)
0.15 <= X < 0.20
2307
3029 0.59%( 0.78%)
10627
17437 2.73%( 4.47%)
0.10 <= X < 0.15
8478
11507 2.17%( 2.95%)
24188
41625 6.20%( 10.67%)
0.05 <= X < 0.10
28850
40357 7.40%( 10.35%)
54346
95971 13.94%( 24.61%)
0.00 <= X < 0.05
349586
389943 89.65%(100.00%)
293972
389943 75.39%(100.00%)
--------------------------------------------------------------------------------------------------------------Total number of nets:
389943
389943
Analyzing Noise
15-33
Net ranked by noise peak value --Noise region: above_low

Pin Name
Net Name
Width
Height
Slack
Constraint Type
--------------------------------------------------------------------------------------------------------------(n127)
4.4773e-01 User Peak(0.324
)
(n_10_11_)
4.0736e-01 User Peak(0.324
)
(reg_rdata1[31])
3.9551e-01 User Peak(0.324
)
(n_26758743)
3.8815e-01 User Peak(0.324
)
(d0[36])
3.8007e-01 User Peak(0.324
)
(reg_rdata0[25])
3.7648e-01 User Peak(0.324
)
(reg_rdata1[9])
3.7008e-01 User Peak(0.324
)
(n873)
3.6163e-01 User Peak(0.324
)
(n3330)
3.6116e-01 User Peak(0.324
)
(n11712)
3.5327e-01 User Peak(0.324
)
(n331)
3.5261e-01 User Peak(0.324
)
(n_325)
3.5158e-01 User Peak(0.324
)
(be_3_)
3.4365e-01 User Peak(0.324
)
(reg_rdata1[25])
3.4064e-01 User Peak(0.324
)
(reg_rdata0[18])
3.3902e-01 User Peak(0.324
)
(n447)
3.3781e-01 User Peak(0.324
)
(reg_rdata1[19])
3.3697e-01 User Peak(0.324
)
(reg_rd_data6070_4_)
3.3511e-01 User Peak(0.324
)
(reg_rdata0[22])
3.3009e-01 User Peak(0.324
)
(slave_wdata_5_)
3.2973e-01 User Peak(0.324
)
(dataout[20])
3.2968e-01 User Peak(0.324
)
--------------------------------------------------------------------------------------------------------------Net ranked by noise peak value --Noise region: below_high
Pin Name
Net Name
Width
Height
Slack
Constraint Type
--------------------------------------------------------------------------------------------------------------(n3_)
5.4076e-01 User Peak(0.324
)
(n127)
5.3465e-01 User Peak(0.324
)
(n13_)
4.9771e-01 User Peak(0.324
)
(w0[36])
4.9360e-01 User Peak(0.324
)
(t_10_11_)
4.9162e-01 User Peak(0.324
)
(t[5])
4.8280e-01 User Peak(0.324
)
(n1713)
4.7186e-01 User Peak(0.324
)
(n6946)
4.7169e-01 User Peak(0.324
)
(g[32])
4.7125e-01 User Peak(0.324
)
(n267)
4.6972e-01 User Peak(0.324
)
(p_fail_n)
4.5876e-01 User Peak(0.324
)
(net160725)
4.5633e-01 User Peak(0.324
)
(n5_2_)
4.5596e-01 User Peak(0.324
)
(low_water)
4.5569e-01 User Peak(0.324
)
(ci_50_)
4.4963e-01 User Peak(0.324
)
(s[13])
4.4819e-01 User Peak(0.324
)
(a_18_)
4.4593e-01 User Peak(0.324
)
(a_5)
4.4586e-01 User Peak(0.324
)
(s_30_)
4.4568e-01 User Peak(0.324
)
---------------------------------------------------------------------------------------------------------------
Example 15-2 is a sample noise analysis report for static noise,

using the medium-effort crosstalk circuit model. With this model,
xtXTalkAnalysis reports noise on pins for each net and both
noise width and noise height, and reports slack in terms of area. The
constraint types reported are constraints from the noise immunity
curve or from either the CLF or global threshold.

15-34
Example 15-2
Static Noise and Medium-Effort Model Report
--------------------------------------------------------------------------------------------------------------Astro Noise Report

Tool
: Astro
Version : W-2004.12 - Development for IA.32 - Nov 24,2004
Design : postroute
Date
: Tues Dec 7 15:04:42 2004
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Design Setup
Parasitics Source: from DB
Simulation Model : Medium Effort
Noise Type
: Static noise
Timing Window
: OFF
- Unit of Height: volt
Unit of Width: ns
Unit of Slack: volt *ns
--------------------------------------------------------------------------------------------------------------Net ranked by noise peak value --Noise region: above_low
Pin Name
Net Name
Width
Height
Slack
Constraint Type
--------------------------------------------------------------------------------------------------------------X2[26]
(X2[26])
7.7331e-01 3.5320e-01 -1.1847e-01 User Peak(0.180
)
W01[16]
(W01[16])
8.0540e-01 2.8470e-01 -6.8217e-02 User Peak(0.180
)
A1[30]
(A1[30])
6.9363e-01 2.8370e-01 -5.8056e-02 User Peak(0.180
)
S02[9]
(S02[9])
5.7654e-01 2.7982e-01 -4.6022e-02 User Peak(0.180
)
P4_9/D
(n13735)
1.1997e+00 2.7611e-01
3.5796e-01 * PX_COL0_reg_25_9/D
P3_9/D
(n13735)
1.1999e+00 2.7603e-01
3.5811e-01 * PX_COL1_reg_25_9/D
Y2[27]
(Y2[27])
9.8058e-01 2.7287e-01 -7.1452e-02 User Peak(0.180
)
X1[21]
(X1[21])
6.0651e-01 2.6695e-01 -4.0606e-02 User Peak(0.180
)
P2_2/D
(n9603)
1.1561e+00 2.6356e-01
3.6387e-01 * PX_COL1_reg_25_2/D
P1_2/D
(n9603)
1.1561e+00 2.6355e-01
3.6389e-01 * PX_COL0_reg_25_2/D
W11[16]
(W11[16])
5.3747e-01 2.4707e-01 -2.5299e-02 User Peak(0.180
)
X3[2]
(X3[2])
6.9722e-01 2.4069e-01 -2.8369e-02 User Peak(0.180
)
X3[26]
(X3[26])
8.2237e-01 2.3102e-01 -2.5507e-02 User Peak(0.180
)
X1[13]
(X1[13])
8.6051e-01 2.2319e-01 -1.9953e-02 User Peak(0.180
)
X1[10]
(X1[10])
5.7474e-01 2.1682e-01 -9.6686e-03 User Peak(0.180
)
X1[3]
(X1[3])
5.9634e-01 2.1510e-01 -9.0054e-03 User Peak(0.180
)
T02[22]
(T02[22])
7.9612e-01 2.0634e-01 -5.0445e-03 User Peak(0.180
)
X3[3]
(X3[3])
4.3117e-01 2.0323e-01 -1.3924e-03 User Peak(0.180
)
T02[5]
(T02[5])
6.6730e-01 2.0211e-01 -1.4097e-03 User Peak(0.180
)
W03[6]
(W03[6])
9.0837e-01 2.0092e-01 -8.3239e-04 User Peak(0.180
)
B2[1]
(B2[1])
4.3241e-01 2.0016e-01 -6.7404e-05 User Peak(0.180
)
X3[27]
(X3[27])
8.4552e-01 1.9856e-01
1.2156e-03 User Peak(0.180
)
T01[9]
(T01[9])
7.6675e-01 1.9644e-01
2.7323e-03 User Peak(0.180
)
U12332/I1
(n244)
1.0323e+00 1.9438e-01
4.0197e-01 * U12332/I1
U12350/I1
(n244)
1.0478e+00 1.8415e-01
4.1877e-01 * U12350/I1
U12346/I1
(n244)
1.0489e+00 1.8395e-01
4.1861e-01 * U12346/I1
W11[4]
(W11[4])
7.0308e-01 1.9240e-01
5.3416e-03 User Peak(0.180
)
X3[11]
(X3[11])
5.1425e-01 1.9211e-01
4.0556e-03 User Peak(0.180
)
G1[14]
(G1[14])
3.9013e-01 1.9207e-01
3.0945e-03 User Peak(0.180
)
W2[23]
(W2[23])
1.0975e+00 1.9162e-01
9.1923e-03 User Peak(0.180
)
X2[11]
(X2[11])
4.3029e-01 1.9027e-01
4.1851e-03 User Peak(0.180
)
--------------------------------------------------------------------------------------------------------------Net ranked by noise peak value --Noise region: below_high
Pin Name
Net Name
Width
Height
Slack
Constraint Type
--------------------------------------------------------------------------------------------------------------X2[26]
(X2[26])
1.2447e+00 4.9421e-01 -3.6622e-01 User Peak(0.180
)
A1[30]
(A1[30])
1.1312e+00 4.4447e-01 -2.7655e-01 User Peak(0.180
)
Y2[27]
(Y2[27])
1.2673e+00 4.3881e-01 -3.0266e-01 User Peak(0.180
)
W01[16]
(W01[16])
1.3908e+00 4.2386e-01 -3.1134e-01 User Peak(0.180
)
X1[13]
(X1[13])
1.3041e+00 4.2138e-01 -2.8869e-01 User Peak(0.180
)
S02[9]
(S02[9])
1.0185e+00 4.1144e-01 -2.1535e-01 User Peak(0.180
)
X3[26]
(X3[26])
1.3657e+00 4.1043e-01 -2.8738e-01 User Peak(0.180
)
T02[22]
(T02[22])
1.1919e+00 4.0261e-01 -2.4150e-01 User Peak(0.180
)
W11[16]
(W11[16])
9.4384e-01 3.9967e-01 -1.8846e-01 User Peak(0.180
)
X1[21]
(X1[21])
1.0735e+00 3.9800e-01 -2.1256e-01 User Peak(0.180
)
Analyzing Noise
15-35
X3[2]
(X3[2])
1.1876e+00 3.8483e-01 -2.1951e-01 User Peak(0.180
)
W2[23]
(W2[23])
1.4794e+00 3.8470e-01 -2.7323e-01 User Peak(0.180
)
T02[5]
(T02[5])
1.0612e+00 3.7406e-01 -1.8472e-01 User Peak(0.180
)
W03[6]
(W03[6])
1.4872e+00 3.7369e-01 -2.5831e-01 User Peak(0.180
)
X1[10]
(X1[10])
9.9837e-01 3.7121e-01 -1.7093e-01 User Peak(0.180
)
X3[27]
(X3[27])
1.3428e+00 3.6864e-01 -2.2645e-01 User Peak(0.180
)
W12[29]
(W12[29])
7.6932e-01 3.6719e-01 -1.2862e-01 User Peak(0.180
)
X3[11]
(X3[11])
8.4058e-01 3.6136e-01 -1.3564e-01 User Peak(0.180
)
W11[4]
(W11[4])
1.1435e+00 3.6112e-01 -1.8424e-01 User Peak(0.180
)
U12332/I1
(n244)
1.4355e+00 3.6010e-01
2.9597e-01 * U12332/I1
U12346/I1
(n244)
1.4434e+00 3.5695e-01
3.0319e-01 * U12346/I1
U12350/I1
(n244)
1.4453e+00 3.5591e-01
3.0606e-01 * U12350/I1
W12[30]
(W12[30])
1.0600e+00 3.5966e-01 -1.6924e-01 User Peak(0.180
)
U11953/I2
(n300)
1.4829e+00 3.5262e-01
3.0591e-01 * U11953/I2
U11967/I2
(n300)
1.4826e+00 3.5204e-01
2.9361e-01 * U11967/I2
U11972/I2
(n300)
1.4819e+00 3.5166e-01
3.0857e-01 * U11972/I2
T11[27]
(T11[27])
1.0891e+00 3.5075e-01 -1.6418e-01 User Peak(0.180
)
W02[7]
(W02[7])
4.5864e-01 3.4562e-01 -6.6788e-02 User Peak(0.180
)
T01[9]
(T01[9])
1.2582e+00 3.4520e-01 -1.8268e-01 User Peak(0.180
)
X3[7]
(X3[7])
8.3410e-01 3.4517e-01 -1.2109e-01 User Peak(0.180
)
X2[11]
(X2[11])
7.3832e-01 3.4050e-01 -1.0374e-01 User Peak(0.180
)
X3[3]
(X3[3])
7.7310e-01 3.3897e-01 -1.0744e-01 User Peak(0.180
)
G2[9]
(G2[9])
7.1740e-01 3.3677e-01 -9.8115e-02 User Peak(0.180
)
U10242/I2
(n99)
1.3390e+00 3.3607e-01
3.1825e-01 * U10242/I2
U10253/I2
(n99)
1.3399e+00 3.3576e-01
3.1244e-01 * U10253/I2
U10265/I2
(n99)
1.3399e+00 3.3575e-01
3.1573e-01 * U10265/I2
X3[8]
(X3[8])
1.7644e+00 3.3350e-01 -2.3555e-01 User Peak(0.180
)
A2[14]
(A2[14])
7.1324e-01 3.3343e-01 -9.5171e-02 User Peak(0.180
)
W12[20]
(W12[20])
1.0142e+00 3.3332e-01 -1.3521e-01 User Peak(0.180
)
X1[3]
(X1[3])
1.1170e+00 3.3260e-01 -1.4811e-01 User Peak(0.180
)
U7108/I2
(n1226)
1.1821e+00 3.3080e-01
3.9589e-01 * U7108/I2
U7647/I
(n1226)
1.1826e+00 3.2943e-01
2.0307e-01 * U7647/I
Y1[25]
(Y1[25])
7.3955e-01 3.2803e-01 -9.4682e-02 User Peak(0.180
)
T11[3]
(T11[3])
1.1896e+00 3.2802e-01 -1.5229e-01 User Peak(0.180
)
---------------------------------------------------------------------------------------------------------------
Generating Detailed Crosstalk Reports

Use the xtXTalkReport command to generate detailed crosstalk
reports that show in-depth crosstalk-related information on victim
nets and their respective aggressors, according to the options
selected in the Crosstalk Analysis dialog box. You can only generate
this report after you run the xtXTalkAnalysis command.
To generate detailed crosstalk reports,
1. Enter xtXTalkReport or choose Crosstalk > Crosstalk Report.
The Crosstalk Report dialog box appears.

15-36

Under Report, you can specify the nets whose crosstalk you are
interested in. You can select
- All Violations, to get information about all the nets with noise
exceeding the thresholds.
- Net Name and enter .* to get information about all nets (the
default), or enter net names to get information about one or
more nets.
You can select Pattern Match to specify a pattern to be used
for matching the names of multiple nets.
- Net Number to specify the number of nets to be reported (the
default is 200 nets).
Analyzing Noise
15-37
- Net Value >= to specify that the nets with noise levels equal to
or greater than the specified value be reported (the default is
0.35). The specified value is in terms of percentage of voltage.
Astro calculates noise height in terms of absolute voltage. The
threshold that is specified as a percentage of voltage is
therefore scaled so as to be represented as an absolute
voltage as well. For example, when you specify a threshold of
0.35 and the supply voltage is 1.2, the noise constraint shown
in the report is 0.420 (0.35 times 1.2).
By default, all top aggressor nets are reported, or you can enter
a number to specify a certain number of top aggressors to be
reported.
You can choose to output the report to a window or file. If you
select File, enter its name in the File Name box.
The detailed crosstalk report that xtXTalkReport generates
reports information about victim nets and their respective
aggressors. The crosstalk report is a more detailed report than the
one generated with xtXTalkAnalysis (see also Noise Analysis
Reports on page 15-31).
Example 15-3 is a sample detailed crosstalk report for static noise,
using the low-effort crosstalk circuit mode. An explanation of the
fields in the report follows the example.
Note:
Although Astro calculates timing windows for each aggressor
and victim net for each clock domain, the detailed crosstalk
report (xtXTalkReport) generated with the low-effort crosstalk
circuit model no longer prints timing window information.

15-38
Example 15-3
Static Noise and Low-Effort Model Detailed Report
Net X2[26] of cell (TCS15) ** Violated (noise)

Ctotal(R:F)
Ccouple
PeakNoise(R:F)
(0.012233:0.012233) 0.008412
(0.454185:0.568789)
Aggressor list :
(Type)Netname
(n)X1[9]
(n)X1[31]
(n)X2[20]
(n)X1[28]
(n)n685
(n)n708
Cc
0.002991
0.002908
0.000732
0.000587
0.000632
0.000563
Driver
MUX4ND1
MUX4ND1
MUX4ND1
MUX4ND1
MUX2ND1
MUX2ND1
Driver
MUX4ND0
IndividualPeak(R:F)
(0.168236:0.205024)
(0.165795:0.200029)
(0.037914:0.049062)
(0.033657:0.040426)
(0.026136:0.039489)
(0.022448:0.034759)
Filtered(R:F)
(N:N)
(N:N)
(N:N)
(N:N)
(N:N)
(N:N)
The format of the crosstalk report is as follows:

For victim nets,
Net precedes the name of the net for which the subsequent
information applies.
In many of the following fields, you see a pair of numbers

separated by a colon (:); the former is for a rise condition, and the
latter is for a fall condition.
Ctotal(R:F) is the total capacitance of the victim net, including

wire and pin capacitance.
Ccouple is the total coupling capacitance between the victim net

and its aggressors.
PeakNoise(R:F) is the induced peak noise voltage (for static

noise, the absolute noise voltage; for switching noise, the
percentage of VDD). The calculation for rise considers the victim
at steady-state low and the aggressors switching from low to
high. The calculation for fall considers the victim at steady-state
high and the aggressors switching from high to low.
Driver is the cell master name for the driver of the victim net.
Analyzing Noise
15-39
For each aggressor listed on the aggressor list,
Cc is the coupling capacitance between this aggressor and the

victim net
Driver is the cell master name of the aggressor driving cell
IndividualPeak(R:F) is the noise contribution of this

aggressor
Example 15-4 is a sample detailed crosstalk report for static noise,

using the medium-effort crosstalk circuit mode. An explanation of the
fields in the report follows the example. For static noise, the format is
similar to the detailed report generated by PrimeTime SI. For
switching noise, the report format is the same as that generated with
the low-effort crosstalk circuit model.
Example 15-4
Static Noise and Medium-Effort Model Detailed Report
**************************************************************************
Report : noise_calculation
-to X2[26]
Design : TCS15
Version: W-2004.12-SP1
Date
: Fri Feb 4 14:03:52 2005
**************************************************************************
Region
: above_low
Victim driver pin
: U12343/ZN
Victim driver library cell : MUX4ND0
Victim net
: X2[26]
Driver voltage swing
: 0.90
Noise calculations:
Attribute:
E - aggressor is excluded by user
Y - aggressor is filtered by timing window or elec. filtering
Height Width
Area
Attribute
---------------------------------------------------------------Aggressors:
X1[9]
0.0163 1.1162
0.0091

15-40
X1[31]
X2[20]
X1[28]
n685
n708
0.0259
0.0191
0.0290
0.1282
0.1315
0.7293
1.0720
0.8329
0.7303
0.7432
0.0095
0.0102
0.0121
0.0468
0.0489
Total:
0.3500
0.7802
0.1365
Noise slack calculation:

Constraint type: User Specified Noise Peak
Height
Area
----------------------------------------------------------------Required
0.1800
(0.1800 * 0.7802)Actual
0.3500
(0.3500 * 0.7802)
----------------------------------------------------------------Slack
-0.1700
-0.1326
The report prints information for each pin. The format of the crosstalk
report is as follows:
Region indicates whether the noise violations that are caused

by aggressor net transitions are above_low or below_high.
Victim driver pin indicates the pin driving the victim net.
Victim driver library cell indicates the cell master of

the cell instance driving the net.
Victim net indicates the victim net name.
Driver voltage swing indicates the power supply voltage for

the cell instance driving the net.
Noise calculations lists each of the aggressor nets and

reports the noise height, width, and area on the victim net for that
aggressor. It also reports whether an aggressor net is filtered
outY in the Attribute column indicates an aggressor net is
either filtered by the timing window or the electrical filter
Analyzing Noise
15-41
thresholds you specify in the Xtalk page of the AstroTime Timing

Setup dialog box (atTimingSetup). No notation indicates an
aggressor net is not filtered out.
Total lists the accumulated noise height, width and area. The
total for height and area is the sum of the values listed in their
respective columns. The total for width is not the sum of the
values in the Width columnit is the width of the composite
waveform, which is the accumulated effect of noise from each
aggressor net.
Noise slack calculation reports the required height and

area as well as the actual height and area.
- The required height is either the constraint from the library or
the noise threshold you specify in the Xtalk page of the
AstroTime Timing Setup dialog box (atTimingSetup).
- The required area is calculated as follows:
required height * width of the composite waveform
where the width of the composite waveform is the total width
from the Noise calculations section.
- The actual height is the total height from the Noise
calculations section and, likewise, the actual area is the total
area from the Noise calculation section.
Slack reports the slack height and area calculation.
- The noise height slack is calculated as follows:
required height actual noise height
- The noise area slack is calculated as follows:
required area (actual noise height * total width)

15-42
Displaying Crosstalk Analysis Results

You can use the xtXTalkDisplayNet command to evaluate noise
analysis results by displaying nets that are being diagnosed. If you
keep the command defaults, the net under diagnosis appears in
white, and the first seven neighboring nets that contribute most to the
crosstalk metric of the current victim net appear in other colors.
To display crosstalk analysis for specific nets,
1. Enter xtXTalkDisplayNet or choose Crosstalk > Display
Crosstalk Results.
The Display Net Crosstalk dialog box appears.
Analyzing Noise
15-43
2. Next to Net Name, specify the name of the net for which the
crosstalk analysis results are to be displayed.
3. Select Show P/G Bus to display power and ground buses (when
they are aggressor nets) for the named net. Power and ground
buses are usually viewed as quiet nets and provide some
shielding from neighboring wires.
4. Choose whether to display the analyzed net and how many
neighboring nets to display (the default is 17). Also, you can
change the display colors or keep the defaults. Select Flash to
display them more clearly.
The graphics window is zoomed in to the bounding box of the
victim net and the selected nets are colored and/or flashing. The
display is accompanied by a report (in the application window)
that shows the noise values contributed by each aggressor net.
Generating Stage Delay Reports

Use the xtDumpStageDelay command to write the stage delay
information for the design to an output file. This information can be
used to check the correlation between Astro and PrimeTime SI.
You must run a timing command, such as astReportTiming, to
put the Astro timer in standby mode before you run
xtDumpStageDelay.
The syntax is
xtDumpStageDelay filename

15-44
Sample Report
Following is the sample stage delay report:
---------------------------------------------------------- Astro Stage Delay Report
- Tool : Astro
- Version : W-2004.12-SP1_rel-Development for SUN.32 -Mar 16, 2005
- Design : add16
- Date : Wed Mar 16 15:50:14 2005
- Timer : Xtalk effect is ON, DeltaTransScaling Factor = 0.00
- : Store Delta Trans and Delay is ON
- Format : Delay for stage stage_chain is:
(rise_min rise_max) (fall_min fall_max)
- Stage Delay Includes Both Cell Delay and Net Delay
- If Xtalk Effect is ON, Stage Delay is Normal Delay + Delta
Delay
---------------------------------------------------------Delay for stage buf_clk/andclk/A -> buf_clk/Z -> ffa0/CP is:
(0.0000 0.0000) (0.0000 0.0000)
Delay for stage buf_clk/andclk/A -> buf_clk/Z -> ffa1/CP is:
(0.0000 0.0000) (0.0000 0.0000)
Delay for stage ffa13/CP -> ffa13/Q -> xadd13/an4/B is:
(0.1643 0.4572) (0.1721 0.4516)
Delay for stage ffa13/CP -> ffa13/Q -> xadd13/xo1/B is:
(0.1643 0.4572) (0.1721 0.4516)
Delay for stage ffa13/CP -> ffa13/Q -> xadd13/an3/A is:
(0.1642 0.4571) (0.1720 0.4515)
Delay for stage ffb12/CP -> ffb12/Q -> xadd12/an4/C is:
(0.1704 0.4500) (0.1731 0.4486)
Generating Delta Transition Delay Reports

Use the xtDumpDeltaTransDelay command to write the normal
slew, delta slew, and crosstalk-induced slew for each pin and port of
the design to an output file. This data can be used to check the
correlation between Astro and PrimeTime SI. The syntax is
Analyzing Noise
15-45
xtDumpDeltaTransDelay filename
Consider whether to select Enable Crosstalk Effects in the

Environment page of the AstroTime Timing Setup dialog box
(atTimingSetup) before you run xtDumpDeltaTransDelay. If
you do not select this option, the delta slew will be zero and the
crosstalk-induced slew will be the same as the normal slew.
You must run a timing command, such as astReportTiming, to
put the Astro timer in standby mode before you run
xtDumpDeltaTransDelay.
Sample Report
Following is the sample delta transition report:
---------------------------------------------------------- Astro Delta Transition Report
- Tool : Astro
- Version : W-2004.12-SP1_rel-Development for SUN.32 -Mar 16, 2005
- Design : add16
- Date : Wed Mar 16 16:17:52 2005
- Timer : Xtalk effect is ON, DeltaTransScaling Factor = 0.00
- : Store Delta Trans and Delay is ON
- Format : pin_name : ((rise_min)(fall_min))
((rise_max)(fall_max))
- rise_min
- fall_min
- rise_max
- fall_max := normalTrans:deltaTrans:annotatedTrans
-

15-46
---------------------------------------------------------ffb15/CP : ((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
ffb15/D : ((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
ffb15/Q : ((0.1549:0.0000:0.1549)(0.0989:0.0000:0.0989))
((0.3612:0.0000:0.3612)(0.2237:0.0000:0.2237))
ffb15/QN : ((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
ffa15/CP : ((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
ffa15/D : ((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
ffa15/Q : ((0.1541:0.0000:0.1541)(0.0985:0.0000:0.0985))
((0.3580:0.0000:0.3580)(0.2218:0.0000:0.2218))
ffa15/QN : ((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
((0.0000:0.0000:0.0000)(0.0000:0.0000:0.0000))
xadd14/Z : ((0.1552:0.0000:0.1552)(0.1176:0.0000:0.1176))
((0.3681:0.0000:0.3681)(0.2691:0.0000:0.2691))
xadd12/B : ((0.0635:0.0000:0.0635)(0.0503:0.0000:0.0503))
xadd12/B : ((0.0635:0.0000:0.0635)(0.0503:0.0000:0.0503))
((0.1592:0.0000:0.1592)(0.1157:0.0000:0.1157))
Analyzing Crosstalk-Induced Delay Shift

Crosstalk affects the timing of the design when any of the aggressors
switch before the transition of the victim signal has finished. When
the aggressor and the victim are switching in the same direction, the
victim driver can expend less effort on charging the coupling
capacitance and more on increasing the switching speed. This can
lead to hold-time problems. On the other hand, when the aggressor
and victim switch in opposite directions, the transition time of the
victim is longer because of a larger effective capacitance, and the
result is likely to be setup-time problems. Therefore to accurately
analyze the timing behavior of a circuit, it is necessary to take into
consideration the effects of crosstalk.
Analyzing Noise
15-47
Astro-Xtalk analyzes the impact on interconnect timing in terms of

propagation delay and transition time. The delay shift of a victim net
depends on the arrival time window of its aggressors and also affects
the net timing windows. During crosstalk-induced delay, Astro-Xtalk
takes into account the timing windows of the victim and aggressor
nets. For an accurate idea of the true delay shift, you must do
iterations between the timing propagation in the static timing
analyzer and the net delay calculation, with crosstalk considered.
There are two ways to run crosstalk-induced delay shift analysis:
Output a timing report that considers crosstalk
Output a crosstalk-induced Standard Delay Format (SDF) file
Generating a Timing Report That Considers Crosstalk

You generate a timing report with the astReportTiming
command. To generate a report that considers crosstalk, first select
Enable CrossTalk Effects in the Environment page of the AstroTime
Timing Setup dialog box (atTimingSetup).
To generate a timing report that considers crosstalk,
1. Enter astReportTiming or choose Timing > AstroTime
Timing Report.
The Timing Report dialog box appears.

15-48
2. Select Report Delta Delay/Trans, to print the delta delays and

delta transition times caused by crosstalk.
When this option is selected, three columns are added to the
timing reportthey show the delta delay, delta transition, and
accumulated delta delay for each path.
Analyzing Noise
15-49
Note:
By default, the crosstalk effect on transitions not considered with
the low-effort crosstalk model. To see the crosstalk effect, as well
as the propagation of the crosstalk effect on the transition time,
you can use the xtDeltaTransScale parameter. The syntax is
axSetRealParam "xt" "xtDeltaTransScale"value
where value is between 0.000 and 1000.0000. The default is

0.000
The scaling factors are considered only with the low-effort
crosstalk circuit model.
Generating a Crosstalk-Induced Standard Delay Format

File
To output a crosstalk-induced SDF file,
1. Enter ataDumpSDF or choose Timing > Delay Output SDF Out.
The SDF Write dialog box appears.

15-50
2. Under Operation Mode, select Crosstalk-Induced SDF.

The Crosstalk-Induced SDF Options area becomes active.
3. In the Crosstalk-Induced SDF Options area, select options or
keep defaults.
To know the effects of crosstalk on delay, specify the number of
iterations between the crosstalk analyzer and the timer
(Astro-Xtalk changes timing windows, which, in turn, changes
Analyzing Noise
15-51
how much crosstalk a net receives). The default for Number of

Iterations is Until Converge, meaning that the timer runs until
convergence is achieved. However, you might want the timer to
run for only a certain number of iterations, for runtime or other
reasons, in which case you specify how many iterations you
need.
Astro-Xtalk performs a delay shift analysis for each net, using
Asymptotic Waveform Evaluation (AWE)-based techniques, with
all the different driving conditions considered, while taking into
account the arrival time windows of all aggressors. The
calculated delays are then fed back into the timer for iterations,
depending on the options you have selected. The results are
written to an SDF file.
For descriptions of all the ataDumpSDF command options, see
Note:
If you use a parasitic view to do timing analysis with crosstalk,
make sure Store coupling mesh is selected in the Generate
Parasitic View dialog box (astGenPV). See also Creating
Parasitic Views on page 13-13.

For best results, use the crosstalk prevention and analysis
processes in conjunction with crosstalk fixing. When crosstalk is
prevented in the placement stage and then in the global routing and
track assignment stages, the routed design will have a smaller
number of crosstalk violations. Consequently crosstalk fixing in the

15-52
postrouting optimization stage will be more effective and have a

shorter runtime. Once the design is detail routed, you should resolve
any timing and congestion issues before trying to fix crosstalk
violations.
Some crosstalk violations might still remain unfixed after you run the
noise avoidance processes that occur in the global routing and track
assignment phases. These violations are detected after you run the
xtXTalkAnalysis command.
Astro fixes the remaining crosstalk violations in the postrouting
optimization stage of the design flow. The preferred methodology is
to use the astPostRouteOpt command. Alternatively, you can use
the stand-alone axgAdvRouteOpt command.
Another approach is to use timing-driven spacing constraints and
isolation constraints to fix crosstalk violations.
You might choose to use the astXTalkFix command, which by
default attempts to repair all violations that can be fixed by sizing. At
the same time, it attempts to minimize the setup time. This command
provides the capability to run a high-level ECO flow, where static and
switching crosstalk noise is fixed based on input from PrimeTime SI.
Fixing Crosstalk With astPostRouteOpt

Use the astPostRouteOpt command to fix crosstalk violations on
a detail-routed design (the recommended flow) or on a design that
has track assignment. For the latter, after you perform detail routing,
use astPostRouteOpt again, to fix violations on the now
detail-routed design.

15-53
Before running astPostRouteOpt, select Enable CrossTalk

Effects in the Environment page of the AstroTime Timing Setup
dialog box (atTimingSetup). When you select this option,
astPostRouteOpt optimizes for crosstalk-induced delay. To
optimize for static noise violations, you need to select Crosstalk
Noise Violations in the Post Route Optimization dialog box. The
astPostRouteOpt command can fix static noise violations with or
without selecting Enable Crosstalk Effects.
When you run astPostRouteOpt, you can choose the effort level
to be used during optimization (low, medium, or high). Depending on
the effort you select in the Post Route Optimization dialog box, the
astPostRouteOpt does the following in the crosstalk fixing flow:
Low optimization effort Runs one phase of optimization that

attempts to fix setup violations, transition and hold violations, and
noise violations, followed by the ECO routing process.
Medium optimization effort Runs a phase of optimization that

attempts to fix setup violations, transition and hold violations, and
noise violations, followed by in-routing optimization that performs
RC reduction. Then runs another phase of optimization to fix
setup violations, transition and hold violations, and noise
violations, followed by the ECO routing process.
High optimization effort Same as the medium optimization

effort, except it sizes both the aggressors and victims during
setup optimization (the medium effort sizes victims only).
To fix crosstalk violations during postrouting optimization,

1. Enter astPostRouteOpt DR or choose Route > Detail Route
Detail Route Placement/Route Optimization.

15-54
Figure 15-2 Post Route Optimization Dialog Box

15-55
2. Make sure the Detail Route routing phase is selected.

3. Select the options or keep defaults that are appropriate for the
detail routing optimization.
Select Crosstalk Noise Violations (in the Optimization Mode
area) to specify that static noise violations are to be fixed.
For descriptions of the astPostRouteOpt command options,
see Performing Postrouting Optimization on page 11-4 or
Fixing Crosstalk With axgAdvRouteOpt

You can use the axgAdvRouteOpt command to optimize the timing
and crosstalk on a fully routed design, based on the detail routing
results. Note that the preferred methodology is to use
astPostRouteOpt.
The axgAdvRouteOpt command works only on detail-routed or
track assigned designs that include all the necessary timing
information. This command concurrently optimizes timing, transition,
capacitance, and crosstalk by changing routing topology, sizing cells,
and inserting buffers.
Before running axgAdvRouteOpt, select Enable CrossTalk Effects
in the Environment page of the AstroTime Timing Setup dialog box
(atTimingSetup).
To fix crosstalk violations during advanced routing optimization,
1. Enter axgAdvRouteOpt.

15-56
The Advanced Route Optimization dialog box appears.
2. Under Optimization Mode, select Crosstalk Noise Constraints.

3. Under Optimization Operations, select the operations you want to
be run, such as Buffer Insertion/Bypass, for crosstalk fixing as
well as for timing optimization.
For descriptions of all the axgAdvRouteOpt command options,
see Using axgAdvRouteOpt on page 11-21 or Physical

15-57
The router computes noise, by using the same crosstalk model

the analyzer uses, checks the computed values against the
specified constraints. The router attempts to minimize the
crosstalk violations by rerouting either the aggressor or the victim
nets.
Note:
The runtime for axgAdvRouteOpt can be considerable. You
can control the runtime by setting a runtime limit in the
Advanced Route Optimization dialog box.
Because the specified time limit can stop axgAdvRouteOpt
at an unknown place during the search-and-repair process,
make sure you run search and repair immediately after using
this parameter.
Using Spacing and Isolation Constraints to Fix

Crosstalk Violations
In addition to fixing crosstalk by running postrouting optimization,
you can fix crosstalk violations on certain nets by specifying that
Astro is to route them with additional spacing. The additional spacing
can be between the net and another net, or all other nets. Do this by
defining timing-driven spacing constraints or isolation constraints.
Set a timing-driven spacing constraint on a net to direct the router

to isolate the net from other nets. This reduces the crosstalk
effect on the net. Use the dbAssignNetTimingSpacing
construct. The syntax is
(dbAssignNetTimingSpacing (geGetEditCell) '( "<netname>" ))

15-58
Set a net isolation constraint on a pair of nets to direct the router

to space the two nets. This reduces the crosstalk effect of one on
the other. Use the dbSetNetXtalkAggressorList construct.
The syntax is
(dbSetNetXtalkAggressorList (geGetEditCell)
"<victim netname>" '( "<aggressor1>"
"<aggressor2>" ...))
After you specify the constraints, do the following:

1. Load the text file containing the constraints.
2. Set signal routing options by entering
axgSetHPORouteOptions or choosing Route Setup > HPO
Signal Route Options.
The HPO Signal Route Options dialog box appears.

15-59
Select user nets (under Timing-Driven Spacing).

3. Run search-and-repair to reroute the constrained nets so that
they meet the constraints.
Make sure you check the results.
Fixing Crosstalk With astXTalkFix

Use the astXTalkFix command to fix crosstalk violations on
routed designs by sizing the drivers of victim and aggressor nets
without inserting buffers. (You can specify that buffers be inserted by
deselecting Gate Sizing Only in the XTalk Fix dialog box.)
By default, the astXTalkFix command attempts to repair all
violations that can be fixed by sizing; at the same time, it attempts to
minimize the setup time.
You can use the astXTalkFix command in a high-level
engineering change order (ECO) flow, where it can reduce static and
switching crosstalk noise and even stage delay in the
postroute-optimized cell based on input from PrimeTime SI. The
input file is a Tcl-encoded binary file generated by PrimeTime SI.
The file contains the following:
The information needed to exchange the timing and noise

information between Astro and PrimeTime SI.
The constraints for a target reduction percentage.

Constraints can be generated to fix set up, hold, and noise in
PrimeTime SI, and then be passed to Astro.

15-60
To fix crosstalk noise in a high-level ECO flow,

1. Enter astXTalkFix.
The XTalk Fix dialog box appears.
2. Set options or keep defaults.

3. Select User Specified Noise, to fix static and switching crosstalk
noise based on information that is specified in the named file. You
must first select Do Optimization From File to activate the File
Name box, and enter the name of the file that was generated by
PrimeTime SI.
4. Click OK.
The astXtalkFix command fixes the nets or port instances or
paths in the order of their appearance in the input file.

15-61
Calculating Noise During Routing

To ensure noise convergence, the router has to be capable of
evaluating the noise on the fly to make correct routing decisions. This
is achieved by an in-routing parasitic extraction and the common
noise analysis engine. The built-in parasitic extraction engine
supports the TLU and TLUPlus capacitance models.
Performing Crosstalk Optimization During Search and

Repair Routing
It can be useful to run advanced routing optimization
(axgAdvRouteOpt) in crosstalk-only mode at the end of the design
flow when you need to run minor routing steps on a design that
already meets timing and crosstalk requirements. The additional
steps need to consider crosstalk, for routing purposes only, to
prevent the creation of new crosstalk violations. The recommended
flow includes these major steps:
1. Get 0 design rule check violations after running search and repair
with crosstalk off.
2. Run the axgAdvRouteOpt command without crosstalk, to
optimize timing (if timing is significantly off).
3. Run crosstalk analysis (xtXTalkAnalysis), followed by the
axgAdvRouteOpt command with crosstalk, to optimize timing
and crosstalk.
You can run the axgAdvRouteOpt command without trying to
improve setup times so that the optimizations concentrate only
on crosstalk violations.

15-62

Astro-Xtalk uses the low-effort and medium-effort crosstalk circuit
models to analyze noise. You can select the effort to be used in the
Xtalk page of the AstroTime Timing Setup dialog box (see Xtalk
Page on page 6-45).
The input for these crosstalk circuit models, as well as the data they
generate, differs. An overview of these differences follows.
For low effort is
For medium effort is
Coupling capacitance
Lumped
2-pi or 3-pi model
Noise immunity curve
Not used
Used
I-V curve
Used
Used
Scaling factors (delta

transition and delta
delay)
Used
Not used
Noise height
Computed
Computed
Noise width
Estimated
Computed
Noise slack
Noise height used
Noise height and noise width

used
Delta transition
Scaled to 0 by default
Computed
Delta delay
Based on lumped noise
Computed
Analysis on clock net
Computed
Computed
Optimization
Default
Not used
Analysis
Default
Used

15-63
Low-Effort Crosstalk Circuit Model

The low-effort crosstalk circuit model, as depicted in Figure 15-3, is
used to analyze the crosstalk severity.
Figure 15-3 The Low-Effort Crosstalk Circuit Model
Tf
Va
Cx
Ca
Vv
Rv
Cv
In Figure 15-3, Ca, Cv, and Cx are the pull-up (pull-down)

capacitances of the aggressor net a, the victim net v, and the
coupling capacitance between nets a and v, respectively; Rv is the
pull-down (pull-up) resistance of the driver of net v. Ra (shown in the
following formula) is the equivalent driving resistance of net a driven
by a step voltage source.
Assuming that the supply voltage is VDD and that the driver does not
suffer from voltage drop, the peak noise voltage Vvmax on the victim
net is bounded by
VDD
V vmax = --------------------------------------------------------Cv Ra
C a
1 + ------ + ------ 1 + ------
Cx R v
C x
For more information about the derivation of the previous formula,
see A. Vittal and M. Marek-Sadowska, Crosstalk Reduction for
VLSI, IEEE Trans. on Computer-Aided Design, pages 290-298, no.
3, 1997.

15-64
For each signal net, Astro-Xtalk finds all of its neighboring

(aggressor) nets and uses one or more of the following methods to
evaluate the above noise expression to identify those that have noise
problems, depending on your preferences:
Noise: Uses the true values of Ra and Rv to calculate the noise

voltage.
The peak noise voltages from all aggressor nets are summed up
as the worst-case noise the victim net can ever receive and are
used as the noise susceptibility metric.
Timing window consideration: The aggressors of a signal net do

not usually switch at the same time, so simply adding the noise
contributions from all aggressors overestimates the actual
scenario. One way to find a more realistic noise boundary is to
use the arrival time windows of the aggressor nets. The arrival
time window is obtained from static timing analysis and shows
the fastest and slowest signal net switches, with reference to the
start of a clock cycle, due to different operating conditions and
signal propagation paths. In the timing window ON mode,
whether or not the aggressor noises are added together depends
on whether or not they have overlapping timing windows. The
effective peak noise can be much smaller than simple peak
noise, especially for victims with long wires that can couple to
many nets with disjointed timing windows.
To enable timing window consideration, select Include Timing
Window in the Xtalk page of the AstroTime Timing Setup dialog

15-65
Medium-Effort Crosstalk Circuit Model

The medium-effort crosstalk model uses the 2-pi or 3-pi model to
represent RC networks. A typical schematic of the medium-effort
crosstalk circuit model is shown in Figure 15-4.
Figure 15-4 The Medium-Effort Circuit Model
Cc
Vx(t)
In Figure 15-4, the aggressor net at the top is coupled with the victim
net at the bottom, with coupling capacitance equal to Cc.
Compared to the low-effort crosstalk model, the medium-effort
crosstalk model provides better accuracy at the cost of longer
runtime. The medium-effort crosstalk model performs more detailed
RC modeling, and it utilizes a topology-sensitive coupling
capacitance Cc. The latter feature means that the coupling strength
is not only related to the value of Cc, but also to the values of the
resistors on the left and right sides of Cc.
A closed-form formula can be derived for Vx(t). Noise and delta delay
based on the waveform of Vx(t) can be obtained.

15-66
16
Signal Integrity: Signal and Cell
Electromigration
16
The Astro-Xtalk tool analyzes signal electromigration, and to ensure

integrity, generates a repair file for nets that violate the current
constraints. It also checks cell electromigration.
About Signal and Cell Electromigration Analysis
Preparing Data for Signal Electromigration Analysis
Performing Signal Electromigration Analysis
Repairing Electromigration Violations
Verifying Electromigration Analysis Results
Performing Cell Electromigration Analysis
16-1
Examples of Signal Electromigration Constraints Processed in

ALF Files
Examples of Scripts
For information about crosstalk prevention, analysis, and fixing, see

Chapter 15, Signal Integrity: Crosstalk Prevention, Analysis, and
Fixing.
Chapter 16: Signal Integrity: Signal and Cell Electromigration

16-2

The use of smaller line widths and higher operational speeds in IC
designs causes an increase in current density that can result in
electromigration problems. Electromigration can lead to shorts or
opens due to the displacement of ions caused by the flow of
electrons. You can use Astro to analyze, correct, and prevent
electromigration in your design.
You can perform signal electromigration analysis by using the
xtSignalEM commandit calculates the current density of each
net and generates a repair file for nets that violate the current
constraints. Additionally, you can use the xtCellEM command to
check cell electromigration.
You use the xtSignalEM command at the prerouting stage to
analyze and prevent electromigration, and at the postrouting stage to
analyze and repair electromigration.The repair file that xtSignalEM
generates contains variable routing rules that are based on
wire-sizing techniques. In the prerouting stage, you load the repair
file, and the router uses the rules to guide the router during detail
routing. In the postrouting stage, you load the repair file and run the
search-and repair process to reroute violating nets. In either case,
violations should be removed. Typically, signal electromigration
analysis at the prerouting stage is more conservative than at the
postrouting stage.
See also Sample Script for Running Signal Electromigration
Analysis and Fixing on page 16-37 and Sample Script for Running
Signal Electromigration Analysis and Prevention on page 16-39.

16-3

Before you perform signal electromigration analysis with the
xtSignalEM command, you need to prepare certain file data.
Defining Current Units in the Technology File

Make sure units and precision of current are defined in your
technology file. If the units are not defined, add the following in the
header section of your technology file:
unitCurrentName = "mA"
currentPrecision = 10000
Loading Signal Electromigration Constraints

Input constraints by loading an Advanced Library Format (ALF) file
of signal electromigration constraints into your design library (or
reference library) or by defining them in the Synopsys .plib format.
To load the signal electromigration constraints from an ALF file,
1. Enter auAlfToDB or choose Tools > Data Prep > CLF > ALF To
DB.
The ALF Loader dialog box appears.

16-4
2. Enter the name of the ALF file to be loaded in the ALF file name
box.
3. Enter the name of the library that is specified in the ALF file in the
Library Name box.
If the library name in the ALF file is inconsistent with the design
library name, the library name you enter here has precedence.
Note:
Do not have the design library open when you load the ALF file.
You can write the loaded constraints by using the auDumpALF
command (or choosing Tools > Data Prep > CLF > Dump ALF). For
descriptions of the auDumpALF command options, see Physical
You can purge the constraints by using the auPurgeSIOfALF
auPurgeSIOfALF "library_name"
Here is a sample ALF file that includes signal electromigration layer

constraints. Usually the ALF file can be obtained from the foundry.

16-5
LAYER metal1 {
PURPOSE = routing ;
LIMIT {
CURRENT absavg_limit {
MEASUREMENT = absolute_average;
MAX { HEADER {
TEMPERATURE { TABLE { 50 75 90 100 115 160 195 } }
WIDTH { TABLE { 0 1 } }
} TABLE { 0
0
0
0
0
0
0
6.6773 4.4319 2.2734 1.11 0.80589 0.65571 0.33536 } }
}
CURRENT avg_limit {
MEASUREMENT = average;
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
6.6773 4.4319 2.2734 1.11 0.80589 0.65571 0.33536 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
42.558 33.154 21.764 12.8 6.9554 3.3834 2.3212 } }
}
CURRENT peak_limit {
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
88.95 66.96 44.54 23 16.304 8.784 4.392 } }
}
}
}
See also Examples of Signal Electromigration Constraints

Processed in ALF Files on page 16-30.

16-6
Loading the Power Supply

You must define the power supply voltages for all the power nets in
your design (the current depends on the voltage magnitude). If your
reference libraries contain LM views, the information is usually
provided in the LM view. If your reference libraries contain only TIM
views, define the power voltages for each net in an ASCII file by using
one or more tdfSetPowerSupply commands, and then use the
poLoadPowerSupply command to load the file.
The syntax is
tdfSetPowerSupply "netName" minValue nomValue maxValue
Note:
When you use LM views and you define power supply information
with tdfSetPowerSupply commands, the xtSignalEM
command will only use the tdfSetPowerSupply definitions if it
fails to find power supply information in the LM views.
To load the ASCII file that contains power supply information,
1. Enter poLoadPowerSupply or choose Power > Data
Preparation Load Power Supply.
The Load Power Supply dialog box appears.

16-7
2. Next to TDF File Name, enter the name of the TDF file containing
the power supply information.
Save the cell to save the loaded power supply information.
Here is a sample TDF file:
tdfSetPowerSupply "VDD" 1.8
Loading Net Switching Information

You must define net switching information to be able to perform
accurate electromigration analysis (the more frequently a net
switches, the more susceptible it is to electromigration). Use the
poLoadNetSwitchingInfo command to load net switching
information.
Consider the following points:
When no switching activity is defined, the signal net is assumed

to have the same switching frequency as the clock.
Clock period is defined in the SDC file, and clock period is used
in the current calculation. When no real clocks are defined, Astro
assumes 100 MHz for the virtual clock.
You can define net switching activities in any of the following formats:
A Scheme file
A value-change dump (VCD) file

16-8
VCD is a standard Verilog output format that prints the time and
value information whenever a monitored net experiences a value
change. VCD files can be parsed into time frames for performing
frame-by-frame analysis or lumped as average net switching
activities.
A switching activity interchange format (SAIF) file
To load net switching activity information:

1. Enter poLoadNetSwitchingInfo or choose Power > Data
Preparation Load Net Switching Activity.
The Load Net Switching Activity dialog box appears.

16-9

16-10

Next to File Name, enter the file names of the Scheme, VCD, or
SAIF files that contain the net switching activities.
For descriptions of all the poLoadNetSwitchingInfo
Save the cell to save the loaded switching activity information.
Scheme Examples
To assign a single switching activity value to every net, use the
following syntax:
defineNetSwitchingActivity (geGetEditCell) ".*" 0.2
In this example, the ".*" pattern matching capability specifies all net
names, and 0.2 specifies the net switching activity. The 0.2 value is
the number of switches or toggles (rise plus fall) per unit of time, as
defined in the unitTimeName parameter of your technology file. For
example, if unitTimeName is defined as ns, 0.2 corresponds to 100
MHz because 0.2 means it toggles twice (one rise plus one fall)
every 10 ns.
Usually you can determine the value to be used in the
defineNetSwitchingActivity command by assuming at what
percentage of the clock frequency the nets are switching. For
example, to calculate the number to be assigned when you want a
net switching activity at 20 percent of the clock frequency that is set
at 125 MHz, where the unit of time is ns, use either of these two
equivalent methods:

16-11
The frequency value of 125 MHz is 0.125 (1/ns), meaning the

value is
(20 %) * (2 toggles) * 0.125 (1/ns) = 0.2 * 2 * 0.125 = 0.05 (1/ns)
A frequency of 125 MHz corresponds to a period of 8 ns,

meaning the value is
(20%) * (2 toggles) / (period) = 0.2 * 2 / (8 ns) = 0.05 (1/ns)
You can define as many different switching activities as you want in

the file, as shown in the following sample Scheme file:
defineNetSwitchingActivity
(geGetEditCell)
(geGetEditCell)
(geGetEditCell)
(geGetEditCell)
(geGetEditCell)
(geGetEditCell)
(geGetEditCell)
".*" 0.2
"A/.*" 0.3
"A/a/.*" 0.4
"B/.*" 0.5
"B/b/.*" 0.6
"clk.*" 0.7
"clk" 0.8
When you load this switching activity in a Scheme file, Astro does the
following:
First, assigns a switching activity of 0.2 to every net in the design.
Then assigns a switching activity of 0.3 to nets with names that

start with A/ (the value of 0.2 is overwritten).
Similarly, assigns a switching activity of 0.4, 0.5, and 0.6 to nets

with names that start with A/a/, B/, and B/b/, respectively.
Assigns a switching activity of 0.7 to all nets with names that start
with clk.
Assigns a switching activity of 0.8 to the net specifically named

clk.

16-12
The last two lines show that you can assign different switching
activities to nets that belong to different clock domains, based on the
patterns of the net names.

Use the xtSignalEM command to perform signal electromigration
analysis for each net by calculating the current on every edge with
Asymptotic Waveform Evaluation (AWE) and comparing this data
with current library-defined thresholds. Violations, as well as
information such as operating temperature, are listed in the analysis
report that xtSignalEM produces. The xtSignalEM command
also generates a repair file of variable routing rules that can be
loaded into the database and used during the search-and-repair
process to fix signal electromigration problems.
The xtSignalEM command honors the parasitic definitions that
you set in the Parasitics page of the AstroTime Timing Setup dialog
box (atTimingSetup) (see Parasitics Page on page 6-38).
Before running xtSignalEM, you can set the parasitic source to
LPE in the Parasitics page. If you select DB or DB_then_LPE, make
sure that you generated the parasitic view with geometry
information.
Remember that, before using xtSignalEM, you must load signal
electromigration constraints into your design library (or reference
library) from an ALF file or define them in the Synopsys .plib format.
To run signal electromigration analysis,
1. Enter xtSignalEM or choose Crosstalk > Signal EM Analysis.
The Signal EM Analysis dialog box appears.

16-13
The command options are briefly described in the next steps. For
detailed descriptions of all the xtSignalEM command options,
2. Specify the names of the nets for which you want to run signal
electromigration analysis. You can specify the net names from a
window list, including specifying a pattern to match the names of
multiple nets, or read the list of net names from an ASCII file.

16-14
3. Specify the names of the nets that you want to exclude from
signal electromigration analysis. You can specify the net names
from a window list, including specifying a pattern to match the
names of multiple nets, or read the list of net names from an
ASCII file.
You can select Exclude Nets without Driver to specify that
electromigration analysis not be performed for the named nets
without drivers. The default is off.
4. Select Hierarchical to perform analysis for top-level nets that are
routed to pins of soft macros.
Signal electromigration analysis of a top-level design with soft
macros not only includes analysis of the top-level nets, it also
accounts for the segments of nets that are inside the blocks and
connected to the top-level nets through ports.
Hierarchical signal electromigration analysis allows you to better
analyze top-level nets that are routed to blocks because it
accounts for the segments of the nets that are within the blocks.
You need to create the models for each block that retain the
geometry information for all the boundary nets. Boundary nets
are nets that are routed to the ports of the block and, therefore,
will be part of top-level routing.
When you run signal electromigration analysis in hierarchical
mode, the resulting repair file will contain variable routing rules
for block-level nets (from the HTV model) as well as for top-level
nets. When this repair file is loaded at the top level, the router
modifies only the top-level nets and not the block-level (HTV)
nets. You will need to fix the signal electromigration violations that
occur within the block at the block level.

16-15
5. Select the options, such as AWE order, wire width condition to be

used for current density calculation, operating condition to be
used for the temperature, derate case to be used for analysis,
and the violation rules to be considered.
To calculate current density, Astro first needs to run timing
analysis to determine the transition time for each net. Once the
current density is calculated, it is checked against the constraint
to determine whether it is a violation. The constraint depends on
the width of each metal segment and the temperature specified.
To specify temperature, select Max, Nom, or Min (next to
Temperature). The corresponding temperature value in the
Parasitics page of the AstroTime Timing Setup dialog box is used
to determine the signal electromigration constraint from the ALF
file (or the .plib file). For example, when you select Nom, and the
temperature for nom on the Parasitics page is 25, the constraint
for a temperature setting of 25 is taken from the ALF file.
The temperature setting also determines the resistance scaling
during parasitic extraction. However, the timing analysis is done
according to the operating condition selection you select in the
Parasitics page.
You can enter a number in the Healing Factor box to specify a
factor to be used by electromigration analysis in calculating the
average current. The default is 1.0.
6. Enter the name of the repair file to which the variable routing
rules for interconnect electromigration repair will be written.
7. Choose whether to output the analysis report to a window or file
(if a file, enter a file name). Also choose whether signal
electromigration information is reported for all nets or only for
those nets with violations.

16-16
Select Detail Report to specify that additional information for all

nets or violating nets be reported (layer name, Rel_AbsAvg, and
Rel_RMS).
A repair file, as well as a signal electromigration report is
generated.The report lists the analysis results, and is described in
the next section. For information about the repair file, see Repairing
Electromigration Violations on page 16-23.
Signal Electromigration Analysis Report

The electromigration analysis report that xtSignalEM generates
reports information such as the calculated average, absolute
average, root mean square (rms), and peak currents. Example 16-1
shows a sample report.
Example 16-1
Signal Electromigration Analysis Report
# Signal EM Report
# Design Name: test

# Date: Thu Mar 6 16:38:14 2003
# Vendor: Synopsys
# Program: Astro
# Version: Astro(TM) version 2002 Thu Mar 6 15:23:12 PST 2003
# Hierarchical Separator : /
# Resistance Units : 1 kohm
# Capacitance Units : 1 pf
# Current Units : mA
N counter_module_inst/counter_5/
timer_count[13]ASTipoNet1947
AWE Order: 4
Met/Via Layer bBox
Width Mode Eff_Avg
Eff_Rms
Metal
15
[ 585, 2] 0.12 min 5.0752e-02 2.8693e-01
Metal
15
[ 585, 2] 0.12 max 5.0752e-02 2.8693e-01
Via
16
[ 613,
2]
min
5.1755e-02 2.9532e-01

16-17
Via
16
[ 613,
2]
max
5.1755e-02 2.9532e-01
Metal
Metal
21
21
[ 623,
[ 623,
2] 0.14 min
2] 0.14 max
5.2277e-02 2.9982e-01
5.2277e-02 2.9982e-01
Via
Via
18
18
[ 613,
[ 613,
2]
2]
5.1788e-02 2.9560e-01
5.1788e-02 2.9560e-01
1
1
min
max
The signal electromigration analysis report starts with a header

section that includes the specified hierarchical separator and the
specified resistance, capacitance, and current units. N precedes the
name of the net for which the subsequent information applies.
AWE Order refers to the specified order that is used for AWE
calculation.
Metal/Via and Layer denote the metal or via edge and the
corresponding layer number.
Note:
Because no actual geometries exist in the virtual routing
stage, the Metal/Via and Layer fields are not present in
prerouting analysis.
bBox lists the coordinates of the center of the edge.
Mode is min or max, which designates the corner on which the

calculation is based.
Width lists the width of the net segment.
Eff_Avg, Eff_Rms, and Eff_Peak show the calculated

average, rms, and peak currents, respectively. These values are
in terms of the current units defined in the technology file. In this
sample, the unit is mA, as shown next to Current Units in the
header section.

16-18
Consider the following points
The current of every edge, including wire and via on a net is

evaluated and reported.
You might see different combinations of average, absolute

average, rms, and peak currents in your report, depending on the
violation rule you have chosen.
Average currents can be zero because the xtSignalEM

command uses 1 for the healing factor. When this occurs, it is
because the integral of the current over time is the total charge
and Q = C V. Therefore, even when the waveform of l_p(t) is
different from that of I_n(t), their integrals over time might cancel
each other as long as the total C is the same. This situation can
occur when the pin capacitances are the same for rise and fall.
Note that wire capacitance is independent of rise and fall
transitions.
Signal electromigration analysis prints additional information in the

report it generates when you select Detail Report in the Signal EM
Analysis dialog box. Example 16-2 show a sample detailed report:
Example 16-2
Detailed Electromigration Analysis Report
N nClk
AWE Order: 4
Met/Via Layer
bBox
Width Mode Eff_AbsAvg Eff_Rms
Rel_AbsAvg Rel_RMS
Metal
12
M2 [ 242, 779] 0.14 min 5.1610e-01 6.7542e-01 1.0393e-01 7.7940e-01
Metal
12
M2 [ 242, 779] 0.14 max 5.2402e-01 5.3575e-01 1.0553e-01 6.1822e-01
Via
Via
22
22
V2 [ 240, 772]
V2 [ 240, 772]
1
1
min
max
5.1652e-01 6.7616e-01 3.2282e+00 0.0000e+00

5.2443e-01 5.3619e-01 3.2777e+00 0.0000e+00
The three new columns are as follows:
Layer, which denotes the layer name
Rel_AbsAvg, which is the ratio of Eff_absAvg to the constraint

for average current density
16-19
Rel_RMS, which is the ratio of Eff_rms to the constraint for root

mean square (rms) current density
Definitions of Average, Absolute Average, Root Mean

Square, and Peak Currents
Average, absolute average, rms, and peak currents are defined as
shown in the following equations:
Average
2 T 2
2 T 2
I avg = -------
I n ( t ) dt
I p ( t ) dt -------
T 0
T 0
where gamma is the healing factor.
Absolute average
2 T 2
2 T 2
I absavg = -------
I n ( t ) dt
I p ( t ) dt + -------
T 0
T 0

16-20
rms
I rms =
T2 2
2 T 2 2
I n ( t ) dt
I p ( t ) dt +
-------
T 0
0
Peak
I peak = MAX ( MAX ( I p ) D p, MAX ( ( I n ) D n ) )
where D is the duty cycle, defined as 50 percent peak width

divided by half of the period, as shown in the following equation:
D p = Width ( I p ) 2 ( T )
D n = Width ( I n ) 2 ( T )
The subscripts p and n denote the rise and fall transitions,

respectively.

16-21
For the equations, consider the following points:
is the number of rise or fall transitions that occur in a half-clock

cycle time. For a clock net, is equal to 0.5 because there is one
rise and one fall in every clock cycle; therefore, during half of the
clock cycle time, the number of rise or fall is counted as 0.5.
Because the value of is derived from the switching activity that

you load with the poLoadNetSwitchingInfo command, you
need to know the relationship between the values specified with
defineNetSwitchingActivity and .
For example, assuming that your time units are ns, for a clock of
10 ns period, the switching activity value to be used in the
defineNetSwitchingActivity statement for this clock is
0.2 (2 toggles divided by 10 ns) and a = 0.5 and T= 10 ns.
Similarly, for a clock net with period of 5 ns, a = 0.5 and T= 5 ns
and the switching activity value to be used in the
defineNetSwitchingActivity statement = 0.4.
Consider an example where the value of

defineNetSwitchingActivity is 0.04 for a net belonging to
the 10-ns-period clock domain. With this information, you can
figure out the corresponding value for the value is 0.1
because 0.04 means 4 toggles per 100 ns, which equals 0.2
toggles in 5 ns; therefore, the number of rise or fall transitions in
5 ns is 0.1.

16-22
The following general relation between the value of

defineNetSwitchingActivity and 2a /T exists:
1
2
------- = -- ( defineNetSwitchingActivity )
2
T
where the units are 1 divided by the time units you define.

After running xtSignalEM and violations are found, a repair file with
the default name EMRepair is created. The repair file defines
variable routing rules, such as width and contact constraints, for
those nets that violate the current constraints. The router follows
these rules to route or reroute these nets. For example, there might
be an increased wire width constraint for a specific metal layer to
help fix a signal electromigration problem.
Here is a sample EMRepair file generated by xtSignalEM. This
example defines a variable routing rule set that includes a width
constraint for metal2 and a contact constraint for via12.
(dbDefineVarRouteRule (geGetEditCell) "rule_2818"
(
(width "METAL2" 0.8)
(contact "VIA12" 1 2)
(taperLevel "" 4)
)
)
dbAssignVarRouteRule (geGetEditCell) "rule_2818" ("a")

16-23
To load the variable routing rules, use the load command. Enter
load "EMRepair.net"
After you load the repair file, run axgSearchRepair to reroute

violating nets. Make sure you select rerun DRC in the Search &
Repair dialog box (axgSearchRepair).
You can also load the repair file in the prerouting stage, before you
run axgAutoRoute, to help prevent electromigration violations. You
can perform similar prevention flows at the post-global routing and
post- track assignment stages.

Remember that the current waveforms are obtained through the AWE
method. You can use the demOpen command to run the Debug
Manager, which works to verify the accuracy of the calculated
currents based on AWE by comparing the results from the HSPICE
simulation.
To run the Debug Manager and verify the accuracy of the calculated
currents based on AWE,
1. Enter demOpen or choose Verify > Debugger - Manager.
The Debug Manager dialog box appears.
2. Click the Current Waveform tab to use the Current Waveform
page.

16-24
Do the following:
- Next to Transition Time, click From Timer or From Window.
The xtSignalEM command uses transition time from the
Astro timer, and uses calculated transition times from static
timing analysis that is done in Astro.
- Enter a pattern to match the names of multiple nets (use .* to
specify all nets).
Then select the net of interest from the list of nets that appears.

16-25
3. Under the list of nets, click Compare and wait for the HSPICE
simulation to be completed.
The results are displayed in the Debug Manager window.
For descriptions of all the demOpen command options, see Physical
Interpreting the Results

The Debug Manager window shows AWE/SPICE Rms, Mean, and
Peak values for rise and fall as well as for each corner. It is important
to interpret these values correctly. Assume the voltage is 1 volt in the
following formulas:
Mean from rise
I mean ( debug, p ) =
T2
Mean from fall
I mean ( debug, n ) =
T2

16-26
I p ( t ) dt
I n ( t ) dt
rms from rise
I rms ( debug, p ) =
T2
2
I p ( t ) dt
T2
2
I n ( t ) dt
rms from fall
I rms ( debug, n ) =
Note:
All the values reported in the Debug Manager window are
expressed in terms of signal integrity units. Width uses second;
peak uses ampere; rms uses ampere / (square root of second);
and mean uses ampere * second.
You can derive the values for current densities that are reported by
the xtSignalEM command from those reported in the Debug
Manager window, through the following relationships:
Average current
2
Eff Avg = ( Vdd ) ------- [ I mean ( debug, p ) I mean ( debug, n ) ]
T
rms current density
2 2
2
Eff Rms = ( Vdd ) ------- I rms ( debug, p ) + I rms ( debug, n )
T

16-27
Peak current density
Eff peak = ( Vdd )MAX ( MAX ( I p ) D p, MAX ( ( I n ) D n ) )
For each net, the Debug Manager only reports the currents for the
first edge that connects to the driver and the last edge that connects
to the receiver, whereas the report generated by the xtSignalEM
command lists the currents of all the edges, including metals and
vias.

Use the xtCellEM command to check the cell electromigration and
hot carrier electron effects of each cell instance within a design by
comparing the switching frequency, input slew rate, or output load
capacitance against the allowed maximum values. The maximum
switching frequency can be a function of the input slew rate or output
load capacitance, and the maximum output load capacitance can be
a function of the input slew rate. Violations are listed in the analysis
report.
Remember that, before using xtCellEM, you must load cell
electromigration constraints into your design library (or reference
library) from an ALF file or define them in the Synopsys .plib format.
For information, see Loading Signal Electromigration Constraints
on page 16-4.

16-28
To check the cell electromigration,

1. Enter xtCellEM or choose Crosstalk > Cell EM Analysis.
The Cell EM Analysis dialog box appears.
2. Specify the operating condition to be used for the output load

capacitance and the input transition, and specify the derate case
to be used for cell electromigration analysis.
3. Choose whether to output the analysis report to a window or a file
(if a file, enter a file name). Also choose whether cell
electromigration information is reported for all nets or only for
those nets with violations.
For detailed descriptions of the xtCellEM command options,

16-29
Examples of Signal Electromigration Constraints

Processed in ALF Files
This section contains examples that show portions of an ALF file that
defines the constraints for metal layers and the constraints for via
layers.
The xtSignalEM command only checks for electromigration
violations on those layers that have constraints defined in the ALF
file. For example, if there are no current constraints defined in the
ALF file for layer metal6, the xtSignalEM command will not check
for electromigration violations for edges on metal6.
In the ALF standard, the entities in the TABLE statements are
currents, not current densities. The critical currents are determined
as width table = (0 1), which means widths of 0 um and 1 um. For a
metal segment of width = 0.24 um, Astro interpolates the critical
current that corresponds to 0.24 um from the table.
Similarly, for vias, area table = (0 0.0361), which means areas of 0
and 0.0361 (um)^2. Astro calculates the current through one via (the
total current evenly divided by the number of vias) and calculates the
area from the technology file. The critical current through the via is
interpolated or extrapolated from the table.
Sample Constraints for Metal Layers

This sample assumes the default ALF units, which are mA for
currents and um for widths. If you want to override the default units
for current and width, insert lines such as the following after the
LIBRARY statement:

16-30
CURRENT {UNIT = 1e-6;}

WIDTH { UNIT = 1e-9; }
These lines define the units as uA for currents and nm for widths.
Replace library_name with the name of the library in the ALF file.
LIBRARY library_name {
LAYER metal1 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {
MAX { HEADER {
TEMPERATURE { TABLE { 70 85
} TABLE { 0
0
0
5.8773 3.3319 1.9734
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
32.058 18.174 10.764
}
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0
73.98 41.94 24.84 18
}
}
}
100 110 125 150 175 } }

0
0
0
0
1.43 0.90519 0.45474 0.24596 } }
100 110 125 150 175 } }

0
0
0
0
7.8 4.9374 2.4804 1.3416 } }
100 110 125 150 175 } }

0
0
0
11.394 5.724 3.096 } }
LAYER metal2 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {
Examples of Signal Electromigration Constraints Processed in ALF Files

16-31
MAX { HEADER {
TEMPERATURE {
WIDTH { TABLE
} TABLE { 0
7.9323
TABLE { 70 85 100 110 125 150 175 } }

{ 0 1 } }
0
0
0
0
0
0
4.4969 2.6634 1.93 1.22169 0.61374 0.33196 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
28.77 16.31 9.66 7 4.431 2.226 1.204} }
}
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
98.64 55.92 33.12 24 15.192 7.632 4.128 } }
}
}
}
LAYER metal3 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
7.9323 4.4969 2.6634 1.93 1.22169 0.61374 0.33196 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
28.77 16.31 9.66 7 4.431 2.226 1.204} }
}

16-32
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
98.64 55.92 33.12 24 15.192 7.632 4.128 } }
}
}
}
LAYER metal4 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
7.9323 4.4969 2.6634 1.93 1.22169 0.61374 0.33196 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
28.77 16.31 9.66 7 4.431 2.226 1.204} }
}
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
98.64 55.92 33.12 24 15.192 7.632 4.128 } }
}
}
}
LAYER metal5 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {

16-33
MAX { HEADER {
TEMPERATURE {
WIDTH { TABLE
} TABLE { 0
7.9323
TABLE { 70 85 100 110 125 150 175 } }

{ 0 1 } }
0
0
0
0
0
0
4.4969 2.6634 1.93 1.22169 0.61374 0.33196 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
28.77 16.31 9.66 7 4.431 2.226 1.204} }
}
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
98.64 55.92 33.12 24 15.192 7.632 4.128 } }
}
}
}
LAYER metal6 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
7.9323 4.4969 2.6634 1.93 1.22169 0.61374 0.33196 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
28.77 16.31 9.66 7 4.431 2.226 1.204} }
}

16-34
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
98.64 55.92 33.12 24 15.192 7.632 4.128 } }
}
}
}
LAYER metal7 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
7.9323 4.4969 2.6634 1.93 1.22169 0.61374 0.33196 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
28.77 16.31 9.66 7 4.431 2.226 1.204} }
}
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
98.64 55.92 33.12 24 15.192 7.632 4.128 } }
}
}
}
LAYER metal8 {
PURPOSE = routing ;
LIMIT {
CURRENT avg_limit {

16-35
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
20.3445 11.5335 6.831 4.95 3.13335 1.5741 0.8514 } }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
} TABLE { 0
0
0
0
0
0
0
55.485 31.455 18.63 13.5 8.5455 4.293 2.322 } }
}
MEASUREMENT = peak;
MAX { HEADER {
} TABLE { 0
0
0
0 0
0
0
246.6 139.8 82.8 60 37.98 19.08 10.32 } }
}
}
}
}
Sample Constraints for Via Layers

This portion of the ALF file shows sample constraints for the via1
layer. Via layer constraints are similar to those defined for metal
layersthe LAYER value is the via name instead of the metal-layer
name, the PURPOSE value is cut instead of routing, and the WIDTH
values are replaced with AREA values. The values for AREA are
micron square, (um)^2.
LAYER via1 {
PURPOSE = cut ;
LIMIT {
CURRENT avg_limit {

16-36
MAX { HEADER {
AREA { TABLE { 0 0.0361 } }
} TABLE { 0
0
0
0
0
0
0
0.81789 0.46367 0.27462 0.199 0.125967 0.063282 0.034228
} }
}
CURRENT rms_limit {
MEASUREMENT = rms;
MAX { HEADER {
TEMPERATURE { TABLE { 70 85 100 110
AREA { TABLE { 0 0.0361 } }
} TABLE { 0
0
0
0
0
4.521 2.563 1.518 1.1 0.6963
} }
}
MEASUREMENT = peak;
MAX { HEADER {
TEMPERATURE { TABLE { 70 85 100 110
AREA { TABLE { 0 0.0361 } }
} TABLE { 0
0
0
0
0
10.275 5.825 3.45 2.5 1.5825
} }
}
125 150 175 } }

0
0
0.3498 0.1892
125 150 175 } }

0
0
0.795 0.43
}
}
Examples of Scripts
This section contains a sample script for running signal
electromigration analysis and fixing and a sample script for running
signal analysis and prevention.

Analysis and Fixing
This sample script is for running signal electromigration analysis and
fixing on a routed design.
Examples of Scripts
16-37
#Signal EM analysis and correction on a routed design

geOpenLib
setFormField "Open Library" "Library Name" "library_name"
formOK "Open Library"
geOpenCell
setFormField "Open Cell" "Cell Name" "cell_name"
formOK "Open Cell"
#Specify the power supply voltage
poLoadPowerSupply
setFormField "Load Power Supply" "TDF File Name"
"powersupply_file_name"
formOK "Load Power Supply"
#Load net switching activity for signal nets
poLoadNetSwitchingInfo
setFormField "Load Net Switching Activity" "File Name"
"netswitch_file_nme"
formOK "Load Net Switching Activity"
#Run Signal EM analysis and generate signal EM constraints
xtSignalEM
setFormField "Signal EM Analysis" "Output To" "File"
setFormField "Signal EM Analysis" "File Name"
"EM.report-before"
formOK "Signal EM Analysis"
#Load the EM repair constraint file
load "EM.repair"
#Router remove the violations
axgSearchRepair
setFormField "Search & Repair" "rerun DRC" "1"
formOK "Search & Repair"
#Run signal EM analysis again to see the final results

16-38
xtSignalEM
"EM.report-after"

Analysis and Prevention
This sample script is for running the signal electromigration analysis
and prevention on a placed design.
#Signal EM prevention routing flow starting from a placed
design
geOpenLib
setFormField "Open Library" "Library Name" "library_name"
formOK "Open Library"
geOpenCell
setFormField "Open Cell" "Cell Name" "cell_name"
formOK "Open Cell"
poLoadPowerSupply
setFormField "Load Power Supply" "TDF File Name"
"powersupply_file_name"
formOK "Load Power Supply"
poLoadNetSwitchingInfo
setFormField "Load Net Switching Activity" "File Name"
"netswitch_file_name"
formOK "Load Net Switching Activity"
xtSignalEM
"EM.report-before"
load "EM.repair"
Examples of Scripts
16-39
axgAutoRoute
formOK "Auto Route"
xtSignalEM
setFormField "Signal EM Analysis" "File Name" "EM.report"

16-40
A
Astro Design Flow
The Astro design flow is shown in Figure A-1. This flow drawing is a
compilation of the flow drawings appearing in various chapters
throughout this user guide. When there is a choice of using a
combined command rather than individual commands, it shows the
combined command. Because of the many differences in design
structures and methods, you might need to use a variation of this
flow.
See also the Astro-Rail and PrimeRail flow (Figure 1-2 on
page 1-14), the charge-collecting antenna fixing flow (Figure 14-1 on
page 14-4, and the crosstalk prevention, analysis, and fixing flow
(Figure 15-1 on page 15-4).
A-1
Figure A-1 Astro Design Flow

Astro
place and route
cell
Contains created
cell bound to
expanded netlist
Design data preparation

Load power supply
poLoadPowerSupply
Preserve hierarchy (if desired)

astInitHierPreservation
astMarkHierAsPreserved
Connect power and ground

aprPGConnect
Load timing constraints

ataLoadSDC
Set up timing
atTimingSetup
Set attributes to specify

clock buffers, delay cells
dont use cells, and so forth
Check timing
astTimingDataCheck
Check design
astCheckDesign
To next page
Appendix A: Astro Design Flow

A-2
From previous page

Placement, optimization, and
Set placement common options
astPlaceOptions
Perform magnet placement (optional)

astMagnetPlace
Perform preplacement, in-placement,

and postplacement optimizations
before clock tree synthesis
astAutoPlace
Evaluate placement
axgDisplayPLCongestionMap
axgDisplayCouplingCapMap

astPowerRecovery
Perform clock tree synthesis

astCTS
Perform postplacement optimization

after clock tree synthesis
astAutoPlace
Perform clock tree optimization

astCTO
To next page
A-3
From previous page

Routing
Set routing common options
axgSetRouteOptions
Route groups of nets

(clocks, special nets, and so forth)
axgRouteGroup
Perform global routing,

track assignment,
detail routing, and
search-and-repair
axgAutoRoute
Reduce wire length and via count

axgRoutOpt
Postrouting optimization
astPostRouteOpt

astPowerRecovery
To next page

A-4
From previous page

Design finishing and
interactive changes
Optimize contacts
axDrouteOptimizeContact
or
axgOptimizeContact
Perform design finishing processes,

such as metal density filling and wide metal slotting
axgFillWireTrack
axgSlotWire
Perform interactive changes
Verification and back-annotation

Perform DRC and connectivity verification
geAdvDRC for 90 nm and below design rules or geNewDRC
geNewLVS
Generate output for back-annotation
A-5

A-6
B
Scan Chains
Astro supports both netlist-defined and user-defined scan chain

optimization flows.
Scan Chain Optimization
Setting Scan Input and Output Ports
Creating Scan Chains
Detaching Scan Chains
Creating and Applying Constraints
Optimizing Scan Chains
Tracing Scan Chains
Writing Out New Scan Chain Information
B-1

Astro improves the wire length of a chip by reordering the scan cells.
Optimization is based on the following user-defined (or
netlist-defined) scan chain specifications:
Source, destination, and interim ports
Order constraints, which control routing sequences between

ports (optional)
Global control nets, such as scan clocks and scan-enabled nets

(optional)
When you perform scan chain optimization, you can also specify a
routing preference (horizontal or vertical).
Note:
Scan chain optimization accepts multiple scan-out ports and
honors minimum edge lengths. Specifying the minimum edge
lengths prevents hold-time violations in some cases.
Before you define and optimize scan chains, complete all placement
operations and identify the scan input and output ports.
For information about identifying scan ports, see the Milkyway Data
Preparation User Guide.
Netlist-Defined Scan Chain Optimization Flow

A sample netlist-defined scan chain optimization flow is shown in
Figure B-1. Because of differences in design structures and
methods, you might need to use a variation of this flow.
Appendix B: Scan Chains

B-2
Figure B-1 Netlist-Defined Scan Chain Optimization Flow

Set scan input and output ports
dbSetCellPortTypes
Create scan chains by tracing the netlist

axgScanTrace
Detach scan chains

axgScanChainOptimization
Perform placement
Create and apply constraints (optional)
Optimize scan chains

Trace scan chains

axgScanTrace
Write new scan chain information to a file

dbDumpScanChain
Perform clock tree synthesis and optimization (optional)
Update netlist
To routing

B-3
Methodology
As shown in Figure B-1, the netlist-defined scan chain optimization
1. Set scan input and output ports. Use dbSetCellPortTypes.
See Setting Scan Input and Output Ports on page B-7.
2. Create scan chains by tracing the netlist. Use axgScanTrace.
See Creating Scan Chains by Tracing the Netlist on page B-7.
3. Detach scan chains. Use axgScanChainOptimization.
See Detaching Scan Chains on page B-9.
4. Perform placement.
See Chapter 8, Placement and Placement Optimizations.
5. (Optional) Create and apply constraints.
See Creating and Applying Constraints on page B-10.
6. Optimize scan chains. Use axgScanchainOptimization.
See Optimizing Scan Chains on page B-19.
7. Trace scan chains. Use axgScanTrace.
See Tracing Scan Chains on page B-21.
8. Write new scan chain information to a file. Use
dbDumpScanChain.
See Writing Out New Scan Chain Information on page B-21.

B-4
9. Perform clock tree synthesis and optimization.

See Chapter 9, Clock Tree Synthesis and Clock Tree
Optimizations.
10. Update the netlist.
User-Defined Scan Chain Optimization Flow

A sample user-defined scan chain optimization flow is shown in
Figure B-2. Because of differences in design structures and
methods, you might need to use a variation of this flow.
Figure B-2 User-Defined Scan Chain Optimization Flow
From placement
Create scan chains manually

dbMakeScanChainByCellInst
dbMakeScanChainByMaster
Write new scan chain information to a file (optional)

dbDumpScanChain
Optimize scan chains

Trace scan chains

axgScanTrace
Perform clock tree synthesis and optimization (optional)
To routing

B-5
Methodology
As shown in Figure B-2, the user-defined scan chain optimization
1. Create scan chains manually. Use
dbMakeScanChainByCellInst and
dbMakeScanChainByMaster.
See Creating Scan Chains Manually on page B-9.
2. Write new scan chain information to a file. Use
dbDumpScanChain.
See Writing Out the Scan Chains on page B-11.
3. Optimize scan chains. Use axgScanchainOptimization.
See Optimizing Scan Chains on page B-19.
4. Trace scan chains. Use axgScanTrace.
See Tracing Scan Chains on page B-21.
5. Perform clock tree synthesis and optimization.
See Chapter 9, Clock Tree Synthesis and Clock Tree
Optimizations.

B-6

Before you define and optimize scan chains, define the scan input
and output ports by using the dbSetCellPortTypes command.
For descriptions of the dbSetCellPortType command
arguments, see Physical Implementation Online Help. See also the
Milkyway Environment Data Preparation User Guide.
Creating Scan Chains

You can create scan chains by tracing the netlist (netlist-defined flow)
or by creating them manually (user-defined flow).
Creating Scan Chains by Tracing the Netlist

Use the axgScanTrace command to extract scan chain information
(trace scan-chain connectivity) that is defined in the netlist.
To extract scan chain definitions for the open cell,
1. Enter axgScanTrace or choose PrePlace > Scan Chain
Trace Scan Chain.
The Scan Trace dialog box appears.

B-7
2. Next to Start Port Name, enter the name of the port that is the
starting point of the scan chain. Also, select the type of cell for
which the port exists (top cell or cell instance). If you select cell
instance, enter the name of the cell instance for which the
specified port exists (next to Instance Name).
For descriptions of the axgScanTrace command options, see
4. Click Apply.
5. Repeat steps 1 and 2 for each scan chain defined in the netlist.
6. Click OK the last time you execute the command.
B-8
Creating Scan Chains Manually

If your netlist does not contain scan chains, you can create them by
opening your layout and using either of the following commands to
define them:
The dbMakeScanChainByCellInst command, which creates

a scan chain containing specified cell instances
The dbMakeScanChainByMaster command, which creates a

scan chain containing all cell instances, except those specifically
excluded, of a specified master cell
Note:
You can replace scan cell instances with instances of a
different master cell by using the dbReplaceScanCell
command.

Before you place standard cells, detach the scan chains, so that they
do not affect the placement. You can rebuild and optimize the scan
chains later.
Note:
You can display the scan chains by using the
axgDisplayScanChain command.
To detach a scan chain,
1. Enter axgScanChainOptim or choose
PrePlace > Scan Chain Optimize/Delete Scan Chain.
The Scan Chain Optimization dialog box appears.
B-9
2. Next to Mode, select Delete only.

For descriptions of the axgScanChainOptim command
After placement, you can reconstruct the scan chain. For additional
scan chain information, see Scan Chain Optimization on page B-2.

Regardless of how you create scan chains, you can write scan chain
information to a file in a format that is required for specifying order
constraints. By editing this file, you can create a scan chain
constraints file that controls scan cell ordering during optimization.

B-10
This section uses the following terminology:

Term
Meaning
Default group
priority
Priority assigned to scan chain groups created by the

Synopsys application.
Edge constraint
Connectivity constraint between two ports.
Fixed edge
Connectivity constraint protected from change during

optimization.
Free edge
Connectivity constraint subject to change during

optimization.
Group priority
Number for specifying the ordering of cell instances in a

scan chain group in relation to other cell instances in the
scan chain. A lower priority results in the instances being
nearer to the beginning of the scan chain.
Scan chain group
Group of cell instances that must be connected together

without interruption.
Writing Out the Scan Chains

With your layout open, use the dbDumpScanChain command to
write scan chain information to a file.
To write scan chain information to a file,
1. Enter dbDumpScanChain or enter PostPlace > Scan Chain
Dump Scan Chain.
The Dump Scan Chain dialog box appears.

B-11
2. Enter the name of the file to which you want to save the scan
chain information.
You can select Print Clock Nets to print the clock nets in the scan
chain file to verify the results of scan chain optimization with clock
net reordering.
Here is a sample output file:
dbCreateScanChain (geGetEditCell) "SCAN1"
dbAddFreeEdgeToScanChain (geGetEditCell) "SCAN1"
((("S" "so") ("F1" "si")) (("F2" "so") ("F3" "si"))
(("F3" "so") ("R" "si2")))
((("S" "so") ("F4" "si")) (("F4" "so") ("F5" "si"))
(("F5" "so") ("F6" "si")) (("F6" "so") ("R" "si1")))
Next, you can edit this file to include fixed-edge constraints and
group-ordering constraints.

B-12
Creating the Constraints File

Follow these guidelines when defining a scan chain:
The primary input scan cell instance should be in one edge

constraint and should not be in a scan chain group.
The primary output scan cell instance should be in one edge

constraint and should not be in a scan chain group.
Each scan cell instance that is not a primary input or output

should be in two edge constraints (scan chain group is optional).
When you finish, the file should contain the following:
At the beginning of the file, the dbDeleteScanChain command

to remove each of the scan chain definitions currently in the
database
For each scan chain defined, the dbCreateScanChain

command to create the scan chain and one or more of the
following functions to add cell instances and specify constraints:
- The dbAddInstGroupToScanChain command to add a
scan chain group to a scan chain
- The dbAddFreeEdgeToScanChain command to add a set of
free edges to a scan chain
- The dbAddFixedEdgeToScanChain command to add a set
of fixed edges to a scan chain
- The dbSetScanChainDefaultPriority command to set
the default priority for scan chain groups

B-13
Now you can edit the file containing the scan chain information to
create your scan chain constraints file. Use the information that
follows to help you specify your constraints.
Task
Command
Delete the scan chain.
dbDeleteScanChain
Create an empty scan chain.
dbCreateScanChain
Add a scan chain group to a scan chain

and set a priority for the group.
dbAddInstGroupToScanChain
Change the default group priority.
dbSetScanChainDefaultPriority
Add a set of free edges to a scan chain.
dbAddFreeEdgeToScanChain
Add a set of fixed edges to a scan

chain.
dbAddFixedEdgeToScanChain
Delete the Scan Chain

You can delete a scan chain in the open cell from the database. Use
the dbDeleteScanChain command at the beginning of the
constraints file to remove a scan chain definition already in the
database.
Note:
You can delete all scan chains in the open cell, using the
axgScanChainOptim command.
Create an Empty Scan Chain

After you create the scan chain, you can assign cell instances to it by
adding scan chain groups, free edges, or fixed edges.

B-14
Add a Scan Chain Group

A scan chain group is a group of scan cell instances that must be
connected without interruption. For example, if instances IA, IB, IC,
and ID are in a scan chain group, the following connection sequence
is prohibited.
IA
IB
IC
ID
IE
Set Default Group Priority

A priority is a number that specifies the ordering of cell instances in
a scan chain group in relation to other cell instances in the scan
chain.
If an edge constraint references a cell instance that is not explicitly
placed in a scan chain group, the place and route tool creates a scan
chain group containing only that cell instance and assigns it a priority
equal to the default priority (except for the primary input scan cell,
which is always at the beginning of the scan chain, and the primary
output scan cell, which is always at the end of the scan chain).
Unless otherwise specified, the default group priority is 0. For an
edge constraint to use the priority you set, place the
dbSetScanChainDefaultPriority command in the constraints
file prior to running the dbAddFreeEdgeToScanChain or
dbAddFixedEdgeToScanChain commands that create the edge
constraint.

B-15
Add Free Edges

A free edge is a connectivity constraint that can change during
optimization.
Note:
If you want to control the sequence of the free edge in the scan
chain, set the default priority using the
dbSetScanChainDefaultPriority command prior to using
this function. If you want to assign different priorities to cell
instances in different sets of edge constraints, insert the
dbSetScanChainDefaultPriority command prior to each
set of edge constraint functions.
Add Fixed Edges

A fixed edge is a connectivity constraint that cannot change during
optimization.
Note:
If you want to control the sequence of the fixed edges in the scan
chain, set the default priority with the
dbSetScanChainDefaultPriority command before using
this function. If you want to assign different priorities to cell
instances in different sets of edge constraints, insert the
dbSetScanChainDefaultPriority command before adding
each set of fixed edges.
Sample Constraints File

When you load a file containing the following functions to define two
scan chains, SCAN1 and SCAN2 (see the following sample), Astro
can optimize the scan chain, based on your specifications.

B-16

((("S" "so") ("F1" "si")) (("F2" "so") ("F3" "si"))
(("F3" "so") ("R" "si2")))
dbAddFixedEdgeToScanChain (geGetEditCell) "SCAN1"
((("F1" "so") ("F2" "si")))
((("S" "so") ("F4" "si")) (("F4" "so") ("F5" "si"))
(("F5" "so") ("F6" "si")) (("F6" "so") ("R" "si1")))
dbAddInstGroupToScanChain (geGetEditCell) 10 "SCAN2"
"registers1" ("F5" "F6")
These functions define the following scan chains:
SCAN1, which contains three free edges and one fixed edge.
SCAN2, which contains four free edges and two scan chain
groups. The scan chain groups include the following:
- registers1, which contains cell instances F5 and F6 and has a
priority of 10. It is defined by the
dbAddInstGroupToScanChain command.
- Cell instance F4, with a default priority of 0. The group is
defined by Astro.
The following diagram illustrates a possible configuration of the scan

chains.

B-17
Fixed edge
S so
si S so
si F2 so
si F3 so
si F4 so
si F5 so
si F6 so
si2
R
si1
a C1
b
C2
a
Note that C1 and C2 are not in a scan chain. They are included in
the diagram to illustrate that when Astro reorders the chain, it
disconnects from the input ports. Thus, any connections external to
the scan chain move with the cells that contain the output ports. For
example, if Astro swaps F5 and F6, C2 moves with F5, as shown in
the next diagram.
Fixed edge
si S so
S so
si F4 so
si F2 so
si F3 so
si F6 so
si F5 so
a C1

B-18
si2
R
si1
b C2
a
Applying the Constraints

You apply the constraints by loading the constraints file. With your
layout open, type the following from the input area of the application
window:
load fileName
where fileName is the name of the constraints file.
Creating Global Control Nets

You create a global net for scan control, such as scan clock or scan
enable for the cell instances, of a scan chain by using the
dbCreateGlobalNetByScanChain command.

After creating scan chains and specifying constraints, optimize the
ordering of scan cell instances.
During scan chain optimization, Astro changes the connections
between the scan cells and generates an ECO. Keep this in mind
when running an external LVS check.
To perform scan chain optimization,
1. Enter axgScanChainOptim or choose PrePlace > Scan Chain
Optimize/Delete Scan Chain.
The Scan Chain Optimization dialog box appears.

B-19
2. Enter a Vertical Weight value to indicate the preference of vertical

versus horizontal routing in scan chains.
- The default weight, 1, means that you weigh vertical and
horizontal routing equally.
- A vertical weight of 0 weighs horizontal routing infinitely.
- A vertical weight of 10 weighs vertical routing infinitely.
3. Specify a minimum edge length allowable for a scan chain edge.
This option prevents hold-time violations in some cases.
4. Select from the Option and Mode options.
For descriptions of the axgScanChainOptim command

B-20
After you run scan chain optimization, trace the scan chain to see the
scan chain connections; then write the scan chain information to a
file. You can also use the axgDisplayScanChain command to
highlight a scan chain within the design.
Tracing Scan Chains

To see the scan chain connections after you run scan chain
optimization, trace the scan chain (see Creating Scan Chains on
page B-7).
Writing Out New Scan Chain Information

After you run scan chain optimization and trace the scan chain, write
the scan chain information to a file (see Writing Out the Scan
Chains on page B-11). The scan chain names in the output file are
the application-assigned names, not the names you assigned when
you created the scan chains.
You can also use the axgDisplayScanChain command to
highlight a scan chain within the design.
With your layout open, you can write scan chain information to a file
using the dbDumpScanChain command.
Tracing Scan Chains

B-21

B-22
C
Routing Design Rules
Astro supports routing design rules for advanced technologies

extending to 90 nm and 65 nm. Most of these rules are defined in the
technology file. Some of the rules are defined with droute
parameters or have additional controls that are defined with droute
parameters that you enter in the command window during an Astro
session.
All the design rules are supported by both the detail route operation
and the search-and-repair operation. Where noted, rules are
supported by other operations, such as power and ground routing.
This appendix contains the following sections:
Minimum Length Rule
Minimum Edge Rules
Via Corner Spacing Rule
C-1
U-Shape Spacing Rule
Minimum Enclosed Area Rule
Fat Poly Contact Rule
Fat Contact Rule
Merging Pins With Abutting Obstruction Rule
Special End-of-Line Spacing Rules
Enclosed Via Spacing Rule
Metal Density Rules
Via Array (Via Farm) Rule
Same Net Minimum Spacing Rule
Dog Bone Rule
Protrusion Length Rule
Via Array Maximum Stack Level Rule
Neighboring Layer Fat Extension Range Spacing Rule
Parallel Length Rule
Jog Wire Rules
Fat Wire Via Keepout Region Rule
Appendix C: Routing Design Rules

C-2
Minimum Length Rule

Use the minLength attribute to specify the minimum wire length
allowed. Define this attribute in the metal Layer section of the
technology file. For example,
Layer
"M1" {
minLength = 0.35
}
By default, the minimum length rule is checked by the total wire

length instead of by wire segments. You can specify that the rule is
to be checked by wire segments that include via cuts by using the
minLengthCheckCutMode parameter. For example, to set this via
cut checking mode, enter
axSetIntParam "droute" "minLengthCheckCutMode" 1
A value of 1 specifies that horizontal and vertical wire segments are

checked separately; if a via cut is enclosed by both horizontal and
vertical segments, at least one segment must meet the minLength
rule. A value of 0 (the default) specifies that the minLength rule is
checked by the total wire length.
You can fix a minimum length rule violation by adding metal stubs or
by rerouting the wire to meet the minLength value.
Minimum Edge Rules

The minimum edge rules are described in the following sections:
Minimum Edge Length Rule
Minimum Length Rule

C-3
Total Minimum Edge Length Rule
Special Notch Rule
Combined Minimum Edge and Special Notch Rule
You control the scope of the check for most of these rules by
specifying a mode value (0 or 1) with the minEdgeMode attribute in
the Technology section of the technology file. For example,
Technology{
minEdgeMode = 0
}
The mode values are described in the table and figure that follow.
Mode value
Description
Must have concave corner to trigger violation (See the figure below
and Table C-1).
Ignore concave corner and check whether maxNumMinEdge or

maxTotalMinEdgeLength is violated (See the figure below and
Table C-2).
A
B
B
C
Metal 1
Metal 1
Concave Corner

C-4
Convex Corner
Consider the following sample technology file syntax:

Layer
"M1" {
minEdgeLength = 0.07
maxTotalMinEdgeLength = 0.11
}
or
Layer
"M1" {
maxNumMinEdge = 2
}
Table C-1 shows how to interpret this syntax when minEdgeMode

has a value of 0.
Table C-1 Interpreting the Rule Check When minEdgeMode Value is 0
minEdgeMode Edge length values
value
Corner
Violation?
A, B, C < 0.07 and A+B+C > 0.11
Concave
Yes
B, C < 0.07 and B+C > 0.11
Convex
No
Table C-2 shows how to interpret this syntax when minEdgeMode

has a value of 1.
Table C-2 Interpreting the Rule Check When minEdgeMode Value is 1
minEdgeMode Edge length values
value
Corner
Violation?
A, B, C < 0.07 and A+B+C > 0.11
Concave
Yes
B, C < 0.07 and B+C > 0.11
Convex
Yes
Minimum Edge Rules

C-5
Note:
For this syntax sample, when minEdgeMode has a value of 1, a
violation also occurs when maxNumMinEdge < 2.
Minimum Edge Length Rule

Use the minEdgeLength and maxNumMinEdge attributes to
specify the minimum edge length rule. Define these attributes in the
metal Layer section of the technology file.
To define the check for this rule, specify a value of 0 or 1 for the
minEdgeMode attribute in the Technology section of the technology
file.
For example,
Technology {
minEdgeMode = 0
}
Layer
"M1" {
minEdgeLength = 0.4
maxNumMinEdge = 2
...
Total Minimum Edge Length Rule

Use the minEdgeLength and maxTotalMinEdgeLength
attributes to specify the maximum total edge length allowed. Define
these attributes in the metal Layer section of the technology file.
To define the check for this rule, specify a value of 0 or 1 for the
minEdgeMode attribute in the Technology section of the technology
file.

C-6
For example,
Technology{
minEdgeMode = 1
}
Layer
"M1" {
maxTotalMinEdgeLength = 0.11
}
Special Notch Rule

Use the minEdgeLength2 attribute to specify the notch width. Use
the minEdgeLength3 attribute to specify the notch height. Define
these attributes in the metal Layer section of the technology file. For
example,
Layer
"M1" {
minEdgeLength2 = 0.4
...
Table C-3 and the following figure show how to interpret this syntax.
Table C-3 Specifying Special Notch Rule Attributes
Attribute
Value
Description
minEdgeLength2
0.4
Specifies the minimum width for metal notch (W).
minEdgeLength3
0.26
Specifies that at least one edge of either length (L1 or L2)

next to the concave corner < 0.26.
Minimum Edge Rules

C-7
270
L1
W
L2
270
You can fix special notch rule violations by rerouting wires, rotating
vias, or adding stubs.
Combined Minimum Edge and Special Notch Rule

You can check the minimum edge rule and special notch rule at the
same time by defining all four parameters (minEdgeLength,
maxNumMinEdge, minEdgeLength2, and minEdgeLength3) in
the metal Layer section.
Specify a value of 1 for the minEdgeMode attribute in the
Technology section of the technology file to define the check for this
rule.
For example,
Technology{
minEdgeMode = 1
}
Layer "M1" {
minEdgeLength = 0.4
maxNumMinEdge = 2
...
}

C-8

Use the cornerMinSpacing attribute to specify the minimum
corner-to-corner spacing allowed between two vias. For corner
spacing between different via layers, define this attribute in the
DesignRule section of the technology file. For corner spacing on the
same via layer, define this attribute in the via Layer section.
For example,
Layer
"VIA1" {
cornerMinSpacing = 0.12
}
Because the cornerMinSpacing value is smaller than the

minSpacing value, extra routing resources are saved when you
define the via corner spacing rule.
You can control whether the minimum corner-to-corner spacing
allowed between two vias is measured with diagonal distance (the
default) or with Manhattan distance by using the
cornerSpacingMode parameter. The syntax is
axSetIntParam "droute" "cornerSpacingMode" value
Value
Description
Measure diagonal distance (the default).
Measure Manhattan distance.

C-9
U-Shape Spacing Rule

To prevent or eliminate U-shaped notches, use the
uShapeDepthThreshold, uShapeMinLength, and
uShapeMinSpacing attributes to specify a larger minimum spacing
value than that specified with the minSpacing attribute.
This rule defines the minimum spacing (S), as specified with
uShapeMinSpacing, between two edges when height (H) >=
uShapeDepthThreshold and length (L) < uShapeMinLength.
Otherwise, the default minimum spacing specified with minSpacing
applies. Usually, uShapeMinSpacing >= minSpacing.
Define these attributes in the metal Layer section of the technology

file. For example,
Layer "M1" {
uShapeMinSpacing
uShapeDepthThreshold
uShapeMinLength
}

C-10
= 0.13
= 0.05
= 0.16

Use the minEnclosedArea attribute to specify the minimum
enclosed area allowed for the given routing layer. Define this attribute
in the metal Layer section of the technology file. For example,
Layer
"M1"
{
minEnclosedArea = 0.2
Astro honors the minimum enclosed area rule by avoiding the

creation of fat wires. Use the fatTblThreshold attribute to specify
the thresholds that the router uses to determine whether a metal wire
is fat. Use the fatTblMinEnclosedArea attribute to specify the
minimum enclosed area for thin metalthe router uses the first value
in the list. These attributes are defined in the Layer section of the
technology file. For example,
Layer
"M1" {
fatTblDimension = 3
fatTblThreshold = (0, 0.155, 1.605)
fatTblMinEnclosedArea = (0.3, 1.0, 1.0)
}
In this example, Astro avoids creating any metal wires with widths
greater than or equal to 0.155.
You must also set the fatTblMinEnclosedAreaMode attribute in
the Technology section of the technology file. This attribute
determines the mode in which the router checks for and avoids a
violation.
When fatTblMinEnclosedAreaMode = 0 (the default), the

fat wire minimum enclosed area mode is triggered when any of
the surrounding metal satisfies the width requirement.

C-11
When fatTblMinEnclosedAreaMode = 1, the fat wire

minimum enclosed area mode is triggered only when all of the
surrounding metal satisfies the width requirement.
Minimum Enclosed Width Rule

To specify that the tool check the width of the enclosed area, use the
minEnclosedWidth attribute to specify the minimum metal width
for the given routing layer. Define this attribute in the metal Layer
section of the technology file.
Note:
When you specify the minEnclosedWidth attribute, you must
also specify the minEclosedArea attribute.
For example,
Layer
"M1" {
minEnclosedArea = 0.2
minEnclosedWidth = 0.7
}
Fat Poly Contact Rule

The fat poly contact rule specifies whether Astro allows wires and
vias that are connecting to pins to create fat shapes that would
otherwise trigger fat via rule violations. The fat via rules are defined
in the via Layer section that connects the pin and metal layers.
To control the scope of the check for the fat poly contact rule, set the
dontMakePinFat parameter. The syntax is
axSetIntParam "droute" "dontMakePinFat" value

C-12
Value
Description
Perform normal checking only.
Check all pin connections to avoid creating new fat shapes that could
cause either fatVia or minEnclosedArea rule violations.
Fat Contact Rule

This section describes the one-dimensional table rule and the
two-dimensional table rule, as used to specify the fat contact rule.
One-Dimensional Table Rule

The one-dimensional fat contact table rule specifies that the size of
a contact is determined by the maximum width of the upper and
lower metals.
Use the following attributes to specify the one-dimensional fat
contact table rule:
fatTblThreshold
Defines the lower layer width threshold.
fatTblFatContactNumber
Defines the contact code numbers.
fatTblFatContactMinCuts
Defines the minimal numbers of cuts.
Define these attributes in the via Layer section of the technology file.
Fat Contact Rule

C-13
For example,
layer
"VIA1" {
fatTblDimension = 3
fatTblThreshold = (0, 0.155, 1.605)
fatTblFatContactNumber = (1, 21, 31)
fatTblFatContactMinCuts = (1, 2, 4)
}
In this example, if either of the metal widths connected by the VIA1

layer is greater than or equal to 0.155, then a via whose contactCode
value is defined as 21 will be used and at least two cuts of this via
will be necessary.
Two-Dimensional Table Rule

The two-dimensional fat contact table rule specifies that the size of
the contact (contact code and number of cuts) is determined by the
widths of both the upper and lower metal layers.
Use the following attributes to specify the two-dimensional fat
contact table rule:
fatTblThreshold
Defines the lower layer width threshold.
fatTblThreshold2
Defines the upper layer width threshold.
fat2DTblFatContactNumber
Defines the contact code numbers.
fat2DTblFatContactMinCuts
Defines the minimal numbers of cuts.

C-14
Note:
In the two-dimensional fat contact tables the horizontal index is
for the lower metal layer (fatTblThreshold) and the vertical
index is for the upper metal layer (fatTblThreshold2).
Define these attributes in the via Layer section of the technology file.
For example,
Layer "VIA23" {
fatTblDimension = 4
fatTblThreshold = (0,0.421,0.701,0.981)
/* Threshold for lower layer metal width */
fatTblThreshold2 = (0,0.221,0.501,0.781)
/* Threshold for upper layer metal width */
fat2DTblFatContactNumber = (1,18,17,20,
20,17,18,20,
21,18,18,19,
20,20,20,20)
fat2DTblFatContactMinCuts = (1,2,2,2,
2,3,3,4,
4,4,4,6,
4,4,4,4)
}
In this example, if the lower metal width value is greater than or equal
to .421 and less than .701, then the tool will consider that value as
element 2 of fatTblThreshold. If the upper metal width value is
greater than or equal to .501 and less than .781, then the tool will
consider that value as element 3 of fatTblThreshold2.
Consequently, the tool will pick up the (2,3) element value from
fat2DTblFatContactNumber, which is 18, and the (2,3) element
from fat2DTblFatContactMinCuts, which is 3. So, Astro will
use the via whose contactCode value is 18 and use 3 cuts of the
via to connect the lower and upper metal layers.
Fat Contact Rule

C-15
Both the power and ground routing and the detail routing operations
honor the two-dimensional table rule. A rule violation is flagged as a
DRC error.
Merging Pins With Abutting Obstruction Rule

When you set the extendMacroPinToBlockage parameter to 1
and the checkMergedFatWire parameter to 2, Astro does the
following: merges the abutting pin and blockage and uses the
resulting pin width to determine the fat metal spacing as well as the
fat metal extension range. In this case, Astro does not flag a DRC
violation when the pin and blockage of a hard macro are abutting.
To specify this behavior, enter the following syntax:
axSetIntParam "droute" "extendMacroPinToBlockage" 1
axSetIntParam "droute" "checkMergedFatWire" 2
If these parameters are not set, Astro uses the original pin width to
determine the fat metal spacing around the pin without considering
the adjacent blockage.

The special end-of-line spacing rules are described in the following
sections:
End-of-Line Spacing Rule
Dense End-of-Line Spacing Rule
L-Shaped End-of-Line Spacing Rule

C-16
End-of-Line Spacing Rule

Use the following attributes to specify the special end-of-line spacing
rule:
stubSpacing
Specifies the minimum end-of-line spacing allowed.
stubThreshold
Specifies the threshold that triggers the end-of-line spacing rule.
file.
Also, depending on the specific process rule, you must specify a
value of 1, 2, or 3 for the stubMode attribute in the Technology
section of the technology file.
For example,
Technology {
stubMode = 1
}
Layer
"M1" {
stubSpacing = 0.14
stubThreshold = 0.2
}
Dense End-of-Line Spacing Rule

Use the endOfLineCornerKeepoutWidth attribute, as well as
the stubSpacing and stubThreshold attributes to specify this
rule. Define these attributes in the metal Layer section of the
technology file.

C-17
The endOfLineCornerKeepoutWidth attribute specifies the

distance from the corner of the end-of-line metal segment to the
neighboring metal segment, defining a keepout region.
Also, you must specify a value of 4 for the stubMode attribute in the
Technology section of the technology file.
For example,
Technology {
stubMode = 4
}
Layer "M1" {
stubSpacing = 0.12
stubThreshold = 0.11
endOfLineCornerKeepoutWidth = 0.035
}
The following figure shows how to interpret this syntax, where

stubSpacing is S1 and S2, stubThreshold is Q,
endOfLineCornerKeepoutWidth is K, and the minimum edge
width of the end-of-line metal is W.
0.035 um
K
0.035 um
S1
<Q
W
S2

C-18
The end-of-line condition is identified as two adjacent convex

corners with edge length < Q.
The keepout region on the side of the end-of-line metal segment

is defined as being within a distance Q from the end-of-line edge.
That is, length is defined by the stubThreshold attribute.
L-Shaped End-of-Line Spacing Rule

L-shaped end-of-line spacing is applied when the end-of-line
segment is part of an L-shape geometry, and its length meets the
given length threshold. The L-shape definition includes any shapes
that have a partial L-shape, such as a T-shape.
Use the stubLengthThreshold attribute, as well as the
stubSpacing and stubThreshold attributes to specify this rule.
file.
Also, you must specify a value of 1 for the stubMode attribute in the
Technology section of the technology file.
The stubSpacing defines the end-of-line edge or corner of the
metal whose edge width is less than or equal to the given
stubThreshold. An L-shape with adjacent segment on the same
layer is required, and at least one of the side edge lengths must be
less than or equal to the given stubLengthThreshold. Otherwise,
the default minimum spacing specified with minSpacing applies.
The L-shape rule is applied to the end-of-line segment edge as well
as to the diagonal corner spacing, provided the L-shape geometry
and its length meet the given length threshold.

C-19
For example,
Technology {
stubMode = 1
}
Layer "M7" {
stubSpacing
stubThreshold
stubLengthThreshold
}
= 0.24
= 0.24
= 0.28
Enclosed Via Spacing Rule

A via surrounded by a certain number of vias within a certain range
is called an enclosed via. Astro honors the spacing between an
enclosed via and surrounding vias.
Use the following attributes to specify the enclosed via spacing rule:
enclosedCutNumNeighbor
Specifies the minimum number of neighboring vias allowed for
defining an enclosed via.
enclosedCutNeighborRange
Specifies the range of neighboring vias for defining an enclosed
via.
enclosedCutToNeighborMinSpacing
Specifies the minimum spacing allowed between an enclosed via
and surrounding vias.
These attributes are defined in the via Layer section of the
technology file.

C-20
For example,
Layer
"V3" {
enclosedCutNumNeighbor
=
enclosedCutNeighborRange
=
enclosedCutToNeighborMinSpacing =
}
4
0.4
0.25
Metal Density Rules

This section describes the metal density rule and the metal density
gradient rule.
Metal Density Rule

Use the following attributes to specify the metal density rule:
layer
Defines the metal layer for which the rule is specified.
windowSize
Defines the size of the window (by default, the window step-size
is half of the defined windowSize).
minDensity
Defines the minimum percentage of metal allowed in the window.
maxDensity
Defines the maximum percentage of metal allowed in the
window.
These attributes are defined in the DensityRule section of the
technology file. Each metal layer requires a DensityRule definition.
Metal Density Rules

C-21
For example,
DensityRule {
layer = "M1"
windowSize = 200
minDensity = 20
maxDensity = 80
}
The metal fill command, axgFillWireTrack, honors the metal

density rule. That is, the total percentage of the named metal layer in
the window size will be within the specified minimum and maximum
density limits after running axgFillWireTrack.
Metal Density Gradient Rule

Use the densityGradient attribute to specify that the fill density
between adjacent windows should not be more than the density
gradient specified. Define this attribute in the DensityRule section of
the technology file.
The density gradient information is read in during the
insert_metal_filler operation. The fill density of each window
is compared with the corresponding density of its neighbors. If the
percentage difference between them exceeds the density gradient of
that layer, the fill is trimmed to satisfy the density gradient rule.

C-22

Use the maxNumRows attribute to specify the via array size and the
viaFarmSpacing attribute to specify the spacing between two via
arrays. Define these attributes in the ContactCode section of the
technology file. Each via array requires a ContactCode definition. For
example,
ContactCode "VIA12_fat" {
maxNumRows = 3
viaFarmSpacing = 1.2
}
The power and ground routing operation honors the via array rule.
Same Net Minimum Spacing Rule

Use the sameNetMinSpacing attribute to override the
minSpacing default value and set a new value for the minimum
spacing between two vias belonging to the same net.
Same-net via spacing
Diff-net via spacing
Define this attribute in the via Layer section of the technology file.

C-23
For example,
Layer
"VIA5"{
sameNetMinSpacing = 0.28
minSpacing = 0.35
}
Note:
If the sameNetMinSpacing value for the via layer is greater
than the minSpacing value, the router will use the minSpacing
value.
Dog Bone Rule

The dog bone rule applies during wire jogging and pin access when
notches can appear next to narrow wires. A violation occurs when
the following conditions exist:
The metal width is less than the value specified with the
sameNetWidthThreshold attribute (W/X).
The notch spacing is less than the value specified with the
sameNetMinSpacing attribute (L/Y).
W
L
X =<5
Y =>10
Metal

C-24
Use the following attributes to specify the dog bone rule:

sameNetWidthThreshold
Specifies a number that represents the threshold value for the
thin wire width.
sameNetMinSpacing
Specifies a number that represents the spacing value for the thin
wire.
file. For example,
Layer
"M5" {
sameNetWidthThreshold = 0.5
sameNetMinSpacing = 1.0
}

The protrusion length rule applies when a fat wire has both
A width larger than a threshold value (T) specified with the

protrusionFatThresholdTbl attribute
A connected thin wire whose length is less than a value (L)

specified with the protrusionFatThresholdTbl attribute
In such cases, the thin wire width must be wider than the width value
(W) specified with the protrusionFatThresholdTbl attribute.

C-25
Use the following attributes to specify the protrusion length rule:

protrusionFatThresholdTbl
Specifies a floating-point number that represents the threshold
value for the fat wire.
protrusionLengthLimitTbl
Specifies a floating-point number that represents the length value
for the connected thin wire.
protrusionMinWIdthTbl
Specifies a floating-point number that represents the minimum
width value for the connected thin wire.
file. For example,
Layer
"M2" {
protrusionTblDim = 2
protrusionFatThresholdTbl = (1.20,2.40)
protrusionLengthLimitTbl = (0.60,0.90)
protrusionMinWidthTbl = (0.30, 0.45)
}

C-26

Use the maxStackLevel attribute to control the number of valid
upper and lower stacked via layers. When the router checks the via
array maximum stack level rule for a via layer, it counts either the
upper stacked cut layers or the lower stacked cut layers, including the
specified layer. If the stacked cut layer number is larger than the
specified maxStackLevel number, it is a DRC violation. Define this
attribute in the via Layer section of the technology file.
To control the scope of the check, specify a mode value by using the
checkViaArrayMaxStackLevel parameter. The syntax is
axSetIntParam "droute" "checkViaArrayMaxStackLevel" value
Mode value
Description
Ignore the maximum stack level rule check when all stacked vias
are via arrays.
Check the maximum stack level rule for stacked via arrays.
Ignore the maximum stack level rule check when at least one
stacked via is a via array.
Ignore the maximum stack level rule check when all stacked vias
are aligned via arrays (overlapped with at least two cuts.
The following figure and table show the scope of the maximum stack
level check for each checkViaArrayMaxStackLevel mode when
you specify a maxStackLevel value of 4.

C-27
Case A
Case B
Case C
Case D
Case E
M6
M6
M6
M6
M6
M5
M5
M5
M5
M5
M4
M4
M4
M4
M4
M3
M3
M3
M3
M3
M2
M2
M2
M2
M2
M1
M1
M1
M1
M1
checkViaArrayMaxStackLevel Case A
Mode
Violation
Violation
Violation
Violation
Case B
Case C
Case D
Case E
Violation
Violation
Violation
Violation
Violation

You can specify a fat wire threshold at which wires on another layer
that are within the defined extension range of the fat wire must meet
the recommended spacing. Use the following parameters to specify
the neighboring layer fat extension range spacing rule:

C-28
neighboringLayerFatThreshold
neighboringLayerFatExtensionRange
neighboringLayerM1RecommendedSpacing
...
For example, as shown in the following figure, if M2 width is greater

than or equal to neighboringLayerFatThreshold and M3 is
within neighboringLayerFatExtensionRange, the
recommended spacing (N) applies; otherwise, the minimum spacing
(D) applies.
M3
M3
M3
M3
ext range
ext range
ext range
M2
width
ext range
The syntax is
(axSetRealParam "droute"
"neighboringLayerFatThreshold"0.000)
;; N: neighboring layer fat threshold (applied to all layers)

C-29
(axSetRealParam
"droute""neighboringLayerFatExtensionRange" 0.000)
;; N: neighboring layer fat extension range (applied to all
;; layers)
"neighboringLayerM1RecommendedSpacing" 0.000)
;; N: neighboring layer recommended spacing for M1
...
Parallel Length Rule

If two or more fat wire segments of different width are to be
connected, the router merges them. The width of the merged wire is
the width of the fattest wire, and the length of the merged wire is
determined when the parallel length is computed. That is, the
spacing between the merged wire and those wires running parallel
to it is based on the width and length of the merged wire.
You control whether the wire segments are to be merged with fat
neighboring shapes only (the default) or with all neighboring shapes
by using the parallelLengthMode parameter.

C-30
The syntax is
axSetIntParam droute parallelLengthMode value
Value
Description
Merge with fat neighboring shapes only (the default).
Merge with all neighboring shapes.
Before you set the parallel length rule mode, you must first define the
following attributes in the technology file: fatTblThreshold,
fatTblParallelLength, and fatTblSpacing. For example,
fatTblThreshold = (0,0.201,0.381,1.501,4.501)
fatTblParallelLength = (0,0.381,0.381,1.501,4.501)
fatTblSpacing = (0.1,0.12,0.16,0.5,1.5,
0.12,0.12,0.16,0.5,1.5,
0.16,0.16,0.16,0.5,1.5,
0.5,0.5,0.5,0.5,1.5,
1.5,1.5,1.5,1.5,1.5)
Jog Wire Rules

The jog wire rules are described in the following sections:
Small Jog Rule
Jog Wire End-of-Line Via Rule
Jog Wire Via Keepout Region Rule
Small Jog Rule

Use the smallJogMinLength parameter to specify the minimum
length allowed for a small jog.
Jog Wire Rules
C-31
The syntax is
axSetIntParam "droute" "smallJogMinLength" value
Value
Description
The small jog rule is not checked.
The jog length needs to be larger than or equal to 1/4 pitch of the wire
tracks for the routing layer.
The jog length needs to be larger than or equal to 1/2 pitch of the wire
tracks for the routing layer.
When you specify a value of 1 or 2, the small jog rule is checked, and
then fixed by the search-and-repair operation. A violation occurs
when the length of the jog is shorter than 1 or 2 times the quarter
pitch of the wire tracks.
For example, when you enter the following:

axSetIntParam "droute" "smallJogMinLength" 2
a violation occurs when the length of the jog is shorter than half the
pitch of the wire track.

C-32
Jog Wire End-of-Line Via Rule

Use the endOfLineViaJogLength, endOfLineViaJogWidth,
and endOfLineViaEncWidth attributes to specify the jog wire
end-of-line via rule. These attributes let you define additional location
constraints for vias that connect to short jog wires. Define these
attributes in the via Layer section of the technology file.
Jog Wire Via Keepout Region Rule

Use the jogWireViaKeepoutTblSize,
jogWireViaKeepoutEncThreshold, and
jogWireViaKeepoutMinSize attributes to specify the jog wire via
keepout region rule. When you do not want a single via on a jog wire
to be placed too close to the outside corner of the jog wire, use this
rule to define a via keepout region at the jog wire corner. Define
these attributes in the DesignRule section of the technology file,
where you specify different values between the metal and via layer.
For example,
DesignRule {
layer1
layer2
minEnclosure
jogWireViaKeepoutTblSize
jogWireViaKeepoutEncThreshold
jogWireViaKeepoutMinSize
}
= "M1"
= "V1"
= 0
= 3
= (0.005,0.015,0.025)
= (0.08,0.06,0)

Use the fatWireViaKeepoutTblSize,
fatWireViaKeepoutWidthThreshold,
fatWireViaKeepoutMinSize, and
C-33
fatWireViaKeepoutEnclosure attributes to specify the fat wire

via keepout region rule. When you do not want the via at the
end-of-line upper-fat wire or lower-fat wire to be placed too close to
the corner of the fat wire, use this rule to define a via keepout region
at the end-of-line corners. Define this rule in the DesignRule section
of the technology file, where you can specify different values
between the via and upper metal layer and between the via and
lower metal layer. For example,
DesignRule
{
layer1
layer2
minSpacing
minEnclosure
fatWireViaKeepoutTblSize
fatWireViaKeepoutWidthThreshold
fatWireViaKeepoutMinSize
fatWireViaKeepoutEnclosure
}
DesignRule

C-34
=
=
=
=
=
=
=
=
"V1"
"M2"
0
0
2
(0.5,1.0)
(0.18,0.36)
(0.05,0.10)
{
layer1
layer2
minSpacing
minEnclosure
fatWireViaKeepoutTblSize
fatWireViaKeepoutWidthThreshold
fatWireViaKeepoutMinSize
fatWireViaKeepoutEnclosure
=
=
=
=
=
=
=
=
"V1"
"M1"
0
0
1
(0.5)
(0.18)
(0.05)
D
Astro Parameters
This appendix addresses various categories of Astro parameters.

This appendix contains the following sections:
Using Parameters and Getting Information
Clock Tree Synthesis Parameters
Common Graph Parameters
Crosstalk Parameters
Global Route Parameters
PDS Optimization Parameters
Rectilinear Parameters
Timing Parameters
D-1

You can use the axSetIntParam and axSetRealParam
commands to set integer and real parameters for various Astro
operations. In general, adjusting these parameters, other than those
you can set in dialog boxes, is an advanced operation. The syntax is
axSetIntParam "operation" "param" value
Option
Description
operation
The operation for which you are setting a parameter. For example,
place indicates placement, route indicates routing, trackAssign
indicates track assignment, groute indicates global routing, droute
indicates detail routing, xt indicates crosstalk, and so forth.
param
The name of the parameter you want to set.
value
The integer value of the parameter.
For example, to specify that a split timer process always be turned

on, enter
axSetIntParam "route" "splitTimer" 1
The axSetRealParam command works the same way, but takes a

floating-point value as its final argument.
You enter the set commandsas well as the print, search, and show
parameter commandsin the command window.
Use the axPrintParams command to print (display) available

parameters for all operations or a specific operation, together
with the range of legal values for each parameter. The syntax is
axPrintParams "all"|"operation"
Appendix D: Astro Parameters

D-2
Here is a sample of the information that is displayed in the

command window:
(axSetIntParam "route" "splitTimer" -1)
;;
range [-1,1], default=-1;
;;
-1: Tool decides whether to split timer process
;;
0: Never split timer process
;;
1: Always split timer process
To print the available parameters and their respective values and

definitions, for all operations, enter
axPrintParams "all"
To print the available parameters and their respective values and

definitions for a particular operation, routing for example, enter
axPrintParams "route"
Use the axSearchParams command to display information for

parameters that contain a matched string. The syntax is
axSearchParams match_string
Use the axShowParams command to display the current

parameter settings. Enter
axShowParams "all"
Detailed descriptions of many of the parameters are provided in the

next sections. The parameters are grouped by operation, and sorted
alphabetically within each group.

D-3
Information about all the parameters is provided in SolvNet articles,

such as the following:
Astro Z-2007.03 CTS Parameters (019738)
Public "cg" params list and Usage (019556)
Details of Crosstalk Commands and Parameters (015623)
Detailed Routing Parameter Documentation (019744)
Global Route Parameter Document in IC Compiler and Astro

(019656)
Parameters Support by Astro LPE (019730)
Optimization "pds" public params list and usage (019752)
Parameters Support by Astro Placement (019729)
Parameters Support by Astro Rectilinear (019728)
Parameters Supported By Astro Timer (019402)
Go to http://solvnet.synopsys.com.

D-4

The clock tree synthesis parameters are divided into the following
sub-categories, each of which is documented in a separate section:
Clock Tree Synthesis General Behavior Parameters
Clock Tree Synthesis Legalization Controlling Placement

Parameters
Clock Tree Synthesis Effort Related Parameters
Clock Tree Synthesis Clock Constraint Targets Parameters
Clock Tree Synthesis Clock Constraint Rules Parameters
Clock Optimization Parameters
Clock Routing Parameters
Standalone Clock Optimization Parameters
Other Clock Tree Synthesis Parameters
Changing Standard Naming Convention Parameters
Changing Default Interpretation of Clock Constraints Parameters

D-5
Clock Tree Synthesis General Behavior Parameters

Table D-1 lists the Astro clock tree synthesis general behavior
parameters.
Table D-1 List of Clock Tree Synthesis General Behavior Parameters
Parameter
Description
best condition
typical condition
worst condition
The best condition parameter optimizes the

skew for best operating conditions.
The typical condition parameter optimizes
the skew for typical operating conditions.
The worst condition parameter optimizes the
skew for worst operating conditions.
cto: buffer sizing

cto: cell sizing
cto: reconfiguration
These parameters determine the order of

operations during embedded clock-tree
optimization.
delay insertion before gate
Enables or disables clock tree synthesis to add

any delay cells before clock gate.
gated clock tree
Turns gated clock tree synthesis on or off.
move clock gates
When set to 1, forces all clock gates move to the

center of their fanout.
size up clock gates
When set to 1, forces all clock gates to largest

size.
best condition, typical condition, worst condition

The best condition parameter optimizes the skew for best
operating conditions.

D-6
The typical condition parameter optimizes the skew for typical

operating conditions.
The worst condition parameter optimizes the skew for worst
conditions.
These three parameters determine the relative weight given to each
operating condition. Non-zero values means skew needs to be
optimized for the corresponding condition during clock tree
synthesis. A value of zero means that no optimization effort is
expended for the corresponding condition.
Note:
If an operating condition is deselected in the clock tree synthesis
dialog box, its weight will be set to zero irrespective of the setting
in this parameter.
These three parameter values indicate relative priority among the
three conditions during clock tree synthesis, with higher values
indicating higher priority. The absolute value of the parameters
carries no meaning; only the order of the values affects the behavior
of the tool.
Usage.
axSetIntParam "acts" "best condition" 1
axSetIntParam "acts" "typical condition" 1
axSetIntParam "acts" "worst condition" 1
Range.
The valid values of best condition, typical condition, and
worst condition range between 0 and 999999. The default is 1.

D-7
cto: buffer sizing

cto: cell sizing
These parameters determine the order of operations in embedded
clock-tree synthesis:
The cto: buffer sizing parameter sets the order of buffer

sizing in optimization.
The cto: buffer relocation parameter sets the order of

buffer relocation in optimization.
The cto: cell sizing parameter sets the order of cell sizing
in optimization.
The cto: cell relocation parameter sets the order of cell

relocation in optimization.
The cto: level adjustment parameter sets the order of

level adjustment in optimization.
The cto: delay insertion parameter sets the order of delay

insertion in optimization.
The cto: dummy load insertion parameter sets the order

of dummy load insertion in optimization.
The cto: reconfiguration parameter sets the order of

reconfiguration in optimization.

D-8
The value of each parameter determines the order of the

corresponding operation in optimization. If -1 or 8 is set, the
corresponding type of optimization is not performed.
If more than one of these parameters have the same value, the
highest priority operation among them, as determined by this list, is
performed: BS>CS>BR>CR>LA>DI>ReCon>DL. The other
operations with the same value will be omitted.
These parameters are only for embedded CTO.
Usage.
axSetIntParam
axSetIntParam
axSetIntParam
axSetIntParam
axSetIntParam
axSetIntParam
axSetIntParam
axSetIntParam
"acts"
"acts"
"acts"
"acts"
"acts"
"acts"
"acts"
"acts"
"cto:
"cto:
"cto:
"cto:
"cto:
"cto:
"cto:
"cto:
buffer sizing" 4
buffer relocation" 6
cell sizing" 3
cell relocation" 5
level adjustment" 0
delay insertion" 1
dummy load insertion" 7
reconfiguration" 2
Range.
The valid values of all these parameters range between -1 and 8.
Table D-2 lists the default values of these parameters.
Table D-2 Default Values of Parameters
Parameter Name
Default Value
cto: buffer sizing
cto: cell sizing

D-9
Table D-2 Default Values of Parameters

Parameter Name
Default Value
cto: dummy load

insertion
delay insertion before gate

The delay insertion before gate parameter enables or
disables clock tree synthesis to add any delay cells before clock gate.
Astro clock tree synthesis builds the clock tree one gate level at a
time. That is, for every clock-gating cell pre-existing in the clock tree,
Astro clock tree synthesis will first do a clock tree synthesis of its
fanout and hook up the clock-gating cell to the next higher level
subtree as appropriate. These clock-gating cells, as well as any cells
that are connected to the clock tree having a sync pin but not being
a register or latch, are called hookup pins.
When this parameter is set to 0, clock tree synthesis is not allowed
to add any delay cells before a hookup pin, which it might otherwise
do in order to delay-balance the buffer level driving the hookup pin;
all hookup pins will be connected directly to the driver of that buffer
level.
Usage.
To enable clock tree synthesis to add delay cells before a clock gate,
enter the following:

D-10
axSetIntParam "acts" "delay insertion before gate" 1
Range.
The valid values are 0 or 1. The default is 1.
gated clock tree

The gated clock tree parameter can be used to turn on or turn
off gated clock tree synthesis. If it is turned off, all cells in the fanout
of the root clock net will be treated as clock sinks.
Usage.
To turn on gated clock tree synthesis, enter the following:
axSetIntParam "acts" "gated clock tree" 1
When set to 0, gated clock tree synthesis is turned off.

Range.
move clock gates

When set to 1, the move clock gates parameter forces all clock
gates to move to the center of their fanout. It can be used to
preprocess the clock tree for pre-existing gates.
The effect of this parameter is different from the Clock Common
Options dialog box setting for gate relocation.

D-11
Using this parameter, all gating cells in the clock tree are moved and
then located at the center of their fanout before any other processing.
With the dialog box option, the clock gates will be moved only if
necessary.
Usage.
To force all clock gates to move to the center of their fanout, enter the
following:
axSetIntParam "acts" "move clock gates" 1
Range.
size up clock gates

When set to 1, the size up clock gates parameter forces all
clock gates to the largest available size. It can be used to preprocess
the clock tree for pre-existing gates.
The effect of this parameter is different from the Clock Common
Options dialog box setting for gate sizing.
Using this parameter, all gating cells in the clock tree are sized to
their largest available drive strength before any other processing.
Using the dialog box option, the clock gates will be sized only if
necessary.
Usage.
To force all clock gates to the largest size, enter the following:

D-12
axSetIntParam "acts" "size up clock gates" 1
Range.
Clock Tree Synthesis Legalization Controlling

Placement Parameters
Table D-3 lists the clock tree synthesis legalization controlling
placement parameters.
Table D-3 List of Legalization Controlling Placement Parameters
Parameter
Description
ECO placement
Used to perform a global ECO placement after

initial clock tree synthesis.
ECO weight
Defines an ECO weight that is given to all cells

connected to the clock tree.
legalize placement
Controls whether placement legalization for

cells added by clock tree synthesis is
performed.
OV
Controls whether overlap removal is used to

legalize clock buffers added by Astro.
set OV maximum displacement
Sets the maximum displacement during

overlap.
ECO placement
The ECO placement parameter is used to perform a global ECO
placement after initial clock tree synthesis; that is, before embedded
clock tree optimization. While this parameter is set to 1 by default, the

D-13
ECO placement may not actually be performed because the overlap

removal switch is also set to 1 by defaultwhich turns off the effect
of this parameter.
Usage.
To perform a global ECO placement after initial clock tree synthesis,
axSetIntParam "acts" "ECO placement" 1
Range.
ECO weight
The ECO weight parameter defines an ECO weight that is given to
all cells connected to the clock tree (sinks, inverters, or buffers) to
give preference to clock-related cells during overlap removal.
Usage.
axSetIntParam "acts" "ECO weight" 2
Range.
The valid values of this parameter range between 0 and 6. The
default is 2.

D-14
legalize placement
The legalize placement parameter controls whether placement
legalization for cells added by clock tree synthesis is performed or
not. Disabling legalization makes the switches for overlap and ECO
placement ineffective.
Without legalization, buffers will be dropped exactly at the location
deemed optimal by clock tree synthesis. Therefore, not performing
legalization can be useful for debugging to get an upper bound on
quality of results (QoR) and to separate legalization problems from
other issues.
Usage.
To control whether placement legalization is performed for the cells
added by clock tree synthesis, use the following syntax:
axSetIntParam "acts" "legalize placement" 1
Range.
OV
The OV parameter controls whether overlap removal is used to
legalize clock buffers added by Astro. If overlap removal is used,
every buffer will be individually legalized as soon as it gets created.
If overlap removal is turned on, ECO placement will be automatically
turned off.

D-15
If legalize placement is turned on but overlap removal is turned

off, the lock buffer locations will be chosen to take advantage of
available space but no legalization will be performed to move other
cells.
Usage.
To control whether overlap removal is used to legalize clock buffers
added by Astro, use the following syntax:
axSetIntParam "acts" "OV" 1
Range.
set OV maximum displacement

The set OV maximum displacement parameter sets the
maximum displacement during overlap. The unit is um in DB.
Usage.
To set the maximum displacement during overlap, use the following
syntax:
axSetIntParam "acts" "set OV maximum displacement"
2147483647
Range.
The valid values of this parameter range between 0 and 999999999.
The default is 2147483647.

D-16
Clock Tree Synthesis Effort Related Parameters

Table D-4 lists the clock tree synthesis effort related parameters
Table D-4 List of Effort Related Parameters
Parameter
Description
clustering effort
Sets the clustering effort during clock tree

synthesis.
reclustering iterations
Sets the minimum number of iterations that the

clustering algorithm takes during clock tree
construction.
synthesis effort
The value of this parameter is multiplied by the

reclustering iterations to determine the number of
reclustering iterations actually used.
clustering effort
The clustering effort parameter sets the clustering effort
during clock tree synthesis. Clustering effort is orthogonal to the
number of reclustering iterations. For example, if effort is set to high,
the high-effort clustering will be executed for the number of iterations
determined by the reclustering iterations and synthesis
effort parameters.
Low and medium effort are the same. If high effort is selected, a
more involved clustering algorithm based on pairing is invoked.
Usage.
To set the effort to low, enter the following:
axSetIntParam "acts" "clustering effort" 1

D-17
Range.
default is 1.
Table D-5 lists the valid values of the clustering effort
parameter.
Table D-5 Valid Values of the clustering effort Parameter
Value
Description
Low effort
Medium effort
High effort
reclustering iterations
The reclustering iterations parameter sets the minimum
number of iterations that the clustering algorithm takes during clock
tree construction. The actual number of iterations is determined by
the product of synthesis effort and reclustering
iterations.
Usage.
To set the minimum number of iterations taken by the clustering
algorithm during clock tree construction, use the following syntax:
axSetIntParam "acts" "reclustering iterations" 4

D-18
Range.
default is 4.
synthesis effort
The synthesis effort parameter sets the synthesis effort which
is identical to the Synthesis Effort option in the Clock Common
Options dialog box.
Setting the value in the Clock Common Options dialog box
overwrites the value of the parameter and setting the parameter after
using the dialog box overwrites the dialog box value.
The value of this parameter is multiplied by the value of
reclustering iterations to determine the number of
reclustering iterations actually used.
Usage.
To set a value for synthesis effort, use the following syntax:
axSetIntParam "acts" "synthesis effort" 2
Range.
default is 2.

D-19
Clock Tree Synthesis Clock Constraint Targets

Parameters
Table D-6 lists the clock constraints targets parameters
Table D-6 List of Clock Constraints Targets Parameters
Parameter
Description
target: best transition delay fall
Sets the target of the best transition delay

fall of each clock net.
target: best transition delay rise
Sets the target of the best rise transition

time of each clock net.
target: clock insertion delay
Sets a target for the overall insertion delay

of the clock tree.
target: clock skew
Sets a target for the overall skew of the

clock tree.
target: load capacitance
Sets the load capacitance target.
target fanout
Sets the fanout target.
target load relax
Enables (or disables) relaxation of the

target load with each buffer level.
target: transition delay fall
Sets the target of the fall transition time of

each clock net.
target: transition delay rise
Sets the target of the rise transition time of

each clock net.
target: worst transition delay fall
Sets the target of the worst fall transition

target: worst transition delay rise
Sets the target of the worst rise transition


D-20
target: best transition delay fall

The target: best transition delay fall parameter sets
the target of the best transition delay fall of each clock net. It is
directly used by clock tree synthesis when creating the tree topology.
The clustering and buffer level creation will be done such that each
resulting clock net has a transition time close to the target. This
means that the actual transition time can be slightly bigger or smaller
than the target.
If the clock tree analyzer is used, the target transition value will be
overridden by clock tree analyzer. This best fall transition target will
override the target: transition delay fall.
Usage.
To set the target of the best transition delay fall of each clock net, use
axSetRealParam "acts" "target: best transition delay fall"
0.000
Range.
The valid values range between 0.000 and 999999.000. The default
is 0.0.
target: best transition delay rise

The target: best transition delay rise parameter sets the
target of the best rise transition time of each clock net. It is directly
used by clock tree synthesis when creating the tree topology. The
clustering and buffer level creation is done such that each resulting

D-21
clock net has a transition time close to the target. This means that
the actual transition time can be slightly bigger or smaller than the
target.
overridden by the clock tree analyzer. This best rise transition target
will override the target: transition delay rise.
Usage.
To set the target of the best rise transition time of each clock net, use
axSetRealParam "acts" "target: best transition delay rise"
0.000
Range.
is 0.0.
target: clock insertion delay

This target: clock insertion delay parameter sets the
clock insertion delay target. It is equivalent to the Clock Common
Options dialog box setting for clock insertion delay.
This parameter is used as a target for the overall insertion delay of
the clock tree; that is, if the tree generated by clock tree synthesis
has smaller insertion delay, delay insertion will be performed to meet
the target. This target value will be overridden by a target specified
through the set_clock_latency setting in the SDC file.

D-22
Usage.
To set the clock insertion delay, use the following syntax:
axSetRealParam "acts" "target: clock insertion delay" 0.000
Range.
is 0.0.
target: clock skew

The target: clock skew parameter sets the clock skew target.
It is equivalent to the Clock Common Options dialog box setting for
skew target. It is used as a target for the overall skew of the clock
tree. However, it has an effect only if the clock tree analyzer is used.
If the SDC file specifies the set_clock_uncertainty constraint,
the smaller of the targets in the dialog box and the SDC file is used.
Usage.
To set the skew target, use the following syntax:
axSetRealParam "acts" "target: clock skew" 0.000
Range.
is 0.0.

D-23
target: load capacitance

The target: load capacitance parameter sets the load
capacitance target. It is directly used by clock tree synthesis when
creating the tree topology. The clustering and buffer level creation is
done such that the load capacitance (wire and pin) of each clock
buffer is close to the target. This means that the actual load can
deviate by a few units from the specified target.
Usage.
axSetRealParam "acts" "target: load capacitance" 0.000
Range.
is 0.0.
target fanout
The target fanout parameter sets the fanout target. It can be
used directly by clock tree synthesis when creating the tree topology.
The clustering and buffer level creation will be done such that the
fanout of each clock buffer is close to the target. This means that the
actual fanout can deviate by a few fanouts from the specified target.
Usage.
To set the fanout target, use the following syntax:
axSetIntParam "acts" "target fanout" 32

D-24
Range.
The valid values range between 0 and 999999. The default is 32.
target load relax

The target load relax parameter turns controls relaxation of
the target load with each buffer level. When this parameter is set, the
target load is used only for the leaf level of the clock tree. For all
higher buffer levels, the actual target load is calculated as:
target load actual = target
load*(1+targetLoad_relax(buffer_level-1))
Usage.
To control relaxation of the target load with each buffer level, use the
following syntax:
axSetRealParam "acts" "target load relax" 1.000
Range.
is 0.0.
target: transition delay fall

The target: transition delay fall parameter sets the
target of the fall transition time of each clock net. It is directly used by
clock tree synthesis when creating the tree topology. The clustering
and buffer level creation is done such that each resulting clock net
has a transition time close to the target. This means that the actual
transition time can be slightly bigger or smaller than the target.

D-25
overridden by the clock tree analyzer. This fall transition target will be
overridden if the fall target for best and worst are specified
separately.
Usage.
axSetRealParam "acts" "target: transition delay fall" 0.000
Range.
is 0.0.
target: transition delay rise

The target: transition delay rise parameter sets the
target of the rise transition time of each clock net. It is directly used
by clock tree synthesis when creating the tree topology. The
clustering and buffer level creation will be done such that each
than the target.
overridden by the clock tree analyzer. This rise transition target will
be overridden if the rise target for best and worst are specified
separately.
Usage.
To set the target of the rise transition time of each clock net, use the
following syntax:

D-26
axSetRealParam "acts" "target: transition delay rise" 0.000
Range.
is 0.0.
target: worst transition delay fall

The target: worst transition delay fall parameter sets
the target of the worst fall transition time of each clock net. It is
The clustering and buffer level creation is done such that each
than the target.
overridden by the clock tree analyzer. This worst fall transition target
will override target: transition delay fall.
Usage.
To set the target of the worst fall transition time of each clock net, use
axSetRealParam "acts" "target: worst transition delay fall"
0.000
Range.
is 0.0.

D-27
target: worst transition delay rise

The target: worst transition delay rise parameter sets
the target of the worst rise transition time of each clock net. It is
The clustering and buffer level creation will be done such that each
than the target.
overridden by the clock tree analyzer. This worst rise transition target
will override target: transition delay rise.
Usage.
To set the target of the worst rise transition time of each clock net,
use the following syntax:
axSetRealParam "acts" "target: worst transition delay rise"
0.000
Range.
is 0.0.

D-28
Clock Tree Synthesis Clock Constraint Rules

Parameters
Table D-7 lists the clock constraints rules parameters
Table D-7 List of Clock Constraint Rules Parameters
Parameter
Description
rule: maximum capacitance
Limits the load capacitance (wire and pin)

each buffer in the clock tree may drive.
rule: maximum insertion delay
Limits the maximum insertion delay time of

each clock net.
rule: maximum skew
Sets one of the global timing/clock tree

constraints.
rule: maximum transition delay fall
Limits the maximum fall transition time of

each clock net.
rule: maximum transition delay rise
Limits the maximum rise transition time of

each clock net.
rule: maximum wire length
Used in topology-based buffer insertion

with global route.
rule: minimum insertion delay
Limits the minimum insertion delay time of

each clock net.
rule: minimum transition delay fall
Limits the minimum fall transition time of

each clock net.
rule: minimum transition delay rise
Limits the minimum rise transition time of

each clock net.
rule maximum buffer levels
Limits the level of buffers clock tree

synthesis might add to the value specified.
rule maximum fanout
Limits the fanout each buffer in the clock

tree may drive.

D-29
rule: maximum capacitance

The rule: maximum capacitance parameter limits the load
capacitance (wire and pin) each buffer in the clock tree may drive.
This parameter is equivalent to the Maximum Load Capacitance
option in the Clock Tree Constraints dialog box.
If rule: maximum capacitance is smaller than the target load
capacitance, the rule: maximum capacitance parameter will be
used as the target capacitance. Target will be 80% of constraint if the
constraint is smaller than the target.
Usage.
To limit the load capacitance (wire and pin) each buffer in the clock
tree may drive, use the following syntax:
axSetRealParam "acts" "rule: maximum capacitance" -0.500
Range.
The valid values of this parameter range between 0.000 and
999999.000. The default is -0.5.
rule: maximum insertion delay

The rule: maximum insertion delay parameter limits the
maximum insertion delay time of each clock net. It is overwritten by
the Maximum Insertion Delay option in the Clock Tree Constraints
dialog box.

D-30
Usage.
To limit the maximum insertion delay time of each clock net, use the
following syntax:
axSetRealParam "acts" "rule: maximum insertion delay" 0.000
Range.
999999.000. The default is 0.0.
rule: maximum skew

The rule: maximum skew parameter sets one of the global timing/
clock tree constraints.
Usage.
To set one of the global timing/clock tree constraints, use the
following syntax:
axSetRealParam "acts" "rule: maximum skew" 0.000
Range.
999999.000. The default is 0.0.

D-31
rule: maximum transition delay fall

The rule: maximum transition delay fall parameter limits
the maximum fall transition time of each clock net. It is overwritten by
the Maximum Transition Delay option in the Clock Tree Constraints
dialog box.
If rule: maximum transition delay fall is smaller than the
target transition time, then rule: maximum transition delay
fall will be used as target transition time. Target will be 80% of
constraint if the constraint is smaller than the target.
Usage.
To limit the maximum fall transition time of each clock net, use the
following syntax:
axSetRealParam "acts" "rule: maximum transition delay fall"
-0.500
Range.
999999.000. The default is -0.5.
rule: maximum transition delay rise

The rule: maximum transition delay rise parameter limits
the maximum rise transition time of each clock net. It is overwritten
by the Maximum Transition Delay option in the Clock Tree
Constraints dialog box.

D-32
If rule: maximum transition delay rise is smaller than the

target transition time, then rule: maximum transition delay
rise will be used as target transition time. Target will be 80% of
constraint if the constraint is smaller than the target.
Usage.
To limit the maximum rise transition time of each clock net, use the
following syntax:
axSetRealParam "acts" "rule: maximum transition delay rise"
-0.500
Range.
999999.000. The default is -0.5.
rule: maximum wire length

The rule: maximum wire length parameter is used in
topology-based buffer insertion with global route.
Usage.
To use topology-based buffer insertion with global route, use the
following syntax:
axSetRealParam "acts" "rule: maximum wire length" 0.000

D-33
Range.
999999.000. The default is 0 which will use a default value (2000
um).
rule: minimum insertion delay

The rule: minimum insertion delay parameter limits the
minimum insertion delay time of each clock net. It is overwritten by
the Minimum Insertion Delay option in the Clock Tree Constraints
dialog box.
Usage.
To limit the minimum insertion delay time of each clock net, use the
following syntax:
axSetRealParam "acts" "rule: minimum insertion delay" 0.000
Range.
999999.000. The default is 0.
rule: minimum transition delay fall

The rule: minimum transition delay fall parameter limits
the minimum fall transition time of each clock net.
Usage.
To limit the minimum fall transition time of each clock net, use the
following syntax:
D-34
axSetRealParam "acts" "rule: minimum transition delay fall"

0.000
Range.
999999.000. The default is 0.0.
rule: minimum transition delay rise

The rule: minimum transition delay rise parameter limits
the minimum rise transition time of each clock net.
Usage.
To limit the minimum rise transition time of each clock net, use the
following syntax:
axSetRealParam "acts" "rule: minimum transition delay rise"
0.000
Range.
999999.000. The default is 0.0.
rule maximum buffer levels

The rule maximum buffer levels parameter specifies the
maximum number of buffer levels that clock tree synthesis is allowed
to add. It is equivalent to the Maximum Buffer Level option in the
Clock Tree Constraints dialog box. It is important to understand that

D-35
this constraint will be applied per gate level; that is, if your clock tree
has several serial gating cells, each subtree can have up to rule
maximum buffer levels levels.
Another thing to note is that when the maximum number of levels is
reached clock tree synthesis will stop any further processing; that is,
if an unrealistic constraint is specified the resulting tree will still
contain DRC violations.
Usage.
To limit the level of buffers clock tree synthesis might add, use the
following syntax:
axSetIntParam "acts" "rule maximum buffer levels" 20
Range.
rule maximum fanout

The rule maximum fanout parameter limits the fanout that each
buffer in the clock tree may drive. It is equivalent to the Maximum
Fanout option in the Clock Tree Constraints dialog box.
If rule maximum fanout is smaller than the target fanout, the
rule maximum fanout parameter will be used as target fanout.
Usage.
To limit the fanout that each buffer in the clock tree may drive, use the
following syntax:

D-36
axSetIntParam "acts" "rule maximum fanout" 64
Range.
Clock Optimization Parameters

Table D-8 lists the clock optimization parameters.
Table D-8 List of Clock Optimization Parameters
Parameter
Description
cto: FF relocation
Enables (or disables) flip-flop relocation during

optimization.
cto: FF sizing
Enables (or disables) flip-flop sizing during

optimization.
cto: latch relocation
Enables (or disables) latch relocation during

optimization.
cto: latch sizing
Enables (or disables) latch sizing during

optimization.
optimization level
Sets the optimization level.
cto: FF relocation
The cto: FF relocation parameter enables or disables flip-flop
relocation during optimization. This parameter is used only for
embedded CTO.
Usage.
To turn on flip-flop relocation during optimization, enter the following:

D-37
axSetIntParam "acts" "cto: FF relocation" 1
Range.
cto: FF sizing
The cto: FF sizing parameter enables or disables flip-flop sizing
during optimization. This parameter is used only for embedded CTO.
Usage.
To turn on flip-flop sizing during optimization, enter the following:
axSetIntParam "acts" "cto: FF sizing" 1
Range.
cto: latch relocation

The cto: latch relocation parameter enables or disables
latch relocation during optimization. This parameter is used only for
embedded CTO.
Usage.
To turn on latch relocation during optimization, enter the following:
axSetIntParam "acts" "cto: latch relocation" 1
Range. The valid values are 0 or 1. The default is 0.

D-38
cto: latch sizing

The cto: latch sizing parameter enables or disables latch
sizing during optimization. This parameter is used only for
embedded CTO.
Usage.
To turn on latch sizing during optimization, enter the following:
axSetIntParam "acts" "cto: latch sizing" 1
Range.
optimization level
The optimization level parameter sets the optimization level.
It is the same as the Optimization Effort option in the Clock Common
Options dialog box. Higher values correspond to higher effort.
Usage.
To set the optimization level, use the following syntax:
axSetIntParam "acts" "optimization level" 3
Range.
default is 3.

D-39
Clock Routing Parameters

Table D-9 lists the clock routing parameters.
Table D-9 List of Clock Routing Parameters
Parameter
Description
ECO Route
Determines whether ECO route is

performed after postroute clock tree
optimization.
set default route rule on bottom level
Resets the variable route rule applied to

the sub clock tree nets for the bottom n
nets.
set default route rule on leaf net
Resets the variable route rule applied to

the sub clock tree nets for the lowest level
nets (leaf nets) only.
ECO Route
The ECO Route parameter determines whether ECO route is
performed after postroute clock tree optimization.
Usage.
To perform ECO route after postroute clock tree optimization, enter
the following:
axSetIntParam "acts" "ECO Route" 1
Range.

D-40
set default route rule on bottom level

By default, clock tree synthesis propagates a variable route rule
applied to the root clock net before clock tree synthesis to all its sub
clock tree nets. The set default route rule on bottom
level parameter resets the variable route rule applied to the sub
clock tree nets for the bottom n nets, where n is the value of the
parameter.
Usage.
axSetIntParam "acts" "set default route rule on bottom level"
0
Range.
default is 0.
set default route rule on leaf net

By default, clock tree synthesis propagates a variable route rule
applied to the root clock net before clock tree synthesis to all its sub
clock tree nets. The set default route rule on leaf net
parameter resets the variable route rule applied to the sub clock tree
nets for the lowest level nets (leaf nets) only.
Usage.
axSetIntParam "acts" "set default route rule on leaf net" 0
Range.

D-41
Standalone Clock Optimization Parameters

Table D-10 lists the Astro standalone clock optimization parameters.
Table D-10 List of Stand-alone Clock Optimization Parameters
Parameter
Description
delay balance: clock skew offset
Sets stand-alone CTO allowed

percentage change of individual clock's
skew for delay balance.
delay balance: insertion delay offset
Sets stand-alone CTO allowed insertion

delay offset (percentage) difference for
delay balance.
fix load cap violation
Turns on (or off) stand-alone CTO to fix

load capacitance violations.
fix transition violation
Turns on (or off) stand-alone CTO to fix

transition violations.
minimize placement changes
Turns on (or off) stand-alone CTO to

minimize placement changes.
minimize placement changes effort
Sets effort for minimizing placement

changes.
delay balance: clock skew offset

The delay balance: clock skew offset parameter sets the
allowed percentage change of individual clock's skew for delay
balance during stand-alone CTO.
Usage.
axSetRealParam "aco" "delay balance: clock skew offset" 0.050

D-42
Range.
The valid values of this parameter range between 0.000 and 1.000.
The default is 0.05.
delay balance: insertion delay offset

The delay balance: insertion delay offset parameter
sets the allowed insertion delay offset (percentage) difference for
delay balance during stand-alone CTO.
Usage.
axSetRealParam "aco" "delay balance: insertion delay offset"
0.010
Range.
fix load cap violation

The fix load cap violation parameter turns on (or off)
stand-alone CTO to fix load capacitance violations.
Usage.
To turn on stand-alone CTO to fix load capacitance violation, enter
the following:
axSetIntParam "aco" "fix load cap violation" 1

D-43
Range.
fix transition violation

The fix transition violation parameter turns on (or off)
stand-alone CTO to fix transition violations.
Usage.
To turn on stand-alone CTO to fix transition violations, enter the
following:
axSetIntParam "aco" "fix transition violation" 1
minimize placement changes

The minimize placement changes parameter turns on (or off)
stand-alone CTO to minimize placement changes.
Usage.
To turn on stand-alone CTO to minimize placement changes, enter
the following:
axSetIntParam "aco" "minimize placement changes" 1
Range.

D-44
minimize placement changes effort

The minimize placement changes effort parameter sets the
level of effort for minimizing placement changes.
Usage.
To set medium effort for minimizing placement changes, enter the
following:
axSetIntParam "aco" "minimize placement changes effort" 2
Range.
default is 2.
Table D-11 lists the valid values of the minimize placement
changes effort parameter and their description.
Table D-11 Valid Values of the minimize placement changes effort
Parameter
Value
Description
Low effort
Medium effort
High effort

D-45
Other Clock Tree Synthesis Parameters

Table D-12 lists other Astro clock tree synthesis parameters
Table D-12 List of Other Clock Tree Synthesis Parameters
Parameter
Description
clock tree root minimum fanout
Used as part of the stop criteria for

clustering when building the tree.
CTA
Enables or disables the clock tree

analyzer.
explore clock tree
Set to turn on clock tree synthesis

search for the optimal buffer and target
load to be used by a search of the
solution space.
fix ignore pins violations
Enables or disables DRC fixing beyond

an implicit ignore pin on data-mixing
clock gate.
leaf net transition constraint
Uses the tightest clock transition of the

leaf net.
length fixed buffer insertion on top
Set to run the top-mode clock tree

synthesis.
logic level balance
Set to use logic level balance for clock

tree synthesis.
number of hookup pins per cluster
Sets the maximum number of hookup

pins per cluster.
real clock useful skew
Enables useful clock skew for clock tree

synthesis.
skew type
Sets the skew type.
update congestion map
Set to force clock tree synthesis to

update the placement-based
congestion map at various points while
it runs.

D-46
Table D-12 List of Other Clock Tree Synthesis Parameters

Parameter
Description
use global route
Set to use global route for clock tree

synthesis.
wire capacitance accuracy
Toggles to and from less accurate

capacitance estimation.
clock tree root minimum fanout

The clock tree root minimum fanout parameter is used as
one of the stop criteria for clustering when building the tree. No
further buffer levels are added to the tree if number of fanouts at the
current level is already smaller than this minimum fanout.
Usage.
axSetIntParam "acts" "clock tree root minimum fanout" 1
Range.
CTA
The CTA parameter enables or disables the clock tree analyzer.
Clock tree synthesis buffer selection and clustering is driven by
target capacitance and target transition parameters. If the CTA
parameter is set to 1, the user-supplied targets for skew and
insertion delay will be converted to target transition and target
capacitance values that meet the skew and insertion delay targets
with the best overall QoR of the tree.

D-47
If the CTA parameter is turned off, the user-supplied or default

settings for target capacitance and target transition will be used.
Usage.
To enable the clock tree analyzer, enter the following:
axSetIntParam "acts" "CTA" 1
Range.
explore clock tree

The explore clock tree parameter turns on (or off) clock tree
synthesis search for the optimal buffer and target load to be used by
a search of the solution space. For each buffer available as a clock
buffer according to dialog box settings and astSetClockCell, you
can explore eight different target capacitance values between a
minimum of two x input capacitance of the buffer and a maximum
defined by max_capacitance for the buffer. The default is disabled
because of runtimes.
Usage.
To turn on clock tree synthesis search for the optimal buffer and
target load, enter the following:
axSetIntParam "acts" "explore clock tree" 1
Range.
D-48
fix ignore pins violations

The fix ignore pins violations parameter enables or
disables DRC fixing beyond an implicit ignore pin on data-mixing
clock gate.
If some deep combinational logic is hooked up to the clock tree (for
example, in clock data mixing), and clock tree synthesis cannot trace
to the next sync/ignore/stop pin, it will identify an implicit ignore pin
automatically. This allows clock tree synthesis to proceed. However,
other optimizations will consider all cells and nets in the transitive
fanout of the implicit ignore pin as clocks and will not touch them. If
the fix ignore pins violations parameter is set to 1, clock
tree synthesis will do a DRC fix for these nets and cells.
Usage.
To enable DRC fixing beyond an implicit ignore pin on data mixing
clock gate, enter the following:
axSetIntParam "acts" "fix ignore pins violations" 1
Range.
leaf net transition constraint

The leaf net transition constraint parameter uses the
tightest clock transition of the leaf net.
Usage.
To use the tightest clock transition of the leaf net, enter the following:

D-49
axSetIntParam "acts" "leaf net transition constraint" 1
Range.
length fixed buffer insertion on top

The length fixed buffer insertion on top parameter is
set to run the top mode clock tree synthesis as it runs in version
2004.06 and earlier.
Usage.
To run the top mode clock tree synthesis, enter the following:
axSetIntParam "acts" "length fixed buffer insertion on top" 1
Range.
logic level balance

The logic level balance parameter is set to use logic level
balance for clock tree synthesis.
Usage.
To use logic level balance for clock tree synthesis, enter the
following:
axSetIntParam "acts" "logic level balance" 1

D-50
Range.
number of hookup pins per cluster

The number of hookup pins per cluster parameter sets the
maximum number of hookup pins per cluster.
Usage.
To set the maximum number of hookup pins per cluster as 32, enter
the following:
axSetIntParam "acts" "number of hookup pins per cluster" 32
Range.
real clock useful skew

The real clock useful skew parameter enables or disables
useful clock skew for clock tree synthesis. In the case of useful skew,
it is actually executed only if both this switch and the skew type
switch are set for useful skew. The Clock Tree Synthesis dialog box
sets both switches if useful skew is selected.
Usage.
To enable useful clock skew for clock tree synthesis, enter the
following:
axSetIntParam "acts" "real clock useful skew" 1

D-51
skew type
The skew type parameter used to set the skew type. It is equivalent
to the skew type selection in the Clock Tree Synthesis dialog box.
Usage.
To set the skew type as global, enter the following:
axSetIntParam "acts" "skew type" 0
Range.
default is 0.
Table D-13 lists the valid values of the skew type parameter and their
description.
Table D-13 Valid Values of the skew type Parameter
Value
Description
Global
Local
Useful
update congestion map

The update congestion map parameter, when set to 1, forces
clock tree synthesis to update the placement-based congestion map
at various points while it runs. This decreases capacitance
estimation error induced by congestion map and layout getting out of
D-52
sync by added clock tree synthesis buffers. It increases the chance

of convergence issues and causes longer runtime, especially for
clock tree optimization.
If switched on, the congestion map is updated after initial clock tree
synthesis and after embedded clock tree optimization. However, if
the debug mode parameter is on, the congestion map will always be
updated at the end of clock tree synthesis.
Usage.
To force clock tree synthesis to update the placement-based
congestion map at various points, enter the following:
axSetIntParam "acts" "update congestion map" 1
Range.
use global route

The use global route parameter is set to use global route for
Usage.
To use global route for clock tree synthesis, enter the following:
axSetIntParam "acts" "use global route" 1
Range.
D-53
wire capacitance accuracy

The wire capacitance accuracy parameter determines the
accuracy of capacitance estimation. For medium and high effort,
there is no difference and clock tree synthesis calls the Astro
extraction engine to perform net capacitance estimation from a
virtual route. For low effort, a crude estimation based on Steiner
weights and bounding box of net fanout is used.
Usage.
To control the accuracy of capacitance estimation, use the following
syntax:
axSetIntParam "acts" "wire capacitance accuracy" 2
Range.
default is 2.
Table D-14 lists the valid values of the wire capacitance
accuracy parameter and their description.
Table D-14 Valid Values of the wire capacitance accuracy Parameter
Value
Description
Low
Medium
High

D-54
Changing Standard Naming Convention Parameters

Table D-17 lists the standard naming convention parameters
Table D-15 List of Standard Naming Convention Parameters
Parameter
Description
bottom level buffer
Determines the cell master used to build the

lowest level buffers.
buffer instance prefix name
Sets a prefix for naming the clock buffers

inserted by clock tree synthesis.
configuration output file
If the configuration output file

parameter is set to specify a file name, clock
tree synthesis will dump a hard configuration
file specifying the tree it created.
file name: buffer instances
Sets the output file name for additional buffers

and inverters that are created to build the clock
tree during clock tree synthesis.
file name: clock tree timing
Sets the output file name of the detailed timing

report of the tree created after clock tree
synthesis.
file name: cluster
When this parameter is set, clock tree

synthesis will dump a file with the coordinates
of the bounding boxes of the clusters it used in
its internal clustering.
file name: FF relationship
If this parameter is set to specify a file name,

clock tree synthesis will dump a file with the
data dependency graph outlining which FFs
are related via a datapath for local skew.
file name: re-synthesis nets
Used to specify a file with a list of root clock

nets for which clock tree synthesis should be
performed even if the clock tree had already
been synthesized earlier.

D-55
Table D-15 List of Standard Naming Convention Parameters

Parameter
Description
file name: synthesized clock tree
By default, clock tree synthesis dumps the

structure of the tree it created to a file called
tree.acts after clock tree synthesis is
completed. Using the file name:
synthesized clock tree parameter, the file
name can be changed.
file name: synthesized nets
During clock tree synthesis, additional nets are

created to build the clock tree. After these nets
are created, all these nets are dumped into a
file. By default the file is called net.acts.
Using the file name: synthesized nets
parameter, this file name can be changed.
net prefix name
Sets a prefix for naming the clock nets added

by clock tree synthesis.
bottom level buffer

The bottom level buffer parameter is set to the name of a cell
master such that the lowest level buffers in the tree are built only by
using this cell master.
Usage.
axSetStringParam "acts" "bottom level buffer" ""
buffer instance prefix name

The buffer instance prefix name parameter sets a prefix for
naming the clock buffers inserted by clock tree synthesis.
By default clock tree synthesis uses local_name = cell master
name*gatelevel*bufferlevel*index as the name for newly
added instances. If this variable is set to a value prefix, the new
instances will be called prefix*local_name.
D-56
This parameter is deprecated. Use the Scheme variable

actBufferNameFormat instead.
Usage.
axSetStringParam "acts" "buffer instance prefix name" ""
configuration output file

If the configuration output file parameter is set to specify
a file name, clock tree synthesis will dump a hard configuration file
specifying the tree it created. This file can be used to recreate exactly
the same tree in incremental runs.
actFileNameConfigurationOutput instead.
Usage.
axSetStringParam "acts" "configuration output file" ""
file name: buffer instances

The file name: buffer instances parameter sets the output
file name for additional buffers and inverters that are created to build
the clock tree during clock tree synthesis. When a clock tree is
created, it dumps a file with all these instances. By default, the file is
called buffer.acts.
This feature might be particularly useful if executing several clock
tree synthesis runs to avoid having files from different runs overwrite
each other.
actFileNameBufferInstances instead.

D-57
Usage.
axSetStringParam "acts" "file name: buffer instances"
"buffer.acts"
file name: clock tree timing

The file name: clock tree timing parameter sets the output
file name of the detailed timing report of the tree created after clock
tree synthesis. By default, the detailed timing report of the tree
created after clock tree synthesis is dumped to a file called
timing.acts. This report is identical to the report you get from
astDumpClockTiming. Using the file name: clock tree
timing parameter, the file name can be changed.
each other.
actFileNameClockTreeTiming instead.
Usage.
axSetStringParam "acts" "file name: clock tree timing"
"timing.acts"
file name: cluster

If the file name: cluster parameter is set to specify a file name,
clock tree synthesis will dump a file with the coordinates of the
bounding boxes of the clusters it used in its internal clustering. This
feature might be particularly useful if executing several clock tree
synthesis runs to avoid having files from different runs overwrite
each other.

D-58

actFileNameCluster instead.
Usage.
axSetStringParam "acts" "file name: cluster" ""
file name: FF relationship

If this parameter is set to specify a file name, clock tree synthesis will
dump a file with the data dependency graph outlining which FFs are
related via a datapath for local skew.
This parameter is deprecated, use the Scheme variable
actFileNameFFRelationship instead.
Usage.
axSetStringParam "acts" "file name: FF relationship" ""
file name: re-synthesis nets

The file name: re-synthesis nets parameter can be used
to specify a file with a list of root clock nets for which clock tree
synthesis should be performed even if the clock tree had already
been synthesized earlier.
actFileNameResynthesisNets instead.
Usage.
axSetStringParam "acts" "file name: re-synthesis nets" ""

D-59
file name: synthesized clock tree

The file name: synthesized clock tree parameter sets the
output file name of clock tree structure created by clock tree
synthesis. By default, clock tree synthesis dumps the structure of the
tree it created to a file called tree.acts after clock tree synthesis
is completed. Using the file name: synthesized clock tree
parameter, the file name can be changed.
each other.
actFileNameSynthesizedClockTree instead.
Usage.
axSetStringParam "acts" "file name: synthesized clock tree"
"tree.acts"
file name: synthesized nets

During clock tree synthesis, additional nets are created to build the
clock tree. After these nets are created, all these nets are dumped
into a file. By default the file is called net.acts. Using the file
name: synthesized nets parameter, this file name can be
changed.
tree synthesis runs and to avoid having files from different runs
overwrite each other.
actFileNameSynthesizedNets instead.

D-60
Usage.
axSetStringParam "acts" "file name: synthesized nets"
"net.acts"
net prefix name

The net prefix name parameter sets a prefix for naming the clock
nets added by clock tree synthesis.
By default, clock tree synthesis uses
local_name=gatelevel*bufferlevel*index as the name for
newly added clock nets. If this variable is set to a value prefix, the
new instances will be called prefix*local_name.
If the root clock net has the form of a bus, local_name will be bus
base name=gatelevel*bufferlevel*index[busindex].
actNetNameFormat instead.
Usage.
axSetStringParam "acts" "net prefix name" ""
Changing Default Interpretation of Clock Constraints

Parameters
Table D-16 lists the Astro Clock Constraints parameters.
Table D-16 List of Clock Constraint Parameters
Parameter
Description
ignore library constraints
Using this parameter, the DRC

constraints coming from the library can
be switched off.

D-61
Table D-16 List of Clock Constraint Parameters

Parameter
Description
ignore library maximum capacitance
Ignores the maximum capacitance set

in a library.
ignore library maximum fanout
Ignores the maximum fanout set in a

library.
ignore library maximum transition
Ignore the maximum transition set in a

library.
ignore SDC
Ignores the constraint setting in the

SDC file.
ignore SDC maximum capacitance
Ignores maximum capacitance set in

the SDC file.
ignore SDC maximum fanout
Ignores the maximum fanout set in the

SDC file.
ignore SDC maximum transition
Ignores the maximum transition set in

the SDC file.
ignore set_clock_latency
Ignores the clock latency set in the SDC

file.
ignore set_clock_transition

file.
ignore set_clock_uncertainty

file.
ignore library constraints

By default, clock tree synthesis will respect any maximum transition,
capacitance, and fanout constraint set in the library. In some cases,
this might not be desired for clock tree synthesis. Using the ignore
library constraints parameter, the DRC constraints coming
from the library can be turned off.

D-62
Usage.
To turn off DRC constraints coming from the library, enter the
following:
axSetIntParam "acts" "ignore library constraints" 1
Range.
ignore library maximum capacitance

The ignore library maximum capacitance parameter is set
to ignore the maximum capacitance set in a library.
Usage.
To ignore the maximum capacitance set in a library, enter the
following:
axSetIntParam "acts" "ignore library maximum capacitance" 1
Range.
ignore library maximum fanout

The ignore library maximum fanout parameter is set to
ignore the maximum fanout set in a library.

D-63
Usage.
To ignore the maximum fanout set in a library, enter the following:
axSetIntParam "acts" "ignore library maximum fanout" 1
Range.
ignore library maximum transition

The ignore library maximum transition parameter is used
to ignore the maximum transition set in a library.
Usage.
To ignore the maximum transition set in a library, enter the following:
axSetIntParam "acts" "ignore library maximum transition" 1
Range.
ignore SDC
The ignore SDC parameter is set to ignore the constraint setting in
the SDC file (DRC set_max_xxx and target values
set_clock_xxx).
Usage.
To ignore constraint setting in the SDC file, enter the following:
D-64
axSetIntParam "acts" "ignore SDC" 1
Range.
ignore SDC maximum capacitance

The ignore SDC maximum capacitance parameter is set to
ignore maximum capacitance set in the SDC file.
Usage.
To ignore maximum capacitance set in the SDC file, enter the
following:
axSetIntParam "acts" "ignore SDC maximum capacitance" 1
Range.
ignore SDC maximum fanout

The ignore SDC maximum fanout parameter is set to ignore
maximum fanout set in the SDC file.
Usage.
To ignore maximum fanout set in the SDC file, enter the following:
axSetIntParam "acts" "ignore SDC maximum fanout" 1

D-65
Range.
ignore SDC maximum transition

The ignore SDC maximum transition parameter is set to
ignore the maximum transition set in the SDC file.
Usage.
To ignore the maximum transition set in the SDC file, enter the
following:
axSetIntParam "acts" "ignore SDC maximum transition" 1
Range.
ignore set_clock_latency
When set to 1, the ignore set_clock_latency parameter
causes the clock latency set in the SDC file to be ignored. Clock tree
synthesis can use set_clock_latency to specify an insertion
delay target for clock tree synthesis. If the ignore
set_clock_latency parameter is set to 1, this target will not be
applied and the insertion delay will be minimized or the target
specified in the dialog box will be used.
This feature is useful to achieve delay balancing and to avoid pre- to
post-clock tree synthesis differences in IO timing. If both the dialog
box and SDC target are given and this parameter is set to 0, the SDC
setting will override the dialog box.

D-66
Usage.
To ignore the clock latency set in the SDC file, enter the following:
axSetIntParam "acts" "ignore set_clock_latency" 1
Range.
ignore set_clock_transition
When set to 1, the ignore set_clock_transition parameter
causes the clock transition set in the SDC file to be ignored. Clock
tree synthesis can use set_clock_transition to specify a
target for the clock net transition times clock tree synthesis needs to
achieve at the sink pins.
If the ignore set_clock_transition parameter is set to 1, the
target will not be applied and transition times are built according to
the cell library and global limits. In other words, the transition times
at the clock buffers in the tree will adhere only to the rule: max
transition value and stay close to the target: max
transition value.
Even if the parameter is set to 1, the set_clock_transition
value will be considered only at the clock sink pins.
Usage.
To ignore the clock transition set in the SDC file, enter the following:
axSetIntParam "acts" "ignore set_clock_transition" 1

D-67
Range.
ignore set_clock_uncertainty
When set to 1, the ignore set_clock_uncertainty parameter
causes the clock uncertainty set in the SDC file to be ignored. Clock
tree synthesis can use set_clock_uncertainty to specify a
skew target for clock tree synthesis. If the ignore
set_clock_uncertainity parameter is set to 1, the target will
not be applied and the skew will be minimized. If using the
set_clock_uncertainty from SDC is turned on, the SDC
constraint and the dialog box setting are compared, and the tighter
constraint is applied. Therefore, to ensure that the SDC value is
used, set the dialog box to a large dummy value.
Usage.
To ignore clock uncertainty set in the SDC file, enter the following:
axSetIntParam "acts" "ignore set_clock_uncertainty" 1
Range.

D-68

Table D-17 lists the Astro common graph parameters.
Table D-17 List of Common Graph Parameters
Parameter
Description
CGHIER_ENABLE_FAST_REPAIR
Determines whether to skip the

hierarchy net uniqueness check and
hierarchy cell unification during
cg_opt_context_flag
Controls connection class constraint

and IBT (Instance Based Target)
library usage in optimization.
disable_escape_char
Determines whether the enable/

disable escape character is added to
the local name of a hierarchy net.
dont_touch_nets_connecting_ls_and_io
Controls the marking of

level_shifter/isolation_cell
connected flat nets as dont_touch.
dont_use_means_dont_touch
Determines whether to size cell

instances whose masters are
marked as dont_use to other usable
cells.
enable_ibt
Controls IBT usage in Astro.
enable_connection_class
Controls connection class constraint

usage in Astro.
max_boolean_syntax_warnings
Sets a threshold number of warnings

before a summary warning message
is issued.
optimize_mix_signal_net
Turned on when optimization needs

to take care of the mixed-signal
paths.

D-69
Table D-17 List of Common Graph Parameters

Parameter
Description
replace_backslash
Determines whether to replace a

backslash (\) with an underscore (_)
during postroute optimization.
save_cell
Determines whether to save cells.
CGHIER_ENABLE_FAST_REPAIR
The CGHIER_ENABLE_FAST_REPAIR parameter is set to skip the
hierarchy net uniqueness check and hierarchy cell unification during
Usage
axSetIntParam "cg" "CGHIER_ENABLE_FAST_REPAIR" 0
Range
cg_opt_context_flag
The cg_opt_context_flag parameter controls connection class
constraint and IBT (Instance Based Target) library usage in
optimization.
Usage
To turn on the connection class constraint in optimization, enter the
following:
axSetIntParam "cg" "cg_opt_context_flag" 1

D-70
Range
default is 0.
Table D-18 lists the valid values of this parameter and their
description.
Table D-18 Valid Values of the cg_opt_context_flag Parameter
Value
Description
Turn off the connection class constraint and IBT
Turn on the connection class constraint
Turn on IBT
Turn on both the connection class constraint and IBT
disable_escape_char
The disable_escape_char parameter determines whether the
enable/disable escape character will be added to the local name of
a hierarchy net. When set to 1, the escape character is added. The
escape character is \ by default.
Usage
axSetIntParam "cg" "disable_escape_char" 0
Range
The valid values are 0 and 1. The default is 0.

D-71
dont_touch_nets_connecting_ls_and_io
The dont_touch_nets_connecting_ls_and_io parameter
controls the marking of level_shifter/isolation_cell
connected flat nets as dont_touch.
Usage
To mark level_shifter/isolation_cell connected flat nets
as dont_touch, enter the following:
axSetIntParam "cg" "dont_touch_nets_connecting_ls_and_io" 1
Range
dont_use_means_dont_touch
When the dont_use_means_dont_touch parameter is set to 0,
the cell instances whose masters are marked as dont_use are
sized to other usable cells.
Usage
axSetIntParam "cg" "dont_use_means_dont_touch" 1
Range
enable_ibt
The enable_ibt parameter controls IBT usage in Astro.

D-72
Usage
To turn on IBT usage, enter the following:
axSetIntParam "cg" "enable_ibt" 1
When set to 0, IBT usage is turned off. Setting this parameter to 1

has the same effect as setting the cg_opt_context_flag to 2.
Range
enable_connection_class
The enable_connection_class parameter controls connection
class constraint usage in Astro.
Usage
To turn on connection class constraint usage, enter the following:
axSetIntParam "cg" "enable_connection_class" 1
When this parameter is set to 1, the effect is the same as setting

cg_opt_context_flag to 1.
Range

D-73
max_boolean_syntax_warnings
The max_boolean_syntax_warnings parameter causes a
warning message to be printed if the number of warnings is greater
than the specified value. The following warning message appears as
a result of setting this parameter:
"CG: warn_number Invalid syntax warnings."
Usage
axSetIntParam "cg" "max_boolean_syntax_warnings" 5
Range
The default is 5.
optimize_mix_signal_net
The optimize_mix_signal_net parameter is turned on to
consider mixed-signal paths during optimization.
Usage
To consider mixed-signal paths during optimization, enter the
following:
axSetIntParam "cg" "optimize_mix_signal_net" 1
Range

D-74
replace_backslash
The replace_backslash parameter determines whether to
replace a backslash (\) with an underscore (_) in bus net names
during postroute optimization. This is done for compatibility with
PrimeTime.
Usage
To replace a backslash (\) with an underscore (_) during postroute
optimization, enter the following:
axSetIntParam "cg" "replace_backslash" 1
Range
save_cell
The save_cell parameter determines whether to save cells.
Usage
To save cells, enter the following:
axSetIntParam "cg" "save_cell" 1
When set to 0, common graph does not save any cell.
Range

D-75
Table D-19 lists the Astro crosstalk parameters.
Table D-19 List of Crosstalk Parameters
Parameter
Description
xtDeltaDelayScale
Controls delta delay scaling.
xtDeltaTransScale
Controls delta transition time scaling.
xtEnableRailToRailDeltaDelay
Multiplies delta delay by 1/

(upper_slew_threshold lower_slew_threshold).
xtNoAdaptiveInMediumEffort
Lets crosstalk analysis run faster in the

medium-effort mode.
xtNumOfTopAggr
Controls the number of effective aggressors

to be included in crosstalk analysis.
xtTimingWindowHighEffort
Invokes crosstalk-induced delay analysis

with better timing correlation, which
requires more runtime.
xtUseAdaptiveDetailWvfmThresh
Improves the transition time correlation with

PrimeTime SI.
xtUseNoiseWidth
Controls whether noise width is used in the

noise prune.
xtXtalkDetailWvfmThreshold
Controls the switching noise bump height

threshold above which a net qualifies for
detailed waveform-based crosstalk
analysis.

D-76
xtDeltaDelayScale
The xtDeltaDelayScale parameter is used to control delta delay
scaling. It works only in the low-effort mode during crosstalk-induced
delay calculation. In the low-effort mode, the scaling factor is 1.0 by
default, which means no adjustment on delta delay. In the
medium-effort mode, the delta delay is calculated more accurately
and this parameter setting is not required.
You can set the scaling factor between 0.0 and 1.0 for better
correlation with PrimeTime SI.
Usage
To control delta delay scaling, use the following syntax:
axSetRealParam "xt" "xtDeltaDelayScale" float
Range
The valid values are 0.0 to 1.0. The default is 1.0.
xtDeltaTransScale
The xtDeltaTransScale parameter controls the delta transition
time scaling. It works only in the low-effort mode during
crosstalk-induced delay calculation. In the low-effort mode, the
scaling factor is zero by default, which indicates no delta transition
time. In the medium-effort mode, the delta transition is calculated
more accurately and this parameter setting is not required.
Beginning with version W-2004.12-SP5, you can set the scaling
factor between 0.0 and 1000.0 for better correlation with PrimeTime
SI.
D-77
Usage
To control the delta transition time scaling, use the following syntax:
axSetRealParam "xt" "xtDeltaTransScale" float
Range
The default is 0.0.
xtEnableRailToRailDeltaDelay
The xtEnableRailToRailDeltaDelay parameter multiplies
delta delay by 1/(upper_slew_threshold lower_slew_threshold).
This option is turned off by default. When the designs slew
thresholds are really close (such as, 40%-60%) and PrimeTime SI is
more pessimistic than Astro, setting this parameter to 1 improves
correlation.
Usage
axSetIntParam "xt" "xtEnableRailToRailDeltaDelay" 0
Range

D-78
xtNoAdaptiveInMediumEffort
The xtNoAdaptiveInMediumEffort parameter lets crosstalk
analysis run faster in the medium-effort mode and provides equally
accurate results. This is achieved by choosing the right model
adaptively.
Usage
To use the most sophisticated model, enter the following:
axSetIntParam "xt" "xtNoAdaptiveInMediumEffort" 0
When set to 1, crosstalk analysis switches back to the old

medium-effort behavior (as in version 2004.12 and older versions).
Range
xtNumOfTopAggr
The xtNumOfTopAggr parameter controls the number of effective
aggressors to be included in crosstalk noise analysis or induced
delay analysis.
Usage
To specify that all effective aggressors are to be included in the
crosstalk noise or induced delay analysis, enter the following:
axSetIntParam "xt" "xtNumOfTopAggr" 0
D-79
When set to a non-zero value, n, only the top n effective aggressors

are included.
Range
The valid values of this parameter range between 0 and
2147483647. The default is 0.
xtTimingWindowHighEffort
The xtTimingWindowHighEffort parameter is used to perform
crosstalk-induced delay analysis with better timing window
correlation. This requires more runtime. This parameter is effective
only when timing window is turned on during crosstalk analysis.
Usage
To perform crosstalk-induced delay analysis with better timing
window correlation, enter the following:
axSetIntParam "xt" "xtTimingWindowHighEffort" 1
Range
When set to 1, the
tool performs two iterations of timing propagation with crosstalk

effect.
infinite timing window is used during first iteration.

D-80
xtUseAdaptiveDetailWvfmThresh
The xtUseAdaptiveDetailWvfmThresh parameter is used to
improve transition time correlation with PrimeTime SI. It is effective
in both low and medium effort crosstalk models.
Usage
To improve transition time correlation with PrimeTime SI, enter the
following:
axSetIntParam "xt" "xtUseAdaptiveDetailWvfmThresh"
Low effort: The potentially optimistic delta transition of low effort is a

known problem of Astro-Xtalk. Optimistic estimates tend to occur
more often in maximum corner calculations when the switching noise
bumps are large, for example, 0.35.
When the xtUseAdaptiveDetailWvfmThresh parameter is set
to 1, Astro-Xtalk calculates the delta transition based on waveforms,
on qualified nets. A net is qualified for the new calculation when the
switching noise bump height is greater than the absolute difference
of the transition upper threshold and the delay threshold. This
variable is effective only in maximum corner calculations.
With this parameter set to 1, it is guaranteed that the delta transition
is more pessimistic than the default mode. For low effort, the variable
is effective to treat optimism of delta transitions for maximum corner
only and there is no noticeable performance penalty.
Medium effort: The xtUseAdaptiveDetailWvfmThresh
parameter is used to provide better correlation with PrimeTime SI on
both delta delay and delta transition. In medium effort, qualification
of a net for detailed waveform calculation is based on the absolute
D-81
difference between upper transition threshold and the delay

threshold for maximum corner, and the difference between lower
transition threshold and the delay threshold for minimum corner.
When the switching noise bump height is larger than the difference,
the delta delay and delta slew are calculated based on the detailed
waveform. Enabling the xtUseAdaptiveDetailWvfmThresh
parameter might slow down the medium effort by 20% depending on
the library thresholds. When this parameter is turned off, the detailed
waveform calculation is activated only when the switching bump
height is larger than 0.35. However, there is a way to change this
default value (see xtXtalkDetailWvfmThreshold).
For medium effort, the variable is effective for both delta delay and
delta transition in both minimum and maximum corners and it has
some runtime penalty.
Range
xtUseNoiseWidth
The xtUseNoiseWidth parameter controls whether noise width is
used during noise prune. It works only in the low-effort mode. In low
effort, the noise width is not calculated by default. In medium effort,
the noise width is always calculated and used for pruning when
information is available.
Usage
To specify that the noise width is to be estimated and checked
against the internal estimated noise width constraints for pruning,
D-82
axSetIntParam "xt" "xtUseNoiseWidth" 1
When set to 0, noise width is not used in the noise pruning operation.
Range
xtXtalkDetailWvfmThreshold
The xtXtalkDetailWvfmThreshold parameter controls the
switching noise bump height threshold above which a net qualifies
for detailed waveform-based crosstalk analysis. This parameter is
effective only in the medium-effort mode.
Usage
To change the default value of switching noise bump height, use the
following syntax:
axSetRealParam "xt" "xtXtalkDetailWvfmThreshold" 0.35
With this setting, all the nets with switching noise bump height
greater than 0.35 are analyzed with detailed waveform based
crosstalk analysis.
If xtUseAdaptiveDetailWvfmThresh is set to 1, the algorithm is
activated when the switching noise bump height is greater than
minimum (the slew and trip point difference,
xtXtalkDetailWvfmThreshold).
Range
The valid values are 0.000 to 1.000. The default is 0.35.
D-83

Table D-20 lists the Astro global route parameters.
Table D-20 List of Global Route Parameters
Parameter
Description
accessPolyPin
Specifies whether poly pins can be used

during global routing for connections.
avoidCouplingUser
Enables the global router to space nets

during routing.
avoidXtalk
Turns on or off crosstalk prevention during

global routing.
blncdToSkewCntrlRatio
Sets a threshold for skew control mode,

based on net aspect ratio.
blockEdgeAccess
Enables the global router to access pins on

edges of hard macros.
brokenNetsThresholdPercent
Specifies whether incremental global

routing should be performed.
clockBalanced
Turns on or off balanced routing over clock

nets.
clockComb
Enables the global router to connect ports

directly to the prerouted clock trunks to
minimize clock skew.
combDistance
Sets a distance threshold for clock routing

to connect clock pins directly to clock nets.
combMaxConnections
Controls the number of direct connections

allowed to the clock pins from the same
clock trunk.
compactMode
Determines the size of gcell used for global

routing.

D-84

Parameter
Description
congestionWeight
Controls the effort to balance routing

congestion relative to wire length.
densityDriven
Turns on or off density-driven global

routing.
detourLimitMinNetLen
Controls the way the global router

implements maxDetourPercent on nets.
extraCostsApplyPercent
Applies the wireCost and viaCost

settings on the top n percent of nets in the
design.
extraWireLengthOpt
Tells the global router to run an additional

rerouting phase to reduce wire length on
nets that have no congestion.
forceUpperLayersForCritNets
Specifies the mode for upper layers usage.
horReserveTracks
Determines the number of horizontal free

tracks reserved in each gcell.
ignoreViaBlockage
Specifies whether to honor a via blockage.
incremental
Controls whether the global router runs

incrementally.
macroBndryDir
Controls the use of macroBndryTrkUtil

differently for layers in different directions.
macroBndryExt
Defines the area in which the global router

obeys macroCornerTrkUtil and
macroBndryTrkUtil.
macroBndryTrkUtil
Sets the percentage of tracks available in

the gcells near a macro boundary.
macroBndryWidth
Defines the distance from the corners of the

macros.
macroCornerTrkUtil
Sets the percentage of tracks available in

the gcells near a macro corner.

D-85

Parameter
Description
mapOnly
Specifies whether the router generates a

congestion map based on global routing
without creating the global wires.
maxDetourPercent
Directs the global router to have no more

than the specified percentage of detours on
any net.
netCriticality
Determines the order in which the global

router routes the nets during initial route.
noTopLevelBusFeedThroughs
Specifies whether to allow feedthroughs on

bus signals.
paEqPinNetMaxPort
Creates equivalent pins for nets with no

more than n ports.
powerDriven
Turns on or off power-driven global routing.
rcOptByLength
Controls the choice of layers for the global

router to reduce RC.
reportDemandOnly
Specifies whether to report demand only.
reportEffectiveOverflow
Specifies whether to generate an effective

overflow report.
reportGCellDensity
Specifies whether to report gcell density for

each layer.
reportNetOrdering
Specifies the number of nets to report,

according to the routing order.
reserveTracksForPowerFile
Defines the percentage of routing tracks on

each layer reserved for power routing.
skewControl
Turns on or off skew control during global

routing.
skewControlNetBBLowBound
Determines the nets considered for skew

control during global routing.

D-86

Parameter
Description
skewControlWeight
Determines the importance given to skew

control on the net during global routing.
speed
Specifies the effort at which the global

router should run.
timingDriven
Turns on or off timing-driven global routing.
timingWeight
Sets the weight given to timing relative to

wire length during global routing.
turboMode
Improves run time.
VABoundaryToLSWeight
Specifies the value to adjust the cost for

level shifter connection when switching
from one voltage area to another.
verReserveTracks
Determines the number of vertical free

tracks reserved in each gcell.
xtalkWeight
Defines the weight given to crosstalk

prevention during global routing.
accessPolyPin
The accessPolyPin parameter specifies whether poly pins can be
used during global routing for connections. If the value is set to 1, the
router can route to poly pins. If the value is set to 0, the router cannot
use poly pins. This parameter has no effect if the current design does
not contain poly pins, as is the case in most designs.
Usage
To access poly pins, enter the following:
axSetIntParam "groute" "accessPolyPin" 1

D-87
When set to 0, the poly pins cannot be accessed.
Range
Note:
This is the only global route parameter that is saved into the
Milkyway CEL view. It is persistent across different sessions.
avoidCouplingUser
The avoidCouplingUser parameter enables the global router to
space nets during routing. The nets to be considered need to be set
with the Set Net Constraints command. If this parameter is set to 1,
timing spacing will be honored.
Usage
To turn on coupling avoidance on user selected nets, enter the
following:
axSetIntParam "groute" "avoidCouplingUser" 1
When set to 0, coupling avoidance is turned off on user selected

nets.
Range

D-88
avoidXtalk
The avoidXtalk parameter turns on/disables crosstalk prevention
during global routing. If this parameter is set to 1, the global router
tries to avoid assigning nets with coupling to the same gcell.
Usage
To turn on the crosstalk avoidance, enter the following:
axSetIntParam "groute" "avoidXtalk" 1
When set to 0, crosstalk avoidance is turned off.
Range
blncdToSkewCntrlRatio
The blncdToSkewCntrlRatio parameter sets a threshold for
turning on the balanced skew control mode. For nets with an aspect
ratio smaller than the parameter value, balanced skew control mode
is enabled. The aspect ratio is calculated based on the bounding box
formed by enclosing the pins.
Usage
To set the aspect-ratio threshold for balanced mode skew control,
axSetIntParam "groute" "blncdToSkewCntrlRatio" 3

D-89
Range
default is 3.
blockEdgeAccess
The blockEdgeAccess parameter allows the global router to
access pins on edges of hard macros. By default, the global router
reaches pins on edges of hard macros. When the parameter is set to
1, it allows the global router is allowed to access or drop vias on
whole macro pins without edges limitation.
Usage
To turn on only macro block edge access, enter the following:
axSetIntParam "groute" "blockEdgeAccess" 1
When set to 0, macro block edge access is turned off.
Range
brokenNetsThresholdPercent
The brokenNetsThresholdPercent parameter specifies a
threshold for incremental global routing to be performed. This is
effective when incremental is set to 1.

D-90
Usage
To specify the maximum broken nets for incremental global route,
enter the following syntax:
axSetIntParam "groute" "brokenNetsThresholdPercent" -1
Range
The valid values of this parameter range between -1 and 100. The
default is -1.
clockBalanced
The clockBalanced parameter turns balanced routing on clock
nets on and off.
Usage
To turn on balanced routing for clock tree synthesized nets, enter the
following:
axSetIntParam "groute" "clockBalanced" 1
When set to 0, balanced routing is turned off for clock tree

synthesized nets.
Range

D-91
clockComb
The clockComb parameter enables the global router to connect
ports directly to the prerouted clock trunks to minimize clock skew.
Be aware that this requires greater routing resources, if the clock
pins are not close to the clock trunks.
The Comb mode works on designs with pre-existing clock nets.
Usage
To turn on comb routing for clock nets with mesh or trunk, enter the
following:
axSetIntParam "groute" "clockComb" 1
When set to 0, comb routing for clock nets with mesh or trunk is
turned off.
Range
combDistance
The combDistance parameter sets a distance threshold, in gcell
units, for clock routing to connect clock pins directly to clock nets.
Usage
To set the threshold for connecting clock pins directly to clock nets,
axSetIntParam "groute" "combDistance" 2

D-92
Range
default is 2.
combMaxConnections
The combMaxConnections parameter limits the number of direct
connections allowed to the clock pins from the same clock trunk. The
default value of -1 allows a clock net to be connected to any number
of clock pins.
Usage
To specify the maximum number of pin connections to any clock
strap, use the following syntax:
axSetIntParam "groute" "combMaxConnections" -1
Range
default is -1.
compactMode
The compactMode parameter determines the size of gcell used for
global routing. If it is set to 0, gcells of 1 cellrow height will be created.
If it is set to 1, the global router automatically adjusts the global route
cell size.
Increasing the size of gcell will complete the global routing faster at
the cost of quality as routing becomes coarser.

D-93
Usage
To specify the mode to adjust GRC size, enter the following:
axSetIntParam "groute" "compactMode" 1
Range
default is 1.
congestionWeight
The congestionWeight parameter specifies the relative
importance of routing congestion versus wire length. As the
parameter value increases, the router tries harder to avoid routing
congestion at the cost of increased wire length.
Usage
To balance routing congestion relative to the wire length, use the
following syntax:
axSetIntParam "groute" "congestionWeight" 4
Range
default is 4.

D-94
densityDriven
The densityDriven parameter turns density-driven global routing
on or off. In the default mode, the router decides the weight given to
density relative to wire length during global routing. If timing driven
or crosstalk is turned on, global route turns on the densityDriven
automatically.
Usage
To turn on the density-driven mode, enter the following:
axSetIntParam "groute" "densityDriven" 1
Range
default is -1.
Table D-21 lists the valid values of this parameter and their effect.
Table D-21 Valid Values of the densityDriven Parameter
Value
Description
-1
Program decides whether density-driven mode should be used
Turn off the density-driven mode
Turn on the density-driven mode
Turn on high effort density-driven mode

D-95
detourLimitMinNetLen
The detourLimitMinNetLen parameter controls the way the
global router implements maxDetourPercent on nets. If the value
is set to 0, the router forces maxDetourPercent on all nets. If the
value is set to n, maxDetourPercent is applied only to nets of
length greater than n gcells.
Usage
To apply maxDetourPercent to all nets, enter the following:
axSetIntParam "groute" "detourLimitMinNetLen" 0
Range
The default is 0.
extraCostsApplyPercent
The extraCostsApplyPercent parameter applies the
wireCost and viaCost settings to the top n percent of nets in the
design. The wireCost and viaCost parameters are route
parameters. The route extra cost applies to GR, TA and DR. This
parameter applies the extra cost percentage only for global route.
Usage
To specify extra cost apply percentage on a wire and via, use the
following syntax:
axSetIntParam "groute" "extraCostsApplyPercent" 50

D-96
Range
default is 50.
extraWireLengthOpt
The extraWireLengthOpt parameter instructs the global router to
run an additional rerouting phase to reduce wire length on nets that
have no congestion. It does not perform any optimization.
Usage
To run an extra pass for optimizing the wire length, enter the
following:
axSetIntParam "groute" "extraWireLengthOpt" 1
When set to 0, no extra pass is performed to optimize wire length.
Range
forceUpperLayersForCritNets
The forceUpperLayersForCritNets parameter specifies the
mode for upper layers usage. To improve timing, Astro will route
timing critical nets on upper layers which have lower RC.
Usage
To specify the mode on upper layers usage on critical nets, enter the
following:

D-97
axSetIntParam "groute" "forceUpperLayersForCritNets" 1
Range
horReserveTracks
The horReserveTracks parameter determines the number of
horizontal free tracks reserved in each gcell.
Usage
To specify the number of horizontal free tracks reserved in each
gcell, use the following syntax:
axSetIntParam "groute" "horReserveTracks" 2
Range
default is 2.
ignoreViaBlockage
The ignoreViaBlockage parameter specifies the mode to honor
a via blockage. By default, global route ignores via blockage.
Usage
To ignore via blockage, enter the following:
axSetIntParam "groute" "ignoreViaBlockage" 1
When set to 0, via blockages are honored.

D-98
Range
The valid values are 0 or1. The default is 1.
incremental
The incremental parameter controls whether global router runs
incrementally.
Usage
To specify the global route incremental mode, enter the following:
axSetIntParam "groute" "incremental" 1
Range
default is 0.
Table D-22 provides the list of valid values of this parameter and their
description.
Table D-22 Valid Values of the incremental Parameter
Value
Description
No incremental global routing
Performs incremental routing
Route only broken nets

D-99
macroBndryDir
The macroBndryDir parameter controls the use of
macroBndryTrkUtil for layers in different directions. If the value
is set to 1, macroBndryTrkUtil will be applied to layers in both
directions.
Usage
To apply macroBndryTrkUtil to the layers in both directions,
axSetIntParam "groute" "macroBndryDir" 1
If the value is set to 0, only the horizontal layers will have

macroBndryTrkUtil applied at top and bottom sides and only the
vertical layers will have macroBndryTrkUtil applied at left and
right sides.
Range
macroBndryExt
The macroBndryExt parameter along with the
macroBndryWidth defines the area in which the global router
obeys macroCornerTrkUtil and macroBndryTrkUtil. By
default, one row or column of gcells is included in the macro
boundary.
This value basically forms the width of the area, where length is
defined by macroBndryWidth.

D-100
Usage
To define the area in which the global router obeys
macroCornerTrkUtil and macroBndryTrkUtil, use the
following syntax:
axSetIntParam "groute" "macroBndryExt" -1
Range
default is -1.
macroBndryTrkUtil
The macroBndryTrkUtil parameter limits the utilization of tracks
available in the gcells near a macro boundary to a specified
percentage. This parameter is used to control the accessibility of
pins and congestion at the macro boundaries. By default, the router
uses 100% of available tracks in the macro boundary width.
Usage
To set the percent usage of tracks available in the gcells near the
macro boundary, use the following syntax:
axSetIntParam "groute" "macroBndryTrkUtil" 100
Range
default is 100.

D-101
macroBndryWidth
The macroBndryWidth parameter specifies a distance from the
corners of macros. Within this distance, the global router obeys the
limits on track utilization specified by macroCornerTrkUtil and
macroBndryTrkUtil. By default, one row or column of gcells is
considered from the corners of the macro.
Usage
To specify the distance from the corners of the macros within which
limits on track utilization apply, use the following syntax:
axSetIntParam "groute" "macroBndryWidth" 1
Range
default is 1.
macroCornerTrkUtil
The macroCornerTrkUtil parameter limits the utilization of
tracks available in the gcells near a macro corner to a specified
percentage. This parameter is used to control the accessibility of
pins and congestion at the macro corners. By default, the router uses
100% of available tracks in the macro boundary width.
Usage
To set the percent usage of tracks available in the gcells near the
macro corner, use the following syntax:
axSetIntParam "groute" "macroCornerTrkUtil" 100

D-102
Range
default is 100.
mapOnly
The mapOnly parameter specifies whether the router generates the
congestion map based on global routing without creating the global
wires.
Usage
To generate the congestion map and the glinks, enter the following:
axSetIntParam "groute" "mapOnly" 0
When set to 1, the router will not generate the glinks.
Range
maxDetourPercent
The maxDetourPercent parameter directs the global router to
have no more than the specified percentage of detours on any net. If
the value is set to -1, the router is free to make any number of detours
(or none).
Usage
To direct the global router to have no more than the specified
percentage of detours on any net, use the following syntax:

D-103
axSetIntParam "groute" "maxDetourPercent" -1
Range
default is -1.
netCriticality
The netCriticality parameter determines the order in which the
global router routes the nets during initial route. Net criticality can be
set on nets in the design by using the Scheme function
dbSetNetCriticality.
If this parameter is set to 1, the global router first routes the nets with
higher criticality value. If the value is set to 0, net criticality has no
effect on routing order. However, net criticality always has an effect
on the congestion cost.
Usage
To turn on the net-criticality mode, enter the following:
axSetIntParam "groute" "netCriticality" 1
When set to 0, the net-criticality mode is turned off.
Range

D-104
noTopLevelBusFeedThroughs
The noTopLevelBusFeedThroughs parameter determines
whether feedthroughs are allowed on bus signals.
Usage
To allow feedthroughs on bus signals during pin assignment, enter
the following:
axSetIntParam "groute" "noTopLevelBusFeedThroughs" 1
When set to 0, feedthroughs are not allowed on bus signals during

pin assignment.
Range
The default values are 0 or 1. The default is 0.
paEqPinNetMaxPort
Setting the paEqPinNetMaxPort parameter to 1 creates
equivalent pins for nets with no more than n ports.
Usage
To specify the number of ports on nets, use the following syntax:
axSetIntParam "groute" "paEqPinNetMaxPort" 20
Range
default is 20.

D-105
powerDriven
The powerDriven parameter turns power-driven global routing on
or off.
Usage
To turn on the power-driven mode, enter the following:
axSetIntParam "groute" "powerDriven" 1
When set to 0, the power-driven mode is turned off.
Range
rcOptByLength
The rcOptByLength parameter controls the choice of layers for
global router to reduce RC. The global router chooses layers with
lower RC values based on the value of this parameter.
Usage
To turn on RC-based layer bias mode, enter the following:
axSetIntParam "groute" "rcOptByLength" 1
Range
default is 1.

D-106
Table D-23 lists the valid values of this parameter and their effect.
Table D-23 Valid Values of the rcOptbyLength Parameter
Value
Description
Turn off RC-based layer bias mode
Turn on RC-based layer bias mode
Turn on RC-based layer bias mode (strong)
reportDemandOnly
The reportDemandOnly parameter specifies the mode to report
demand only. In this mode, Astro performs virtual route only, with no
reroute phases. In the log file, it reports average gcell capacity per
layer.
Usage
To report demand, enter the following:
axSetIntParam "groute" "reportDemandOnly" 0
Range
reportEffectiveOverflow
The reportEffectiveOverflow parameter specifies the mode
for generating an effective overflow report.
Usage
To report effective overflow, enter the following:
D-107
axSetIntParam "groute" "reportEffectiveOverflow" 1
When set to 0, effective overflow is not reported.
Range
reportGCellDensity
The reportGCellDensity parameter controls reporting of gcell
density for each layer. In density-driven mode, the router generates
a report of gcell density. However, this parameter is independent of
the density-driven switch.
Usage
To specify the mode to generate a gcell density report, enter the
following:
axSetIntParam "groute" "reportGCellDensity" 1
When set to 0, gcell density is not reported.
Range
reportNetOrdering
The reportNetOrdering parameter specifies the number of nets
to be reported according to the routing order. By default, the global
router does not report on net ordering. If this parameter is set to n,
global route will report the first n nets in the order of routing.

D-108
Usage
To turn off report net ordering, enter the following:
axSetIntParam "groute" "reportNetOrdering" -1
When set to 0, net ordering is reported for the first 100 nets.
Range
default is -1.
reserveTracksForPowerFile
The file indicated by the reserveTracksForPowerFile
parameter is used to define the percentage of routing tracks on each
layer that are reserved for power routing. For example,
reserveTracksForPowerFile = "reservedTracks.rc"
Suppose the reservedTracks.rc file defines METAL1 layer as

20. Then, the router reserves 20% of available routing tracks in
METAL1 for power routing later. Therefore, global route uses only
80% of the routing tracks.
skewControl
The skewControl parameter turns skew control on or off during
global routing. If the value is set to 1, the global router tries to
minimize the gross delay in net skew. Skew control applies to all
signal nets (except for small nets) but skew control for clock nets
occurs only when clockBalanced is set to 1.

D-109
Usage
To turn on skew control pattern routing, enter the following:
axSetIntParam "groute" "skewControl" 1
When set to 0, the skew control pattern routing is turned off.
Range
skewControlNetBBLowBound
The skewControlNetBBLowBound parameter determines which
nets are considered for skew control during global routing. The
choice is made based on the size of the net measured in number of
gcells. Only nets with size greater than the specified value will be
considered for skew control.
Usage
To specify the minimum size (in gcells) for nets to be subject to skew
control, use the following syntax:
axSetIntParam "groute" "skewControlNetBBLowBound" 5
Range
default is 5.

D-110
skewControlWeight
The skewControlWeight parameter determines the importance
given to skew control on the net during global routing. You can set
the skew control weight from 1 to 10 based on net criticality.
Usage
To specify the weight of skew control, enter the following syntax:
axSetIntParam "groute" "skewControlWeight" 5
Range
default is 5.
speed
The speed parameter specifies the effort at which the global router
should run. The global router runs a different number of phases,
depending on the specified value. It is recommended you run the
router in default mode.
Usage
To perform global routing in the medium-effort mode, enter the
following:
axSetIntParam "groute" "speed" 2
Range
default is 2.

D-111
Table D-24 lists the default values of this parameter and their effect.
Table D-24 Valid Values of the speed Parameter
Value
Description
Router performs initial global routing only
Router performs initial global routing and one rerouting phase
Router performs initial global routing and four rerouting phases
Router performs initial global routing and eight rerouting phases
timingDriven
The timingDriven parameter turns timing-driven global routing on
or off. The timingWeight parameter controls the trade-off between
timing and wire length during global routing. By default, timing-driven
mode is turned off.
Usage
To turn on timing-driven mode, enter the following syntax:
axSetIntParam "groute" "timingDriven" 1
When set to 0, timing-driven mode is turned off.
Range

D-112
timingWeight
The timingWeight parameter sets the weight given to the timing
relative to wire length during global routing. This parameter is
effective only in timing-driven mode.
Usage
To set the timing weight to 4, enter the following:
axSetIntParam "groute" "timingWeight" 4
Range
default is 4.
turboMode
The turboMode parameter is used to improve runtime.
Usage
To turn on turbo mode, enter the following:
axSetIntParam "groute" "turboMode" 1
Range
default is 1.

D-113
Table D-25 lists the values of this parameter and their effect.
Table D-25 Valid Values of the turboMode Parameter
Value
Description
Turns off the turbo mode
Turns on the turbo mode
Special turbo mode for congested designs (runs slower)
VABoundaryToLSWeight
The VABoundaryToLSWeight parameter is used in multivoltage
mode. It specifies the value to adjust the cost for a level shifter
connection when switching voltage area from one to another.
Usage
To specify the cost value for level shifter connection, enter the
following syntax:
axSetIntParam "groute" "VABoundaryToLSWeight" 0
Range
The valid values of this parameter range between 0 and 10, The
default is 0.
verReserveTracks
The verReserveTracks parameter determines the number of
vertical free tracks reserved in each gcell.

D-114
Usage
To specify the number of vertical free tracks reserved in each gcell,
axSetIntParam "groute" "verReserveTracks" 2
Range
default is 2.
xtalkWeight
The xtalkWeight parameter defines the weight given to crosstalk
prevention during global routing.
Usage
To specify the weight given to crosstalk prevention during global
routing, use the following syntax:
axSetIntParam "groute" "xtalkWeight" 4
Range
default is 4.

D-115

Table D-26 lists the PDS optimization parameters.
Table D-26 List of Optimization Parameters
Parameter
Description
aggOpt
Determines whether aggressors are

optimized during postroute
optimization signal integrity flow.
buf_ins_hold
Determines whether buffers are

inserted during hold optimization.
flag_cr_opt
Determines whether critical regions

are fixed during placement
optimization.
hfn_fanout_threshold
Sets the threshold value for the

number of fanouts to trigger
high-fanout optimization.
hfn_max_fanouts
Sets the maximum number of

fanouts for a buffer used for
high-fanout optimization.
max_iteration
Sets the maximum number of

iterations for setup and hold fixing
while running astPostPS,
astSetUpFix, astHoldFix, and
pdsMoveCell.
max_level_buffer
Sets the maximum number of levels

of buffers inserted in high-fanout
optimization.
max_runtime
Sets a maximum runtime for setup

and hold fixing while running
astPostPS, astSetUpFix,
astHoldFix, and pdsMoveCell.

D-116

Parameter
Description
max_utilization
Sets the maximum utilization of the

design before PDS optimization
stops.
move_flip_flop
Determines whether flip-flop

movement is allowed for
placement-driven synthesis
optimization.
no_new_instance
Controls the addition of new

instances while running astPostPS,
astTranFix, astCapFix, and
astHoldFix.
ov_max_displaced_cells
Specifies the maximum number of

cells to be moved during overlap.
ov_max_displacement
Specifies the distance of maximum

displacement (in microns) during
overlap.
pds_message_level
Controls the level of detail in the

messaging report in the log file
during optimization.
pr_use_fpclass
Set when you to want to use the

footprint class.
slack_range_hold_max
Sets the maximum hold slack for

slack range optimization.
slack_range_hold_min
Sets the minimum hold slack for

slack_range_setup_max
Sets the maximum setup slack for

slack_range_setup_min
Sets the minimum setup slack value

for slack range optimization.

D-117

Parameter
Description
target_hold_slack
Sets the target hold time value for

PDS optimization to stop.
target_setup_slack
Sets the target setup time value.
target_utilization
Sets the target utilization value for

the area recovery to stop.
topo_only
Controls the use of topology-based

techniques during postroute
optimization flow.
use_child_router
Controls the use of a child router, to

reduce peak memory usage in the
routing engine when it is called
during optimization.
use_global_cost
Turns the global cost function for

astPostRouteOpt on or off.
wire_delay_model
Sets a wire delay model during

optimization.
xtalk_noise_limit
Sets the noise limit value used by

crosstalk optimization during Pre/
Post-Placement optimization and
Post-CTS optimization.
aggOpt
The aggOpt parameter determines whether aggressors are
optimized during postroute optimization signal integrity flow.
Usage
To optimize the aggressors during postroute optimization signal
integrity flow, enter the following:

D-118
axSetIntParam "pds" "aggOpt" 1
Range
buf_ins_hold
The buf_ins_hold parameter controls the insertion of buffers
during hold optimization that is performed in postroute optimization.
Usage
To insert buffers during hold optimization, enter the following:
axSetIntParam "pds" "buf_ins_hold" 1
When set to 0, buffers are not inserted.
Range
flag_cr_opt
The flag_cr_opt parameter controls whether critical regions are
fixed during placement optimization. When this parameter is set,
additional buffers are inserted.
Usage
To fix critical regions during placement optimization, enter the
following:
axSetIntParam "pds" "flag_cr_opt" 1

D-119
When set to 0, the critical regions are not fixed.
Range
hfn_fanout_threshold
The hfn_fanout_threshold parameter sets the threshold value
for the number of fanouts sufficient to trigger high-fanout
optimization. This value is persistent and stored in the CEL view.
Usage
To specify the threshold value for the number of fanouts to trigger
high-fanout optimization, use the following syntax:
axSetIntParam "pds" "hfn_fanout_threshold" 40
Range
The default is 40.
hfn_max_fanouts
The hfn_max_fanouts parameter is used to set the maximum
number of fanouts for a buffer used for high-fanout optimization.
Usage
To specify the maximum number of fanouts for a buffer used for
high-fanout optimization, use the following syntax:

D-120
axSetIntParam "pds" "hfn_max_fanouts" 40
Range
default is 40.
max_iteration
The max_iteration parameter sets the maximum number of
iterations for setup and hold fixing while running astPostPS,
astSetUpFix, astHoldFix, and pdsMoveCell. Setup and hold
fixing stops when the specified maximum number of iterations is
reached.
Usage
To set the maximum number of iterations for setup and hold fixing,
enter the following syntax:
axSetIntParam "pds" "max_iteration" 100000
Range
The valid values range between 0 and 100000. The default is
100000.
max_level_buffer
The max_level_buffer parameter is used to set the maximum
number of levels of buffers inserted in high-fanout optimization. Do
not change the default value of this parameter without specific
design requirement.

D-121
Usage
To specify the level of buffers inserted in the high-fanout optimization,
axSetIntParam "pds" "max_level_buffer" 6
Range
default is 6.
max_runtime
The max_runtime parameter sets a maximum runtime for setup
and hold fixing while running astPostPS, astSetupFix,
astHoldFix, and pdsMoveCell. Setup and hold fixing stops on
reaching the specified maximum runtime.
Usage
To set a maximum runtime for setup and hold fixing while running
astPostPS, astSetupFix, astHoldFix, and pdsMoveCell,
axSetRealParam "pds" "max_runtime" 604800.000
Range
The valid values range between 0.0 and 2419200.0. The default is
604800.0.

D-122
max_utilization
The max_utilization parameter sets a maximum utilization of
the design before PDS optimization stops. You can control this
parameter value if the chip design and congestion requirements are
stringent.
Usage
To set maximum utilization of the design before PDS optimization
stops, use the following syntax:
axSetRealParam "pds" "max_utilization" 95.000
Range
The valid values of this parameter range between 5.000 to 100.000.
move_flip_flop
The move_flip_flop parameter determines whether flip-flop
movement is allowed for placement-driven synthesis (PDS)
optimization (post CTS). The flip-flop movement changes the clock
tree; therefore, do not use this parameter after the clock tree is
created.
Usage
To allow flip-flop movement for PDS optimization, enter the following:
axSetIntParam "pds" "move_flip_flop" 1
When set to 0, the flip-flops do not move.

D-123
Range
no_new_instance
The no_new_instance parameter is used to prevent the addition
of new instances while running astPostPS, astTranFix,
astCapFix, and astHoldFix.
Usage
To prevent the addition of new instances while running astPostPS,
astTranFix, astCapFix, and astHoldFix, enter the following:
axSetIntParam "pds" "no_new_instance" 0
Range
ov_max_displaced_cells
The ov_max_displaced_cells parameter specifies the
maximum number of cells to be moved during overlap.
Usage
To specify the maximum number of cells to be moved during overlap,

D-124
Range
The valid values range between -1 and 500. The default is -1.
ov_max_displacement
The ov_max_displacement parameter specifies the distance of
maximum displacement (in microns) during overlap.
Usage
To define the distance of maximum displacement during overlap, use
Range
The valid values range between -1 and 1000. The default is -1
pds_message_level
The pds_message_level parameter controls the level of detail in
the messaging report in the log file during optimization.
Usage
To receive a messaging report in the log file during optimization for
every buffer insertion, deletion, cell sizing, and so on, enter the
following:
axSetIntParam "pds" "pds_message_level" -1

D-125
Range
The valid values range between -1 and 10. The default is -1.
pr_use_fpclass
Set the pr_use_fpclass parameter to 1 when you to want to use
the footprint class.
Two cells are defined as footprint-equivalent if they have identical
physical layout, that is, the pin locations and names are identical,
vias and blockages are identical, and they are of the same size.
Usage
To use the footprint class, enter the following:
axSetIntParam "pds" "pr_use_fpclass" 1
By default, the LEQ classes are used.
Range
slack_range_hold_max
The slack_range_hold_max parameter sets the maximum hold
slack for slack range optimization.
Usage
To set the maximum hold slack for slack range optimization, use the
following syntax:

D-126
axSetRealParam "pds" "slack_range_hold_max" 0.000
Range
The valid values of this parameter range between
-99999996802856924650656260769173209088.000 and
99999996802856924650656260769173209088.000. The default is
0.000.
slack_range_hold_min
The slack_range_hold_min parameter sets the minimum hold
slack for slack range optimization.
Usage
To set the minimum hold slack for slack range optimization, use the
following syntax:
axSetRealParam "pds" "slack_range_hold_min" -100.000
Range
-99999996802856924650656260769173209088.000 and
99999996802856924650656260769173209088. The default is
-100.000.
slack_range_setup_max
The slack_range_setup_max parameter sets the maximum
setup slack for slack range optimization.

D-127
Usage
To set the maximum setup slack for slack range optimization, use the
following syntax:
axSetRealParam "pds" "slack_range_setup_max" 0.100
Range
-99999996802856924650656260769173209088.000 and
99999996802856924650656260769173209088.000. The default is
0.100.
slack_range_setup_min
The slack_range_setup_min parameter sets the minimum
setup slack value for slack range optimization.
Usage
To set the minimum setup slack value for slack range optimization,
axSetRealParam "pds" "slack_range_setup_min" -100.000
Range
-99999996802856924650656260769173209088.000 and
99999996802856924650656260769173209088. The default is
-100.000.

D-128
target_hold_slack
The target_hold_slack parameter sets the target hold time
value for PDS optimization to stop.
Usage
To specify the target slack in hold time for PDS optimization to stop,
axSetRealParam "pds" "target_hold_slack" 0.000
Range
The valid values of this parameter range between -1000.000 to
1000.000. The default is 0.000.
target_setup_slack
The target_setup_slack parameter specifies the target setup
time value. This value controls PDS optimization that is
recommended to do iterative change according to the slack
requirement of the design during postroute /postplace optimization.
Usage
To specify the target slack in setup time for PDS optimization to stop,
axSetRealParam "pds" "target_setup_slack" 0.100
Range
The valid values of this parameter range between -1000.000 to
1000.000. The default is 0.100.

D-129
target_utilization
The target_utilization parameter sets the target utilization
value for area recovery to stop. In some cases, it can be used for
controlling the congestion distribution effectively.
Usage
To set the target utilization for area recovery to stop, use the following
syntax:
axSetRealParam "pds" "target_utilization" 50.000
Range
The valid values of target_utilization range between 0.000
and 100.000. The default is 50.
topo_only
The topo_only parameter controls the use of topology-based
techniques during postroute optimization flow.
Usage
To use topology-based techniques during postroute optimization
flow, enter the following:
axSetIntParam "pds" "topo_only" 1
When set to 0, the topology-based technique is not used.

D-130
Range
use_child_router
The use_child_router parameter controls the use of a child
router to reduce peak memory usage in the routing engine when it is
called during optimization. For example, as in ECO routing during
postroute optimization.
Usage
To reduce peak memory usage in the routing engine when it is called
during optimization, enter the following:
axSetIntParam "pds" "use_child_router" 0
Range
Table D-27 provides a description of the valid values of the
use_child_router parameter.
Table D-27 Valid Values of the use_child_router Parameter
Value
Description
This is the default value.

The child router is invoked only
- on x32-bit machines as x64-bit machines allows you to access or
utilize the entire accessible memory.
- when the number of nets is above a certain threshold value.
When the value of the use_child_router parameter is set to 1, the

child router is turned off.

D-131
Table D-27 Valid Values of the use_child_router Parameter

Value
Description
When the value of the use_child_router parameter is set to 2, The

child router is turned on.
use_global_cost
When set to 1, the use_global_cost parameter turns on the
global cost function for astPostRouteOpt. Using this parameter,
Astro performs optimization based on a cost function with each
metric, such as setup, hold, trans, cap, and so on.
The use_global_cost parameter performs optimization to accept
or reject certain transforms. It can used only before
astPostRouteOpt and does not have any user control to change
the cost.
Usage
To turn on the global cost function for the astPostRouteOpt
command, enter the following:
axSetIntParam "pds" "use_global_cost" 1
Range

D-132
wire_delay_model
The wire_delay_model parameter sets a wire delay model during
optimization. It overrides the GUI option in the Timing Setup dialog
box. When the optimization is completed, the original delay model is
restored.
The wire_delay_model parameter can be changed in each stage
of optimization. As timing setup automatically takes care of the delay
models to be used in each design stage, changing this parameter is
not recommended. This parameter is persistent and stored in the
CEL view.
Usage
To set a wire delay model during optimization, use the following
syntax:
axSetIntParam "pds" "wire_delay_model" 0
Range
default is 0.
Table D-28 lists the valid values of wire_delay_model and their
associated delay models.
Table D-28 Valid Values of the wire_delay_model parameter
Value
Description
ATA_ELMORE_WIREDELAY
ATA_AWE_WIREDELAY
ATA_ARNOLDI_WIREDELAY

D-133
xtalk_noise_limit
The xtalk_noise_limit parameter determines the noise limit
value used by crosstalk optimization during Pre/Post-Placement
optimization and Post-CTS optimization. It controls area recovery
during these stages.
Usage
To set the noise limit value used by crosstalk optimization during Pre/
Post-Placement optimization and Post-CTS optimization, use the
following syntax:
axSetRealParam "pds" "xtalk_noise_limit" 0.450
Range
Table D-29 lists the Astro rectilinear parameters.
Table D-29 List of Rectilinear Parameters
Parameter
Description
allowMovePG
Controls movement of power and ground

pins on a rectilinear design.
controlparameter
Specifies the shape of a floorplan.
core2Bottom
Specifies the distance between the bottom

side of the core and top side of the
boundary.

D-134

Parameter
Description
core2Left
Specifies the distance between the left side

of the core and right side of the boundary.
core2Right
Specifies the distance between the right

side of the core and left side of the
boundary.
core2Top
Specifies the distance between the top side

of the core and bottom side of the
boundary.
doubleBack
Controls double-back mode, in which the

core contains pairs of cell rows, with one
row in each pair flipped.
flipfirst
Used in double-back mode; determines

whether to flip a row at the bottom of a
horizontal core area or the left side of a
vertical core area.
forceTrackAlignment
When set to 1, forces the alignment of

tracks in double-back mode.
lengthMode
Used to calculate the core utilization on a

rectilinear design.
macros
Controls movement of macros.
rotation
Used to rotate a rectilinear object

clockwise.
rowDirction
Sets the row direction as horizontal or

vertical.
rowRatio
Specifies the amount of channel space that

needs to be provided for routing between
the cell rows.
rpinECO
Controls ECO mode for rectilinear pin

placement.
D-135

Parameter
Description
startfirst
Used in double-back mode; determines

whether to put a pair of rows at the bottom
of a horizontal core area or left side of a
vertical core area.
stdcells
Controls movement of standard cells.
utilization
Sets the core utilization area for cell

placement.
allowMovePG
The allowMovePG parameter controls the movement of power and
ground pins on a rectilinear design.
Usage
To move power and ground pins, enter the following:
axSetIntParam "rectilinear" "allowMovePG" 1
When set to 0, the power and ground pins are not moved.
Range
controlparameter
The controlparameter parameter specifies the shape of a
floorplan.

D-136
Usage
To add an L-shaped rectilinear object, enter the following:
axSetIntParam "rectilinear" "controlparameter" 1
Range
default is 1.
Table D-30 lists the valid values of controlparameter and their
associated shapes.
Table D-30 Valid Values of controlparameter
Value
Description
L shape
T shape
U shape
Cross shape
Boundary (users boundary shape)
core2Bottom
The core2Bottom parameter specifies the distance between the
bottom side of the core and top side of the boundary.
Usage
To specify the distance between the bottom side of the core and top
side of the boundary, use the following syntax:
axSetRealParam "rectilinear" "core2Bottom" 10.000
D-137
Range
core2Left
The core2Left parameter specifies the distance between the left
side of the core and right side of the boundary.
Usage
To specify the distance between the left side of the core and right
axSetRealParam "rectilinear" "core2Left" 10.000
Range
core2Right
The core2Right parameter specifies the distance between the
right side of the core and left side of the boundary.
Usage
To specify the distance between the right side of the core and left
axSetIntParam "rectilinear" "core2Right" 10.000

D-138
Range
core2Top
The core2Top parameter specifies the distance between the top
side of the core and bottom side of the boundary.
Usage
To specify the distance between the top side of the core and bottom
axSetRealParam "rectilinear" "core2Top" 10.000
Range
doubleBack
The doubleBack parameter is set when you want the core to
contain pairs of cell rows, with one row in each pair flipped.
Usage
If you want the core to contain pairs of cell rows, with one row in each
pair flipped, enter the following:
axSetIntParam "rectilinear" "doubleBack" 1
When set to 0, the double back is not set.
D-139
Range
flipfirst
The flipfirst parameter is used if you selected Double Back and
want a flipped row at the bottom of a horizontal core area or left side
of a vertical core area.
Usage
If you selected Double Back and want a flipped row at the bottom of
a horizontal core area or left side of a vertical core area, enter the
following:
axSetIntParam "rectilinear" "flipfirst" 1
Set it to 0 when you want an unflipped row at the bottom of a

horizontal core area or left side of a vertical core area.
Range
forceTrackAlignment
When set to 1, the forceTrackAlignment parameter forces the
alignment of tracks in double-back mode.
Usage
To force track alignment, enter the following:
axSetIntParam "rectilinear" "forceTrackAlignment" 1

D-140
When set to 0, there is no track alignment in double-back mode.
Range
lengthMode
The lengthMode parameter is used to calculate the core utilization
on a rectilinear design.
Usage
To calculate the core utilization on a rectilinear design, enter the
following:
axSetIntParam "rectilinear" "lengthMode" 0
When set to 1, the true size value is used.
Range
macros
The macros parameter controls movement of macros.
Usage
To turn on macro movement, enter the following:
axSetIntParam "rectilinear" "macros" 0
D-141
When set to 1, macro movement is turned off.
Range
rotation
The rotation parameter rotates a rectilinear object.
Usage
To rotate a rectilinear object by 90 degrees, enter the following:
axSetIntParam "rectilinear" "rotation" 1
When set to 0, the rectilinear object is not rotated.
Range
default is 0.
Table D-31 lists the valid values of rotation parameter with their
description.
Table D-31 Valid Values of the rotation Parameter
Value
Description
Rotation is 0 degree

D-142
rowDirction
The rowDirction parameter sets the row direction as horizontal or
vertical.
Usage
To set the row direction as horizontal, enter the following:
axSetIntParam "rectilinear" "rowDirction" 0
When set to 1, the row direction is set as vertical.
Range
rowRatio
The rowratio parameter specifies the amount of channel space
that needs to be provided for routing between cell rows. The smaller
the number, the more space Astro leaves for routing channels.
Usage
To indicate the amount of channel space that needs to be provided
for routing between the cell rows, enter the following syntax:
axSetRealParam "rectilinear" "rowRatio" 0.00
When set to 1, no routing channel space is left.
Range
The valid values range from 0.0 to 1.0. The default is 1.0.
D-143
rpinECO
The rpinECO parameter controls ECO mode for rectilinear pin
placement.
Usage
To turn on ECO mode for rectilinear pin placement, enter the
following:
axSetIntParam "rectilinear" "rpinECO" 1
When set to 0, ECO mode is turned off during rectilinear pin

placement.
Range
startfirst
The startfirst parameter is used if you selected Double Back
and want a pair of rows at the bottom of a horizontal core area or left
side of a vertical core area.
Usage
If you want a pair of rows at the bottom of a horizontal core area or
left side of a vertical core area, enter the following:
axSetIntParam "rectilinear" "startfirst" 1
Set it to 0, if you want a single row at the bottom of a horizontal core

area or left side of a vertical core area.

D-144
Range
stdcells
The stdcells parameter controls movement of standard cells.
Usage
To move standard cells, enter the following:
axSetIntParam "rectilinear" "stdcells" 0
When set to 1, standard cell movement is turned off.
Range
utilization
The utilization parameter specifies the core utilization area for
cell placement, as a ratio of the total cell area (standard and macro
cells) to the core area.
Usage
To set the set the smallest core utilization area value for cell
placement, enter the following:
axSetRealParam "rectilinear" "utilization" 0.0
When set to 1, the highest core utilization value is set.
D-145
Range
The valid values of this parameter range between 0.0 and 1.0. The
default is 0.8.
Timing Parameters
Table D-32 lists the Astro timing parameters.
Table D-32 List of Timing Parameters
Parameter
Description
all_macro_as_VR_block
Determines whether a macro that is

not blocked on all the metal layers is
treated as a virtual route blockage.
ata_crp_transition
Determines how the clock

reconvergence pessimism value is
computed in the event of a mismatch at
a common point.
ata_crpr_threshold_ps
Specifies the amount of pessimism

that CRPR is allowed to leave in the
timing report.
capture_path_propagate_worst_slew
Used for improved correlation with

PrimeTime under bc_wc timing
analysis.
case_analysis_disable_entire_path
Determines whether only the last edge

is disabled or all the edges are
disabled along a path where a constant
is propagated.
case_analysis_sequential_propagation
Determines whether case analysis is

propagated across sequential cells.
clock_cell_has_multiple_edge
Reduces the clock traverse time for

reconvergent clock networks.

D-146

Parameter
Description
clock_gating_propagate_enable
Determines whether the gating enable

signal delay and slew propagate
through the gating cell.
clock_tree_report_debug_mode
Controls whether the astClockTree

output exactly matches the IC
Compiler exception pins report.
disable_cond_default_arcs
Enables or disables the default

nonconditional timing arcs between
pins that have conditional arcs.
driving_cell_include_cell_delay
Determines whether to include or

ignore the cell delay of a driving cell in
the timing path delay.
early_launch_at_borrowing_latches
When set to 1, removes clock latency

pessimism from the launch times for
paths that begin at the data pins of
transparent latches.
group_path_opt
Enables or disables optimization by

path group.
max_RG_size_multiplier
Controls the minimum size of route

guides considered by virtual route for
RC estimation.
multicycle_hold_follow_setup
Determines whether multicycle path

exceptions defined on setup
relationships affect the hold
relationship.
non_unate_clock_compatibility
Controls the clock sense considered

for analysis in a non-unate clock
network.
Timing Parameters
D-147

Parameter
Description
print_Clock_Timing_For_Mixed_Edges
Controls whether delay and transition

values of clock path or data path is
reported for mixed-signal edges in
report_delay calculation and SDF
output.
pulse_latch_as_ICG_cell
Determines whether to consider the

pulse latch cell as an ICG cell.
rc_degrade_min_slew_when_rd_less_t
han_rnet
Enables or disables slew degradation

through the RC network in minimum
analysis when the library-derived drive
resistance is significantly less than
dynamic RC network impedance to
ground.
remove_Escape_From_Bus
Controls the filtering of backslash in a

bus name while exporting SDF.
report_timing_through_sync_pin
Used in JupiterXT during clock

planning. It controls the clock
propagation beyond sync pin.
rpt_max_cap_multiplier
Determines the maximum capacitance

constraint considered by
astReportTiming to report maximum
capacitance violations.
rpt_max_tran_multiplier
Determines the maximum transition

astReportTiming to report maximum
rpt_min_cap_multiplier
Determines the minimum capacitance

astReportTiming to report minimum
capacitance violations.

D-148

Parameter
Description
rpt_min_tran_multiplier
Determines the minimum transition

astReportTiming to report minimum
splitEK
Determines whether to split the

extraction kernel during timing
analysis.
all_macro_as_VR_block
The all_macro_as_VR_block parameter determines whether a
macro that is not blocked on all the metal layers is treated as a virtual
route blockage.
Usage
To consider all macros as virtual route blockages even if they do not
block all metal layers, enter the following syntax:
axSetIntParam "ata" "all_macro_as_VR_block" 1
If set to 0, macros that do not block all the metal layers are not treated
as blockages.
Range
Timing Parameters
D-149
ata_crp_transition
The ata_crp_transition parameter determines how the clock
reconvergence pessimism value is computed depending upon the
transition sense at common point.
Usage
To use the minimum of rise and fall clock reconvergence pessimism
values in the event of a mismatch at a common point, enter the
following:
axSetIntParam "ata" "ata_crp_transition" 0
When set to 1, zero-clock reconvergence pessimism is used in the

event of a mismatch.
Range
The valid values are 0 (normal) or 1(same_transition). The
default is 0.
Equivalent PrimeTime Parameter

The equivalent PrimeTime parameter is
timing_clock_reconvergence_pessimism
ata_crpr_threshold_ps
The ata_crpr_threshold_ps parameter specifies amount of
pessimism that CRPR is allowed to leave in the timing report. This
parameter is measured in picoseconds (ps), regardless of the main
library units.

D-150
The larger the value, the faster the runtime when CRPR is active.
The recommended setting is about one half of the stage (gate plus
net) delay of a typical stage in the clock network. This value provides
a reasonable trade-off between accuracy and runtime in most cases.
You might want to use large values during the design phase and
small values during signoff. Experiment and try a different value
when moving to a different technology.
Usage
To specify the amount of pessimism that CRPR is allowed to leave in
a report, enter the following syntax:
axSetRealParam "ata" "ata_crpr_threshold_ps" 20.000
Range
99999996802856924650656260769173209088.000. The default is
20.0. The threshold values range between 1 and 1e+38
picoseconds.

timing_crpr_threshold_ps.
capture_path_propagate_worst_slew
The capture_path_propagate_worst_slew parameter is used
for improved correlation with PrimeTime under bc_wc timing
analysis. It controls the propagation of worst slew at merge points in
the capture clock path.
Timing Parameters
D-151
Usage
To improve correlation with PrimeTime under bc_wc timing analysis,
axSetIntParam "ata" "capture_path_propagate_worst_slew" 0
Range
During bc_wc timing analysis, when the parameter is set to the
default value at slew merge points along the capture clock path,
Astro propagates the worst slew (fastest slew during max delay
analysis and slowest slew in min delay analysis) forward. This makes
the analysis in Astro pessimistic when compared to PrimeTime.
Set this parameter to 0 to correlate with PrimeTime.
case_analysis_disable_entire_path
The case_analysis_disable_entire_path parameter
determines whether only the last edge is disabled or all the edges
are disabled along a path where a constant is propagated.
Usage
axSetIntParam "ata" "case_analysis_disable_entire_path" 0
By default, when the parameter is set to 0, only the last edge is

disabled. So before disabled edges, the entire transition time can
inherit the transition time from the previous stage, making the value
more accurate. Consequently, Astro fixes more maximum-transition
violations.

D-152
When the parameter is set to 1, it disables all those edges along the
path until the constant does not affect the design anymore. It means
that all affected edges along the path are disabled. So, timing
information cannot propagate through those timing arcs. Therefore,
both arrival time and slope values are affected.
If an arc is disabled, both arrival time and transition time are not
propagated through the arc.
Range
The case_analysis_sequential_propagation parameter
determines whether case analysis is propagated across sequential
cells.
Usage
To enable case analysis constants to propagate across sequential
cells, enter the following:
axSetIntParam "ata" \
"case_analysis_sequential_propagation" 1
By default, case analysis is not propagated across sequential cells.
Range
Timing Parameters
D-153

clock_cell_has_multiple_edge
The clock_cell_has_multiple_edge parameter reduces the
clock traverse time for reconvergent clock networks.
Astro supports this parameter starting from version Y-2006.06-SP3.
Usage
To reduce the clock traverse time for reconvergent clock networks,
axSetIntParam "ata" "clock_cell_has_multiple_edge" 1
Range
clock_gating_propagate_enable
The clock_gating_propagate_enable parameter controls
whether the delay and slew of the clock signal or the gating signal is
propagated to the output of a cell, where clock gating occurs.
Usage
By default, when the parameter is set to 1, Astro propagates the
delay and slew of the gating signal. Setting the parameter to 1 is
recommended when the output of the gating cell goes to a data pin.

D-154
To allow the delay and slew from the clock line set the parameter to 0:
axSetIntParam "ata" "clock_gating_propagate_enable" 0
Setting the parameter to 0 produces the most desirable behavior

when the output goes to a clock pin of a sequential cell.
Range

timing_clock_gating_propagate_enable.
clock_tree_report_debug_mode
The clock_tree_report_debug_mode parameter, when turned
on, generates astReportClockTree output that exactly matches
with IC Compiler exception pins report.
Astro supports this parameter starting from version Y-2006.06-SP3.
Usage
To get a report that exactly matches the IC Compiler report, enter the
following:
axSetIntParam "ata" "clock_tree_report_debug_mode" 1
Range
Timing Parameters
D-155
disable_cond_default_arcs
The disable_cond_default_arcs parameter enables or
disables the default nonconditional timing arcs between pins that
have conditional arcs.
Usage
To disable nonconditional timing arcs between any pair of pins that
have at least one conditional arc, enter the following:
axSetIntParam "ata" "disable_cond_default_arcs" 1
When the specified conditions cover all possible state-dependent

delays, so that the default arc is of no use, set this parameter to 1.
When set to 0, the nonconditional timing arcs are not disabled.
Range

timing_disable_cond_default_arcs.
driving_cell_include_cell_delay
The driving_cell_include_cell_delay parameter
determines whether to include or ignore the cell delay of a driving cell
in the timing path delay.

D-156
Usage
To include the cell delay of a driving cell in the timing path delay,
axSetIntParam "ata" "driving_cell_include_cell_delay" 1
When set to 0, the cell delay of a driving cell is ignored in the timing
path delay.
Range
early_launch_at_borrowing_latches
When set to 1, the early_launch_at_borrowing_latches
parameter removes clock latency pessimism from the launch times
for paths that begin at the data pins of transparent latches. This
parameter is turned off when clock reconvergence pessimism
removal (CRPR) is enabled.
Sometimes there is a difference between launching and capturing
clock latencies, either due to reconvergent paths in the clock network
or different minimum and maximum delays of cells in the clock
network. For setup paths, Astro uses the late value to launch and the
early value to capture. This achieves the tightest constraint and
avoids optimism.
However, for paths starting from latch data pins (latches where time
borrowing has occurred and that are in transparent phase), this is
pessimistic since data simply passes through and therefore does not
even observe the clock edge at the latch. The
Timing Parameters
D-157
early_launch_at_borrowing_latches parameter can be

used to eliminate such pessimism by using the early clock latency to
launch such paths.
Usage
Set this parameter to 1 to use early clock latency for launching setup
paths starting from the data pin of latches. The syntax is
axSetIntParam "ata" "early_launch_at_borrowing_latches" 1
When set to 0, late clock latency is used to launch all setup paths in
the design.
This form of pessimism removal is recommended, since it does not
cause the runtime of analysis to increase. CRPR may not be applied
to paths which have been launched using an early latency or the
results may be optimistic. Since CRPR is a more sophisticated and
accurate means of pessimism removal, Astro turns off this
parameter when CRPR is turned on.
Range

timing_early_launch_at_borrowing_latches.The default
is 1.

D-158
group_path_opt
The group_path_opt parameter controls optimization by path
group.
Usage
To enable optimization by path group, enter the following:
axSetIntParam "ata" "group_path_opt" 1
When set to 0, the optimization by path group is disabled.
Range
max_RG_size_multiplier
The max_RG_size_multiplier parameter controls the minimum
size of the route guides considered by virtual route for RC
estimation. This parameter is used only for virtual routing and does
not affect the routing behavior.
Virtual route is used to estimate pre-route RC and therefore should
consider large route guides only. Small route guides are not useful to
virtual route because their effect on RC estimation is negligible.
If you process small route guides, it results in CPU and memory
wastage. Regardless of what is done in virtual route, both large and
small route guides are handled by the router.
Timing Parameters
D-159
Usage
By default, a route guide that is smaller than two row heights is
ignored by the virtual route. To set the row height of the route guide
as 2, enter the following:
axSetRealParam "ata" "max_RG_size_multiplier" 2.0
Range
default is 2.0.
multicycle_hold_follow_setup
The multicycle_hold_follow_setup parameter determines
whether multicycle path exceptions defined on setup relationships
affect the hold relationship.
Changing the setup relationship implicitly changes the hold
relationship because all hold relationships are based on valid setup
relationships. Astro verifies that the data launched by setup launch
edge is not captured by the previous capture edge.
Usage
To specify that multicycle path exceptions defined on setup
relationships affect the hold relationship, enter the following:
axSetIntParam "ata" "multicycle_hold_follow_setup" 1
When set to 0, the setup relationship does not affect the hold
relationship.

D-160
Range
non_unate_clock_compatibility
The non_unate_clock_compatibility parameter controls the
clock sense considered for analysis in a non-unate clock network.
Usage
To consider only the noninverting sense of the clock, enter the
following:
axSetIntParam "ata" "non_unate_clock_compatibility" 1
When set to 0, both the inverting sense and noninverting sense of

the clock are analyzed simultaneously.
Range

timing_non_unate_clock_compatibility.
Timing Parameters
D-161
print_Clock_Timing_For_Mixed_Edges
The print_Clock_Timing_For_Mixed_Edges controls whether
it is the clock path or the data path whose delay and transition values
are reported for mixed signal edges in the report_delay
calculation and SDF output. This parameter affects report delay
calculation and SDF export.
Usage
To obtain the clock path value report, enter the following:
axSetIntParam "ata" "print_Clock_Timing_For_Mixed_Edges" 1
Set the parameter to 0 to obtain the data path report.
Range
pulse_latch_as_ICG_cell
The pulse_latch_as_ICG_cell parameter determines whether
the pulse latch cell is considered as an ICG cell. This parameter
controls the tracing through the pulse latch.
Usage
To specify the pulse latch cell as an ICG cell, enter the following:
axSetIntParam "ata" "pulse_latch_as_ICG_cell" 1
By default, the pulse latch cell is not considered as an ICG cell.

D-162
Range
rc_degrade_min_slew_when_rd_less_than_rnet
The rc_degrade_min_slew_when_rd_less_than_rnet
parameter enables or disables slew degradation through the RC
network in minimum analysis when the library-derived drive
resistance is significantly less than the dynamic RC network
impedance to ground.
Usage
To perform slew degradation in minimum analysis mode, enter the
following:
axSetIntParam "ata"\
"rc_degrade_min_slew_when_rd_less_than_rnet" 1
By default, when the value is 0, Astro does not degrade the transition
for minimum delay computation on affected nets.
Range

rc_degrade_min_slew_when_rd_less_than_rnet
Timing Parameters
D-163
remove_Escape_From_Bus
The remove_Escape_From_Bus parameter is used to control the
filtering of backslash in a bus name while exporting SDF.
Usage
To filter out backslashes (used as escape characters) from a bus
name while exporting SDF, enter the following:
axSetIntParam "ata" "remove_Escape_From_Bus" 1
By default, Astro writes out backslash for buses in SDF, for example,
A\/\\B\[2\]/C.
To avoid inconsistencies with the Verilog file written out of Astro and
consequent issues during mapping in PrimeTime, use this
parameter to prevent the backslash from being written out, for
example, A/\B[2]/C.
Range
report_timing_through_sync_pin
The report_timing_through_sync_pin parameter is used in
JupiterXT during clock planning. This parameter controls clock
propagation beyond sync pin.
Usage
To turn on the propagation at sync pin, enter the following:
axSetIntParam "ata" "report_timing_through_sync_pin" 1
D-164
When set to 0, the clock propagation stops at sync pin.
Range
rpt_max_cap_multiplier
The rpt_max_cap_multiplier parameter determines the
maximum capacitance constraint considered by
astReportTiming to report maximum capacitance violations.
Usage
axSetRealParam "ata" "rpt_max_cap_multiplier" 1.050
The maximum capacitance constraint multiplied by this factor is

taken as the constraint for reporting maximum capacitance
violations.
Range
default is 1.050.
rpt_max_tran_multiplier
The rpt_max_tran_multiplier parameter determines the
maximum transition constraint considered by astReportTiming to
report maximum transition violations.
Timing Parameters
D-165
Usage
axSetRealParam "ata" "rpt_max_tran_multiplier" 1.050
The maximum transition constraint multiplied by this factor is taken

as a constraint for reporting the maximum transition violations.
Range
default is 1.050.
rpt_min_cap_multiplier
The rpt_min_cap_multiplier parameter determines the
minimum capacitance constraint considered by astReportTiming
to report minimum capacitance violations.
Usage
axSetRealParam "ata" "rpt_min_cap_multiplier" 1.050
Minimum capacitance constraint multiplied by this factor is taken as

a constraint for reporting the minimum capacitance violations.
Range
default is 1.050.

D-166
rpt_min_tran_multiplier
The rpt_min_tran_multiplier parameter determines the
minimum transition constraint considered by astReportTiming to
report minimum transition violations.
Usage
axSetRealParam "ata" "rpt_min_tran_multiplier" 1.050
The minimum transition constraint multiplied by this factor is taken as

a constraint for reporting the minimum transition violations.
Range
default is 1.050.
splitEK
The splitEK parameter determines whether to split the extraction
kernel during timing analysis. Splitting the process reduces peak
memory used by Astro.
Usage
To split the extraction kernel, enter the following:
axSetIntParam "ata" "splitEK" 1
When set to 0, the extraction kernel is not split.
Timing Parameters
D-167
When the splitEK parameter is used together with another

parameter, for example, splitThreshold, it tells the tool when to
split the extraction kernel process.
axSetIntParam "ek" "splitThreshold" 150000
;; range [0,1000000], default=150000;
In the above example, the extraction kernel process is split after the
number of instances in a design exceeds 150000.
Range

D-168
Glossary
GL
block
The meaning of block depends on the context in which the term is
used.
In the logical hierarchy, a block is also called a module, logic

block, or subblock.
In the physical hierarchy, a block is also called a cluster, physical

block, or floorplan block.
blockage
Rectangular areas in which cells cannot be placed. Blockages can
be soft or hard.
A soft blockage prevents cell instances, except for cell instances

that are either fixed or softfixed, from being placed inside an area.
A soft blockage allows cells to be added for optimization
A hard blockage prevents all cell instances from being placed

inside an area (the only exception is a fixed cell instance). A hard
blockage does not allow cells to be added for optimization
GL-1
cluster
Partitioning of cells in a design on a physical chip, used to guide the
layout tools and optimization commands. Clusters in the hierarchy
for the top level must match the hierarchy for the logic modules in
the top level. Clusters are sometimes called physical blocks or
floorplan blocks. Clusters have hard boundaries.
core area
The area where standard cells are placed.
die area
The silicon area of the chip.
DRC
Design rule checking, which differs between the logic and physical
domains.
Logic domain: Timing design rule constraints that must be met

before further optimization for skew and insertion delay;
examples are fanout, transition, and capacitance.
Physical domain: Wire spacing and so forth.
filler cell
A physical-only cell used by silicon vendors to fill open areas in the
rows to make sure all power nets are connected. Usually this is
done after placement is complete.
fixed
A status assigned to cell instances. Cell instances of fixed status
can neither be placed nor optimized. They can be moved only with
the geMove command. A fixed cell instance automatically prevents
netlist optimization commands from changing it. A fixed status
implies a dont touch status. A fixed cell instance can legally stay
within any placement blockages (hard or soft).
GL-2
flyline
A pin-to-pin connection (segment), drawn as a straight line between
two pins.
hot spot
A place in the floorplan that is highly congested.
isolation cell
A cell that is used to isolate the signals coming from an unpowered
voltage area.
legalized cell
A placed cell that does not overlap other cells or blockages and is
placed on a legal tile location. Different die technologies have
different rules that specify which cells are legal and where.
legalized placement
A placement in which no row contains more cells than the number
of tiles available. All cells are placed on legal locations, snapped to
the tile array grid.
level-shifter cell
A special cell that can carry a signal across different voltage areas.
operating condition
The combined process, operating voltage, temperature, and other
information that controls the performance of a cell instance. This
information is needed to compute the proper timing delay of a cell.
pin
The input and output of cells within a design (such as gates and
flip-flops). The ports of a subdesign are pins within the parent
design.
pitch
The centerline-to-centerline spacing of metal tracks on the same
layer. Pitch is defined in the physical technology library.
GL-3
port
The inputs and outputs of a design. Port direction is designated as
input, output, or inout.
RC correlation
The process of comparing RC parameters before and after routing
and then tuning RC parameter values to reflect the true wire delays.
region constraint
Rectangular areas in which you can constrain the placement of a
subset of standard cells.
routing guide
The process of changing the routing direction or prohibiting
automatic prerouting as well as global routing within a defined area
on specific layers.
soft-fixed
A status assigned to cell instances. Cell instances of soft-fixed
status cannot be placed or moved but can be optimized with netlist
optimization commands. A soft-fixed cell instance cannot legally
stay within hard placement blockages. Netlist optimization
commands can create buffers or inverters in soft placement
blockage areas (during in-placement optimization or postplacement
optimization) with soft-fixed status. During optimization, soft-fixed
cells can be moved to improve timing. Soft-fixed cells cannot be
moved during global placement.
spare cell
A logic gate added to a design to allow quick, logic changes to be
made without replacing all mask layers of the chip. Spare cells exist
in the netlist and the input PDEF. Spare cells are not the same as
filler cells.
GL-4
unfixed
A status assigned to cell instances. Cell instances of unfixed status
can be placed, moved, or optimized. However, when being placed,
they cannot be placed within any (hard or soft) placement blockage.
unit tile cell
The smallest unit of placement. The width of the unit tile is the
metal2 pitch. The height is the standard cell height, unless you are
using double-, triple-, and multiple-height cells. Each standard cell
library contains a unit tile cell. There is no need to redefine the unit
tile cell when using double-, triple-, and multiple-height cells.
voltage area
An area you define that describes the legal locations of cells in a
voltage domain. You create a voltage area by drawing a rectilinear
shape that defines its boundary. Typically, voltage areas need to
coincide with the power supply structures of the chip.
voltage domain
A physical or logical grouping of cell instances that share an
identical power supply with a certain operating voltage.
GL-5
GL-6
Index
A
ALF (Advanced Library Format) files
loading 16-4
sample constraints 16-30
antennas
about fixing 14-10
checking and fixing floating wire 14-11
data preparation
CLF requirements 3-40, 14-6
diode cell 14-8
hierarchical requirements 14-7
TDF requirements 14-6
technolgy file 14-8
deleting diodes 14-17
flow for fixing 14-3
importing reports from Hercules 14-18
inserting diodes 14-15
inserting diodes on preroute nets 14-9
reporting violations 14-18
setting the mode 14-13
application startup files 2-37
application window
exiting 2-39
starting 2-4
aprAddGroupBySelSet command 8-47
aprCmdCreateHierGroup command 8-47
aprCmdFixCell command 8-47
aprCreateGCTSExplorer command 9-66

aprPGConnect command 4-15, 5-2, 11-18
aprSetDensity command 8-71
area placement, command to run 8-71
area recovery, optimization 8-103
astAddPlaceSRConst command 8-70
astAreaRecovery command 8-103
astAutoPlace command 8-3, 8-4, 8-17, 8-22,
8-40, 15-7
astCapFix command 8-93
astChangeNetlist command 7-23, 12-22
astCheckDesign command 6-4, 7-32, 7-33,
7-39, 8-64
astCheckDesignForCTS command 6-4, 9-5,
9-12
astCheckHierPresConsistency command
4-16, 4-28
astClearDesignLEQ command 3-39
astClockBrowser command 9-5, 9-14
astClockOptions command 8-36, 8-37, 9-5,
9-9, 9-18
astClockTiming command 9-5, 9-100
astCTO command 9-5, 9-9, 9-58, 9-68, 9-76,
9-77
astCTOInterClocksBalance command 9-5,
9-83, 9-84
IN-1
astCTS command 8-38, 9-5, 9-9, 9-49, 9-58,

9-61, 9-63, 9-69, 9-72, 9-73, 9-74, 9-75,
9-110
astCTSBasic command 9-5, 9-49
astDeleteClockTree command 9-5, 9-58
astDeleteHierPreservation command 4-28
astDesignRules command 8-82, 8-89, 8-91,
8-93
astDSPFOut command 13-19
astDumpAttachedDesignLEQFile command
3-40
astDumpDesignLEQ command 3-39
astDumpHFN command 8-65
astDumpHierPreservation command 4-28
astDumpHierVerilog command 4-16, 4-19,
12-24, 13-18
astDumpLEQ command 7-40
astECOCTS command 9-5, 9-95, 12-22
astEdit command 7-21, 12-22
astExtrLEQ command 3-23, 3-36
astFanoutSetup command 8-68, 8-88
astFastPlace command 6-4, 7-33
astGenPV command 13-13, 15-13, 15-52
astHFCTS command 9-9, 9-107, 9-109, 9-110
astHoldGenerateCutSet command 8-101
astInitHierPreservation command 4-15, 4-16,
4-17, 6-6
astLenBI command 8-93, 8-94, 12-22
astLoadDesignLEQ command 3-38
astLPEOut command 13-18
astMagnetPlace command 8-14, 8-16
astMarkClockTree command 9-5, 9-54, 9-56,
9-57, 9-59, 9-67, 9-75, 9-76
astMarkHierAsPreserved command 4-15,
4-18, 5-2
astPath command 7-10
astPathClear command 7-10
astPlaceArea command 8-67, 8-71
astPlaceDesign command 8-66, 8-67
IN-2
astPlaceOptions command 8-71

astPostGR command 7-29, 10-32, 11-19
astPostPS command 7-29, 8-83, 8-84, 8-85,
8-86
astPostPS1 command 7-29, 8-78, 15-10
astPostRouteCTO command 9-5, 9-9, 9-91
astPostRouteOpt command 11-2, 11-4, 11-5,
11-8, 15-53, 15-54
astPostRT command 7-29, 7-41, 11-21, 11-24
astPowerRecovery command 8-35, 11-15,
11-16
astPrePS command 8-58, 8-59, 8-63
astRepairHierPreservation command 4-16,
4-23, 4-24, 4-25, 12-23, 12-24
astReportClockTreePower command 9-6,
9-111, 9-112
astReportTiming command 7-3, 15-22, 15-44,
15-46, 15-48
Astro
benefits, list of 1-3
data requirements 3-4
design flow
detailed A-1
overview 1-7
documentation set 1-9
exiting a session 2-39
licensing requirements 1-6
output files, list of 3-6
product packages, list of 1-4
recommended script-based methodology
1-10
starting a session 2-4
supported platforms 1-6
user interfaces 2-3
Astro Interactive Ultra, working with 12-28
Astro-Rail, about 1-11
astSearchRefine command 8-67, 8-69, 8-70
astSetCellInstDontTouch command 9-10
astSetClockCell command 9-10, 9-29, 9-30,
9-31, 9-35, 9-37, 9-39, 9-79, 9-80, 9-82,
9-83
astSetDelayCell command 8-98, 8-100, 9-10,

9-36, 9-37, 9-82
astSetDontTouch command 9-9, 9-10
astSetDontUse command 9-9, 9-10, 11-8
astSetSizeOnly command 8-20
astSkewAnalysis command 9-5, 9-102, 9-104,
9-108
astSPEFOut command 13-19
astSPICEOut command 13-19
astSplitClockNet command 9-5, 9-9
astStarRCXT command 6-41
astSynNetSkewReport command 9-107,
9-108
astTimingDataCheck command 6-3, 7-30,
7-37
astTimingModel command 13-15
astTimingProbe command 7-11
astTopoHold command 8-96, 8-97, 8-98
astTopoTransCap command 8-91, 8-92, 8-93
astTransFix command 8-93
astWriteDC command 6-14, 8-20
astXTalkFix command 15-60, 15-61
ataDefineIgnorePin command 9-11
commands
ataDefineIgnorePin 9-28
ataDefineSyncPin command 9-8, 9-11, 9-22,
9-23, 9-24
ataDefineSyncPort command 9-8, 9-22, 9-23,
9-24
ataDisableIdealNetworkDelay command 6-30
ataDumpClockNets command 10-13
ataDumpPropagatedMaxCap command 6-61
ataDumpSDC command 9-9, 9-10
ataDumpSDF command 13-19, 15-50
ataEnableIdealNetworkDelay command 6-30
ataLoadSDC command 6-9, 6-13, 6-14, 7-36,
7-37, 9-111
ataPurgeDBUsefulSkew command 9-72
ataRemoveMaxCapBoundPort command 6-61
ataRemoveMaxCapClockData command 6-61

ataRemoveTC command 6-13
ataSetAndPropagateMaxCapBoundPort
command 6-60
ataSetAndPropagateMaxCapClock command
9-10, 9-44
ataSetAndPropagateMaxCapClockData
command 6-61
ataSetAndPropagateMaxTransClock
command 9-5, 9-10, 9-44
ataSetDisableTiming command 7-31
ataSetNetCapTransAndDelayTime command
6-11, 6-63, 6-64, 8-63, 8-65, 9-10, 9-12
ataSetTimeBorrowMethod command 6-22
ataSkewAnalysisTriggerAware variable 9-102
ataWriteTC command 6-11, 6-12, 6-18, 8-65
atTimingSetup command 6-19, 7-3, 7-13,
7-38, 8-39, 8-73, 8-82, 8-92, 8-93, 9-12,
15-65
auAlfToDB command 16-4
auDumpALF command 16-5
auDumpCLF command 9-7, 9-24, 9-25
auECOByChangeFile command 4-27, 12-22,
12-23, 12-24
auECOByNetCmp command 12-22, 12-24
auEDIFIn command 4-8
auEdifOut command 13-17
auExtractBlockagePinVia command 3-17,
14-8
auGenCellBndry command 14-8
auLoadCLF command 3-23, 3-29, 3-40, 13-17
auNDOApi command 13-18
auNLOApi command 13-18
auPurgeSIOfALF command 16-5
auSetPRBdry command 3-19, 3-42, 14-8
auStreamIn command 3-16, 14-8
auStreamOut command 13-18
auto_place command 8-4
auVerilogIn command 4-14
auVerilogOut command 13-17
IN-3
auVerilogToCell command 4-2, 4-14, 4-15

auVhdlOut command 13-18
axComputeHierAntennaProp command 14-7
axDrouteOptimizeContact command 12-6
axgAddDiodeForPreroute command 14-9
axgAddFillerCell command 8-48, 8-49
axgAddFillerCellByArea command 8-48
axgAddRouteGuide command 10-10
axgAdvRouteOpt command 7-29, 7-41, 11-21,
15-56
axgAssignToTracks command 10-48
axgAutoRoute command 10-3, 10-25, 10-26
axgAutoShieldRoute command 10-40, 10-41,
15-13
axgBindNetlist command 4-15
axgCheckDesignForRoute command 6-5,
10-6
axgCreateRectangularRings command 5-10
axgCreateRegion command 8-11
axgCreateStraps command 5-14, 5-18
axgDefineVarRule command 9-6, 9-57, 9-75,
10-12, 10-13, 10-41
axgDefineWireTracks command 3-20
axgDeleteDiode command 14-17
axgDetailRoute command 10-48
axgDisplayCouplingCapMap command 8-34
axgDisplayCritAreaHeatMap command 12-19
axgDisplayGRCongestionMap command
10-30
axgDisplayPLCongestionMap command 8-31
axgDisplayScanChain B-9, B-21
axgDumpFloorPlan 5-9
axgDumpPseudoPinConstr command 10-23
axgECOPlace command 8-48
axgECORouteDesign command 9-92, 10-44
axgFillWireTrack command 12-11, 12-12
axgGlobalRoute command 10-46, 10-47
axgInsertDiode command 14-15
axgListPRSummary command 7-25
IN-4
axgLoadPLCongMap command 8-33

axgLoadPseudoPinConstr command 10-22
axgOptimizeContact command 12-7
axgPlaceOptions command 8-9
axgPlanner command 5-6, 5-8
axgPrerouteInstances command 5-18
axgPrerouteStandardCells command 5-18
axgQuickSignalRoute command 10-40, 10-42,
12-20, 15-13
axgRouteGroup command 9-58, 10-23
axgRouterVerify command 13-6
axgRoutOpt command 10-38
axgSavePLCongMap command 8-33
axgScanChainOptim command B-9, B-14,
B-19
axgScanTrace command B-7
axgSearchRepair command 10-50, 14-12
axgSetHPORouteOptions command 14-13,
15-59
axgSetMinMaxLayer command 9-6
axgSetNetConstraint command 9-6, 9-57,
9-75, 10-12, 10-15, 10-16
axgSetRouteOptions command 9-74, 10-18,
10-32, 10-39, 15-11
axgSlotWire command 12-14
axgSpreadGroupCells command 8-47
axgUpdateCongMap command 8-32, 8-33,
8-66
axImportAntennaReport command 14-8,
14-18
axPrintParams command D-2
axReportAntennaRatio command 14-18
axReportIsolatedVia command 12-10
axRouteAddBufferByFile command 12-22
axSearchParams command D-3
axSetIntParam command
act 9-56, 9-58
acts 9-48, 9-57, 9-66, 9-94
apl 6-34
ata 7-47, 8-45
droute 10-36, 10-37, 10-39, 10-40, 11-3,

12-4, 12-5, 12-6, 12-10, 12-11, 12-12,
12-16, 14-11, C-16, C-27
groute 10-28, 10-29, 10-32, 10-33
pds 6-36, 7-36, 8-84, 8-86, 8-102, 8-103,
11-5, 11-7
place 8-15, 8-20, 8-22, 8-56
preroute 5-18
route 10-9
trackAssign 10-34, 10-35
xt 15-16, 15-17
axSetRealParam command
acts 9-48
droute 12-5
ek 7-40, 7-41, 7-43
xt 15-50
axShowParams command D-3
B
back-annotation
data exchange formats, list of 13-17
RC and delay output formats, list of 13-18
balance_inter_clock_delay command 9-6
begin_scheme command 2-8
begin_tcl command 2-7
block, defined GL-1
blockage, defined GL-1
buffer tree, inserting for each high-fanout net
9-109
buffers
clock tree (delay cells) 9-36
defining for clock tree synthesis 9-30
dummy cells are, clock tree 9-37
nonclock nets, asynchronous 8-65
relocation, clock tree 9-79
setting level for clock tree 9-43
sizing, clock tree 9-78
C
capacitance, settings for clock tree 9-43
capacitance, TLU model
checking parameters 7-41
setting 4-9, 6-38, 6-41
capacitance, TLUPlus model
about 7-43
generating 7-44
writing information to an ASCII file 7-46
case analysis, setting an operating condition
6-7
cell electromigration
about 16-3
performing analysis 16-28
cell instance groups, adding to a scan chain
B-15
cell sizing, clock tree optimization 9-33
cells
creating new 2-26
displaying in a layout window 2-27
legalized, defined GL-3
opening existing 2-23
spare, defined GL-4
using edit-in-place 12-28
cells, filler
adding 8-48
adding back after optimization 11-18
defined GL-2
removing 10-8
cells, tie-high, tie-low, and tie-highlow
examples 8-57
inserting 8-52
modes 8-55
check_design_for_cts command 9-7
CLF (Cell Library Format) files
about 3-2
antenna requirements 3-40, 14-6
clock tree synthesis 9-7
constraints for noise analysis 15-20
loading supplemental 3-40
clfCreateTable command 9-8
IN-5
clock browser, using to view clock structures

9-14
clock domains, setting capacitance, transition,
and delay defaults 6-60
clock gating
defining cell 9-25
setting option for 9-49
clock groups, optimizing 8-43
clock latency
about 9-48
settings for 9-11
clock nets
routing as a group 9-114, 10-22
setting variable routing rules for 10-12
clock network analysis, non-unate 7-47
clock path
clear from graphics window 7-10
color, clock browser 9-16
display from clock list, clock browser 9-16
display in graphics window 7-10
full, clock browser 9-16
show in timing report 7-10
view details of between the master and the
generated clocks 7-10
clock signal, distributing 9-62
clock sink
identifying 9-24
setting as fixed 9-54
clock skew
analysis 9-96
minimizing 9-64
minimizing local 9-68
optimizing useful 9-85
reporting 9-5
clock structures
view all 9-16
clock transition
about 9-48
setting default values at the clock pins 6-58
settings for 9-12
clock tree
buffer relocation 9-79
IN-6
buffer sizing 9-78

checking data in the design 9-12
constraints for 9-43
deleting 9-59
dummy cells 9-37
ECO 9-94
gate relocation 9-80
gate sizing 9-80
ignore pins 9-28
interactive changes 9-96
parameter settings 9-47
propagating special routing rules 9-56
reporting power consumption for 9-111
root 9-20
starting point 9-20
stop pins 9-28
top-level designs 9-73
clock tree configuration file
hard 9-39
soft 9-39
syntax 9-40
clock tree optimization
cell sizing 9-33
choosing mode 9-75
clearing and resetting attributes 9-76
command to run 9-77
delay insertion 9-82
level adjustment 9-81
reconfiguration 9-81
clock tree postrouting optimization
about 9-90
command to run 9-91
choosing building style 9-60
command to run 8-38
defining buffers, inverters 9-30
design preparation 9-9
library setup 9-7
setting common options for 8-36, 9-18
warning message for routed clocks 9-59
clocks
balancing delays 9-83
multiple 9-67
pulse generated 9-26
cluster, defined GL-2
cmAttachStarRCXT command 11-26
cmCmdECODump command 12-24
cmCmdExpand command 4-14
cmCreateCapModel command 3-4, 4-9, 6-38,
6-41, 7-42, 7-44
cmCreateLib command 3-15, 3-25
cmDumpTech command 3-42
cmDumpTLUPlus command 7-46
cmItfToTLUPlus command 4-9, 7-44
cmMarkLefSite command 3-42
cmRefLib command 3-25
cmReplaceTech command 3-7, 3-42
cmReplaceTLUPlus command 7-46
cmSetMultiHeightProperty command 3-20,
3-42
cmSmash command 3-17, 3-27
command files
creating and running 2-35
load 2-38
replay 2-36
script 2-39
startup
about 2-37
application 2-37
library 2-38
command menu, using 2-10
command processing, interrupting 2-9
command window, using 2-13
commands
aprAddGroupBySelSet 8-47
aprCmdCreateHierGroup 8-47
aprCmdFixCell 8-47
aprCreateGCTSExplorer 9-66
aprPGConnect 4-15, 5-2, 11-18
aprSetDensity 8-71
astAddPlaceSRConst 8-70
astAreaRecovery 8-103
astAutoPlace 8-3, 8-4, 8-17, 8-22, 8-40,

15-7
astCapFix 8-93
astChangeNetlist 7-23, 12-22
astCheckDesign 6-4, 7-32, 7-33, 7-39, 8-64
astCheckDesignForCTS 6-4, 9-5, 9-12
astCheckHierPresConsistency 4-28
astClearDesignLEQ 3-39
astClockBrowser 9-5, 9-14
astClockOptions 8-36, 8-37, 9-5, 9-9, 9-18
astClockTiming 9-5, 9-100
astCTO 9-5, 9-9, 9-58, 9-68, 9-76, 9-77
astCTOInterClocksBalance 9-5, 9-83, 9-84
astCTS 8-38, 9-5, 9-9, 9-49, 9-58, 9-61,
9-63, 9-69, 9-72, 9-73, 9-74, 9-75, 9-110
astCTSBasic 9-5, 9-49
astDeleteClockTree 9-5, 9-58
astDeleteHierPreservation 4-28
astDesignRules 8-82, 8-89, 8-91, 8-93
astDSPFOut 13-19
astDumpAttachedDesignLEQFile 3-40
astDumpDesignLEQ 3-39
astDumpHFN 8-65
astDumpHierPreservation 4-28
astDumpHierVerilog 4-16, 4-19, 12-24,
13-18
astDumpLEQ 7-40
astECOCTS 9-5, 9-95, 12-22
astEdit 7-21, 12-22
astExtrLEQ 3-23, 3-36
astFanoutSetup 8-68, 8-88
astFastPlace 6-4, 7-33
astGenPV 13-13, 15-13, 15-52
astHFCTS 9-9, 9-107, 9-109, 9-110
astHoldGenerateCutSet 8-101
astInitHierPreservation 4-15, 4-16, 4-17, 6-6
astLenBI 8-93, 8-94, 12-22
astLoadDesignLEQ 3-38
astLPEOut 13-18
astMagnetPlace 8-14, 8-16
astMarkClockTree 9-5, 9-54, 9-56, 9-57,
9-59, 9-67, 9-75, 9-76
IN-7
astMarkHierAsPreserved 4-15, 4-18, 5-2

astPath 7-10
astPathClear 7-10
astPlaceArea 8-67, 8-71
astPlaceDesign 8-66, 8-67
astPlaceOptions 8-71
astPostGR 7-29, 10-32, 11-19
astPostPS 7-29, 8-83, 8-84, 8-85, 8-86
astPostPS1 7-29, 8-78, 15-10
astPostRouteCTO 9-5, 9-9, 9-91
astPostRouteOpt 11-2, 11-4, 11-5, 11-8,
15-53, 15-54
astPostRT 7-29, 7-41, 11-21, 11-24
astPowerRecovery 8-35, 11-15, 11-16
astPrePS 8-58, 8-59, 8-63
astRepairHierPreservation 4-16, 4-23, 4-24,
4-25, 12-23, 12-24
astReportClockTreePower 9-6, 9-111, 9-112
astReportTiming 7-3, 15-22, 15-44, 15-46,
15-48
astSearchRefine 8-67, 8-69, 8-70
astSetCellInstDontTouch 9-10
astSetClockCell 9-10, 9-29, 9-30, 9-31,
9-35, 9-37, 9-39, 9-79, 9-80, 9-82, 9-83
astSetDelayCell 8-98, 8-100, 9-10, 9-36,
9-37, 9-82
astSetDontTouch 9-9, 9-10
astSetDontUse 9-9, 9-10, 11-8
astSetSizeOnly 8-20
astSkewAnalysis 9-5, 9-102, 9-104, 9-108
astSPEFOut 13-19
astSPICEOut 13-19
astSplitClockNet 9-5, 9-9
astStarRCXT 6-41
astSynNetSkewReport 9-107, 9-108
astTimingDataCheck 6-3, 7-30, 7-37
astTimingModel 13-15
astTimingProbe 7-11
astTopoHold 8-96, 8-97, 8-98
astTopoTransCap 8-91, 8-92, 8-93
astTransFix 8-93
astWriteDC 6-14, 8-20
IN-8
astXTalkFix 15-60, 15-61

ataDefineIgnorePin 9-11
ataDefineSyncPin 9-8, 9-11, 9-22, 9-23,
9-24
ataDefineSyncPort 9-8, 9-22, 9-23, 9-24
ataDisableIdealNetworkDelay 6-30
ataDumpClockNets 10-13
ataDumpPropagatedMaxCap 6-61
ataDumpSDC 9-9, 9-10
ataDumpSDF 13-19, 15-50
ataEnableIdealNetworkDelay 6-30
ataLoadSDC 6-9, 6-13, 6-14, 7-36, 7-37,
9-111
ataPurgeDBUsefulSkew 9-72
ataRemoveMaxCapBoundPort 6-61
ataRemoveMaxCapClockData 6-61
ataRemoveTC 6-13
ataSetAndPropagateMaxCapBoundPort
6-60
ataSetAndPropagateMaxCapClock 9-10,
9-44
ataSetAndPropagateMaxCapClockData
6-61
ataSetAndPropagateMaxTransClock 9-5,
9-10, 9-44
ataSetDisableTiming 7-31
ataSetNetCapTransAndDelayTime 6-11,
6-63, 6-64, 8-63, 8-65, 9-10, 9-12
ataSetTimeBorrowMethod 6-22
ataWriteTC 6-11, 6-12, 6-18, 8-65
atTimingSetup 6-19, 7-3, 7-13, 7-38, 8-39,
8-73, 8-82, 8-92, 8-93, 9-12, 15-65
auAlfToDB 16-4
auDumpALF 16-5
auDumpCLF 9-7, 9-24, 9-25
auECOByChangeFile 4-27, 12-22, 12-23,
12-24
auECOByNetCmp 12-22, 12-24
auEDIFIn 4-8
auEdifOut 13-17
auExtractBlockagePinVia 3-17, 14-8
auGenCellBndry 14-8
auLoadCLF 3-23, 3-29, 3-40, 13-17
auNDOApi 13-18
auNLOApi 13-18
auPurgeSIOfALF 16-5
auSetPRBdry 3-19, 3-42, 14-8
auStreamIn 3-16, 14-8
auStreamOut 13-18
auto_place 8-4
auVerilogIn 4-14
auVerilogOut 13-17
auVerilogToCell 4-2, 4-14, 4-15
auVhdlOut 13-18
axComputeHierAntennaProp 14-7
axDrouteOptimizeContact 12-6
axgAddDiodeForPreroute 14-9
axgAddFillerCell 8-48, 8-49
axgAddFillerCellByArea 8-48
axgAddRouteGuide 10-10
axgAdvRouteOpt 7-29, 7-41, 11-21, 15-56
axgAssignToTracks 10-48
axgAutoRoute 10-3, 10-25, 10-26
axgAutoShield 10-40, 10-41, 15-13
axgBindNetlist 4-15
axgCheckDesignForRoute 6-5, 10-6
axgCreateRectangularRings 5-10
axgCreateRegion 8-11
axgCreateStraps 5-14, 5-18
axgDefineVarRule 9-6, 9-57, 9-75, 10-12,
10-13, 10-41
axgDefineWireTracks 3-20
axgDeleteDiode 14-17
axgDetailRoute 10-48
axgDisplayCouplingCapMap 8-34
axgDisplayCritAreaHeatMap 12-19
axgDisplayGRCongestionMap 10-30
axgDisplayPLCongestionMap 8-31
axgDisplayScanChain B-9, B-21
axgDumpFloorPlan 5-9
axgDumpPseudoPinConstr 10-23
axgECOPlace 8-48
axgECORouteDesign 9-92, 10-44
axgFillWireTrack 12-11, 12-12
axgGlobalRoute 10-46, 10-47
axgInsertDiode 14-15
axgListPRSummary 7-25
axgLoadPLCongMap 8-33
axgLoadPseudoPinConstr 10-22
axgOptimizeContact 12-7
axgPlaceOptions 8-9
axgPlanner 5-6, 5-8
axgPrerouteInstances 5-18
axgPrerouteStandardCells 5-18
axgQuickSignalRoute 10-40, 10-42, 12-20,
15-13
axgRouteGroup 9-58, 10-23
axgRouterVerify 13-6
axgRoutOpt 10-38
axgSavePLCongMap 8-33
axgScanChainOptim B-9, B-14, B-19
axgScanTrace B-7
axgSearchRepair 10-50, 14-12
axgSetHPORouteOptions 14-13, 15-59
axgSetMinMaxLayer 9-6
axgSetNetConstraint 9-6, 9-57, 9-75, 10-12,
10-15, 10-16
axgSetRouteOptions 9-74, 10-18, 10-32,
10-39, 15-11
axgSlotWire 12-14
axgSpreadGroupCells 8-47
axgUpdateCongMap 8-32, 8-33, 8-66
axImportAntennaReport 14-8, 14-18
axPrintParams D-2
axReportAntennaRatio 14-18
axReportIsolatedVia 12-10
axRouteAddBufferByFile 12-22
axSearchParams D-3
axSetIntParam
act 9-56, 9-58
acts 9-48, 9-57, 9-66, 9-94
apl 6-34
ata 7-47, 8-45
droute 10-36, 10-37, 10-39, 10-40, 11-3,
12-4, 12-5, 12-6, 12-10, 12-11, 12-12,
12-16, 14-11, C-16, C-27
groute 10-28, 10-29, 10-32, 10-33
IN-9
pds 6-36, 7-36, 8-84, 8-86, 8-102, 8-103,

11-5, 11-7
place 8-15, 8-20, 8-22, 8-56
preroute 5-18
route 10-9
trackAssign 10-34, 10-35
xt 15-16, 15-17
axSetRealParam
acts 9-48
droute 12-5
ek 7-40, 7-41, 7-43
xt 15-50
axShowParams D-3
balance_inter_clock_delay 9-6
begin_scheme 2-8
begin_tcl 2-7
check_design_for_cts 9-7
clfCreateTable 9-8
cmAttachStarRCXT 11-26
cmCmdECODump 12-24
cmCmdExpand 4-14
cmCreateCapModel 3-4, 4-9, 6-38, 6-41,
7-42, 7-44
cmCreateLib 3-15, 3-25
cmDumpTech 3-42
cmDumpTLUPlus 7-46
cmItfToTLUPlus 4-9, 7-44
cmMarkLefSite 3-42
cmRefLib 3-25
cmReplaceTech 3-7, 3-42
cmReplaceTLUPlus 7-46
cmSetMultiHeightProperty 3-20, 3-42
cmSmash 3-17, 3-27
compile_clock_trees 9-6
connect_tie_cells 8-52, 8-54
create_clock 9-60
create_design 2-26
create_generated_clock 9-26, 9-62
ctiCTS 9-6, 9-96, 9-97
dbAddAntennaLayerRule 14-14
dbAddFixedEdgeToScanChain B-13, B-15
IN-10
dbAddFreeEdgeToScanChain B-12, B-13,

B-15
dbAddInstGroupToScanChain B-13, B-17
dbAssignNetTimingSpacing 15-58
dbAssignVarRouteRule 10-12
dbClearCellFootPrintEQClass 11-17
dbConvertPortToDiodePort 14-8
dbCreateGlobalNetByScanChain B-19
dbCreateScanChain B-12, B-13
dbDefineAntennaRule 14-14
dbDefineIgnorePin 9-28
dbDefineIgnorePort 9-8
dbDefineSyncPin 9-25, 9-26
dbDefineSyncPort 9-25
dbDefineVarRouteRule 10-12
dbDeleteAllVarRouteRules 10-12
dbDeleteScanChain B-13, B-14
dbDumpAllVarRouteRules 10-12
dbDumpFootPrintEQ 11-17
dbDumpScanChain B-11, B-21
dbDumpScanPortPairs 8-47
dbDumpSyncPin 9-26
dbMakeScanChainByCellInst B-6, B-9
dbMakeScanChainByMaster B-6, B-9
dbMarkScanPortPairs 8-47
dbReplaceScanCell B-9
dbSetCellPortTypes 3-17, 3-27, 9-8, 9-9, B-7
dbSetLModeSubType 9-8, 9-25
dbSetNetXtalkAggressorList 15-59
dbSetScanChainDefaultPriority B-13, B-15,
B-16
defineAntennaArea 14-6
defineBooleanFunction 9-8
defineCellDontTouch 9-8
defineCellDontUse 9-8
defineCellMaxCapacitance 9-8
defineCellMaxFanout 9-8
defineCellMaxTransition 9-8
defineClockNetworkTLU 9-8
defineDiodeProtection 14-6, 14-8
defineExtAntennaArea 14-6
defineExtDiodeProtection 14-6
defineExtGateSize 14-6
defineFlipFlopFunction 9-8
defineFootPrintEQCell 11-17
defineGateSize 14-6
defineHierAntennaProp 14-7
defineLatchFunction 9-8
definePad 3-40
definePortCapacitance 9-8
defineStaticNoiseMargin 15-20
defineStaticNoiseWidth 15-20
defineStroke 2-41
defineTimingTLU 9-8, 9-24
disableStroke 2-41
ekDeleteNetRoutingRuleTabInfo 10-8
ekDumpNetRoutingRuleTabInfo 10-8
ekGenNetRoutingRuleTabInfo 10-7
ekGenVRCCMapAttachFile 8-33
ekIgnoreShieldNDRinDR 10-42
ekSetLayerScope 7-42
ekSetMaxIntraCapDistRatio 7-42
ekSetTLUPlus 7-45
geAdvDRC 13-3
geConfirmCloseLib 2-40
geCreateCell 2-26, 4-15
geCreateLib 3-7
geCreateLogicView 4-31
geErrorBrowser 10-6, 13-9
geGetEditCell 7-33
geMove GL-2
geNameSelect 2-40
geNewDRC 13-5
geNewFillNG 10-40
geNewLVS 13-8
geNewMakeMacro 3-27
geOpenCell 2-23, 5-2
geOpenLib 2-22, 3-20, 5-2
gePrepLibs 3-21, 3-29, 3-30, 3-31, 3-33
geQueryNetConstraint 10-12
geSaveAllOpenCells 6-64
grdgenxo -itf2TLUPlus 7-44
group_path 8-43
help 2-21
hmiHierAntenna 14-7
jpParallelJob 10-53
leaPointToPointRoute 12-29
load 2-36, 2-38
load_scheme 2-39
mark_clock_tree 9-6
menuQuit 2-40
menuReload 4-9
open_design 2-23
open_mw_lib 2-22
optimize_clock_tree 9-6
pdsCROptimization 8-86, 8-87
pdsHFNCollapse 7-36
pdsHFNOptimization 8-65, 8-91
pdsHFNOptNet 8-63, 9-29
pdsMoveCell 8-86, 8-87
pdsMoveIOPaths 8-86
pdsSplit3StateNet 8-87
poLoadNetSwitchingInfo 9-111, 16-8, 16-9,
16-11
poLoadPowerSupply 4-30, 9-111, 15-19,
16-7
poPowerAnalysis 9-111
post_route_opt 11-2
process_particle_probability_file 12-17
read_lib 3-11, 3-25
remove_clock_sense 7-48
remove_clock_tree 9-6
remove_clock_tree_exceptions 9-7
remove_dynamic_latch 6-57
report_clock 9-27
report_critical_area 12-17
report_path_group 8-45
report_timing 7-10
report_units 6-18
route_spreadwire 12-16
rsh 10-55
set_case_analysis 6-7
set_clock_sense 7-47
set_clock_transition 6-58
set_clock_tree_exceptions 9-7, 9-22
set_clock_tree_options 9-6
IN-11
set_clock_tree_references 9-7
set_data_check 6-26
set_drivng_cell 15-19
set_dynamic_latch 6-56
set_max_capacitance 6-62
set_noise_lib_pin 15-24
set_propagated_clock 6-6, 7-5
set_si_analysis 15-17
set_si_delay_analysis 15-18
set_units 6-17
setSideButton 2-32
source 2-36, 2-39
split_clock_net 9-7
tdfSetPowerSupply 16-7
trPanel 12-31
undefineStroke 2-43
unitMaxThickness 14-8
unitMinThickness 14-8
unitNomThickness 14-8
useful_skew_opt 9-7, 9-85
write_mdb 3-43
write_sdc 6-6, 6-18
xtCellEM 16-3, 16-28, 16-29
xtDefineXtalkConxGroup 6-54
xtDumpDeltaTransDelay 15-45, 15-46
xtDumpStageDelay 15-44
xtGetXtalkFilter 6-50
xtIgnoreTieHighLowNet 15-17
xtReportNoiseLibInfo 15-22
xtSignalEM 16-3, 16-4, 16-7, 16-13, 16-23
xtXTalkAnalysis 7-3, 15-27, 15-53
xtXTalkDisplayNet 15-43
xtXTalkReport 15-36
common graph data
loaded and reloaded by the clock browser
9-15
not refreshed by the clock browser 9-16
compile_clock_trees command 9-6
configuration file
hard 9-39
soft 9-39
syntax 9-40
IN-12
congestion
fixing with search-and-refine 8-67
placement cleanup of 8-61
routing and placement 8-29
congestion maps
about 8-28
global routing, displaying 10-30
placement
displaying 8-31
saving and restoring 8-33
updating 8-32
connect_tie_cells command 8-52, 8-54
constraints
about loading timing (SDC) 6-6
backward compatibility (SDC) 6-13
check timing (SDC) 7-36
clock tree 9-43
command to load timing (SDC) 6-9
generate crosstalk 15-28
modifying (SDC) 6-12
timing flow 6-7
writing to a file 6-11
constraints, scan chains
applying to B-19
creating a file B-13
editing the file B-14
sample file B-16
specifying order B-10
contacts, optimizing
about 12-3
using axDrouteOptimizeContact 12-6
using axgOptimizeContact 12-7
control nets, creating for a scan chain B-19
control panel, using 12-31
core area, defined GL-2
coupling capacitance maps
displaying 8-34
generating 8-33
CPUs, distributed routing 10-52, 10-53, 10-55
create_clock command 9-60
create_design command 2-26
create_generated_clock command 9-26, 9-62

critical areas
displaying heat maps 12-19
encrypting and decrypting the particle
probability function 12-17
reporting heat maps 12-17
spreading wires 12-16
crosstalk
about 15-2
constraints 15-28
filtering mechanisms, list of 6-49
generating timing reports 15-48
optimization during search-and-repair
routing 15-62
reporting filtering thresholds 6-50
running noise-induced delay shift 15-47
setting aggressor and electrical filters 6-46
setting circuit model 6-49
setting global thresholds 6-48
setting timing setup options 15-14
crosstalk analysis
displaying results of 15-43
generating reports 15-36
sample report 15-38, 15-40
specifying power supply 15-18
using the low-effort crosstalk circuit model
15-25
using the medium-effort crosstalk circuit
model 15-26
crosstalk circuit models
about low effort 15-64
about medium effort 15-66
differences between 15-63
using low effort for analysis 15-25
using medium effort for analysis 15-26
crosstalk fixing
about 15-52
using astPostRouteOpt 15-53
using astXTalkFix 15-60
using axgAdvRouteOpt 15-56
using spacing and isolation constraints 15-58
crosstalk noise analysis

about 15-13
command to run 15-27
excluding nets from 15-17
reporting noise information from reference
libraries 15-22
setting CLF constraints 15-20
using noise library information 15-20
crosstalk parameters D-76
crosstalk prevention
during global routing 15-12
during in-placement and postplacement
optimization 15-7
during postplacement optimization phase 1
15-10
during track assignment 15-12
setup 15-11
shielding nets 15-13
ctiCTS command 9-6, 9-96, 9-97
D
data exchange output formats, list of 13-17
data preparation
creating LM views 3-29
data preparation, design
about generating hierarchical Verilog out
4-11
dynamic latch analysis 6-55
loading power supply information 4-29
loading SDC 6-6
preserving hierarchy 4-12
setting capacitance constraints on clock
domains 6-60
setting capacitance, transition, and delay
defaults for nets 6-63
setting clock transition defaults 6-58
setting net transition defaults for nonclock
nets 6-59
timing setup 6-19
data preparation, library
IN-13
creating logical equivalent cell information

3-35
loading supplemental CLF 3-40
database, Milkyway
about 3-2
dbAddAntennaLayerRule command 14-14
dbAddFixedEdgeToScanChain command
B-13, B-15
dbAddFreeEdgeToScanChain command B-12,
B-13, B-15
dbAddInstGroupToScanChain command
B-13, B-17
dbAssignNetTimingSpacing command 15-58
dbAssignVarRouteRule command 10-12
dbClearCellFootPrintEQClass command
11-17
dbConvertPortToDiodePort command 14-8
dbCreateGlobalNetByScanChain command
B-19
dbCreateScanChain command B-12, B-13
dbDefineAntennaRule command 14-14
dbDefineIgnorePin command 9-28
dbDefineIgnorePort command 9-8
dbDefineSyncPin command 9-25, 9-26
dbDefineSyncPort command 9-25
dbDefineVarRouteRule command 10-12
dbDeleteAllVarRouteRules command 10-12
dbDeleteScanChain command B-13, B-14
dbDumpAllVarRouteRules command 10-12
dbDumpFootPrintEQ command 11-17
dbDumpScanChain command B-11, B-21
dbDumpScanPortPairs command 8-47
dbDumpSyncPin command 9-26
dbMakeScanChainByCellInst command B-6,
B-9
dbMakeScanChainByMaster command B-6,
B-9
dbMarkScanPortPairs command 8-47
dbReplaceScanCell command B-9
IN-14
dbSetCellPortTypes command 3-17, 3-27, 9-8,

9-9, B-7
dbSetLModeSubType command 9-8, 9-25
dbSetNetXtalkAggressorList command 15-59
dbSetScanChainDefaultPriority command
B-13, B-15, B-16
defineAntennaArea command 14-6
defineBooleanFunction command 9-8
defineCellDontTouch command 9-8
defineCellDontUse command 9-8
defineCellMaxCapacitance command 9-8
defineCellMaxFanout command 9-8
defineCellMaxTransition command 9-8
defineClockNetworkTLU command 9-8
defineDiodeProtection command 3-40, 14-6,
14-8
defineExtAntennaArea command 14-6
defineExtDiodeProtection command 14-6
defineExtGateSize command 14-6
defineFlipFlopFunction command 9-8
defineFootPrintEQCell command 11-17
defineGateSize command 3-40, 14-6
defineHierAntennaProp command 14-7
defineLatchFunction command 9-8
definePad command 3-40
definePortCapacitance command 9-8
defineStaticNoiseMargin command 15-20
defineStaticNoiseWidth command 15-20
defineStroke command 2-41
defineTimingTLU command 9-8, 9-24
delay cells
balancing 9-83
defining for delay balance 9-36
delay shift, noise-induced 15-47
delay, settings for clock tree 9-43
design data preparation
about generating hierarchical Verilog out
4-11

loading power supply information 4-29
loading SDC 6-6
preserving hierarchy 4-12
setting capacitance constaints on clock
domains 6-60
defaults for nets 6-63
setting clock transition defaults 6-58
setting net transition defaults for nonclock
nets 6-59
timing setup 6-19
design data, checking 6-3
design database file, about 3-3
design finishing
metal density filling 12-11
wide metal slotting 12-14
design flow, Astro
detailed A-1
overview 1-7
design LEQ
defined 3-35
using 3-37
verifying 3-39
design library
adding TLU or TLUPlus capacitance tables
4-8
creating with a Verilog netlist 4-2
creating with a VHDL or EDIF netlist 4-8
data requirements for 3-5
design rule support
filling notches and gaps 10-39
preventing isolated 12-10
design rules, routing
dog bone C-24
enclosed via spacing C-20
fat contact C-13
fat poly contact C-12
fat wire via keepout region C-33
jog wire C-31
merging pins with abutting obstruction C-16
metal density C-21
minimum edge C-3

minimum enclosed area C-11
minimum length C-3
neighboring layer fat extension range
spacing C-28
parallel length C-30
protrusion length C-25
same net minimum spacing C-23
special end-of-line spacing C-16
U-shape spacing C-10
via array (via farm) C-23
via array maximum stack level C-27
via corner spacing C-9
design units
checking consistency 6-18
reporting information about 6-18
specifying in SDC file 6-17
writing out information 6-18
detail routing
about 10-36
command to run (alternative) 10-48
handling off-grid routing and off-grid pins
10-36
optimization 11-14, 11-21
reducing wire length and via count 10-38
running ECO 10-44
die area, defined GL-2
diodes
deleting 14-17
inserting on preroute nets 14-9
inserting to fix antenna violations 14-15
preparing 14-8
disableStroke command 2-41
distibuted routing
about 10-52
choosing JP 10-54
choosing LSF 10-54
connection errors 10-55
initializing 10-53
dont touch and dont use, setting 9-9
DRC
IN-15
about 13-2
cleaning up errors 12-20
defined GL-2
fixing problems across the hierarchy 12-28
running advanced 13-3
running basic 13-5
running with verification 13-6
DRC errors, displaying in browser 10-6, 13-9
E
ECO
change file method 12-23
clock tree changes 9-94
generating during scan chain optimization
B-19
methods, list of 12-22
net compare method 12-24
running after postrouting clock tree
optimization 9-92
running on detail routing 10-44
updating netlist changes 4-24
EDIF netlist, creating a design library with 4-8
editing, interactive 7-21
edit-in-place 12-28
ekDeleteNetRoutingRuleTabInfo command
10-8
ekDumpNetRoutingRuleTabInfo command
10-8
ekGenNetRoutingRuleTabInfo command 10-7
ekGenVRCCMapAttachFile command 8-33
ekIgnoreShieldNDRinDR command 10-42
ekSetLayerScope command 7-42
ekSetMaxIntraCapDistRatio command 7-42
ekSetTLUPlus command 7-45
electrical filters, crosstalk
list of 6-50
setting 6-46
electromigration
about 16-3
IN-16
loading net switching information for analysis

16-8
loading power supply for analysis 16-7
performing cell analysis 16-28
performing signal analysis 16-13
preparing data for analysis 16-4
sample scripts 16-37
signal analysis repair file 16-23
signal analysis report 16-17
verifying analysis results 16-24
Environment page, timing setup 6-20
extraction, parasitic layout
determining mode 7-41
fast 11-25
in-routing 11-21, 15-62
setting mode for 6-40
setting mode for signal electromigration
analysis 16-13
using a net-based routing rule table 10-7
extraction, parasitic, Star-RCXT 4-9
F
falling edge, clock tree 9-9
fanout nets, high
about 8-63
buffering of 8-62
optimization, in-placement 8-68
optimization, preplacement 8-62
reporting skew for non-clock 9-107
setting maximum for clock tree 9-43
synthesizing 9-109
files
ALF (Advanced Library Format) 16-4, 16-30
CLF (Cell Library Format) 3-2
design database 3-3
GDSII 3-3
netlist 3-3
output from Astro, list of types 3-6
.rhost 10-55
SDC 3-3
SDF (Standard Delay Format) 15-50
SPEF (Standard Parasitic Exchange Format)

4-27, 13-19
synthesis library 3-4
TDF (Top Design Format) 3-3
technology 3-2
files, command
load 2-38
replay 2-36
script 2-39
startup 2-37
application 2-37
library 2-38
filler cells
adding 8-48
adding back after optimizations 11-18
defined GL-2
removing 10-8
filters, crosstalk
electrical, list of 6-50
parasitic aggressor, list of 6-49
setting 6-46
fixed edges, adding to a scan chain B-16
fixed, defined GL-2
floating wire antennas, checking and fixing
14-11
floorplans
about 5-6
creating 5-6
dumping information 5-9
flyline, defined GL-3
free edges, adding to a scan chain B-16
G
gated clock tree
defining cell 9-25
setting option for 9-49
gates
relocation, clock tree 9-80
sizing, clock tree 9-80
GDSII files, about 3-3
geAdvDRC command 13-3

geConfirmCloseLib command 2-40
geCreateCell command 2-26, 4-15
geCreateLib commmand 3-7
geCreateLogicView command 4-31
geErrorBrowser command 10-6, 13-9
geGetEditCell command 7-33
geMove command GL-2
geNameSelect command 2-40
generated clocks, reporting 7-32
geNewDRC command 13-5
geNewFillNG command 10-40
geNewLVS command 13-8
geNewMakeMacro command 3-27
geOpenCell command 2-23, 5-2
geOpenLib command 2-22, 3-20, 5-2
gePrepLibs command 3-21, 3-29, 3-30, 3-31,
3-33
geQueryNetConstraint command 10-12
geSaveAllOpenCells command 6-64
global route parameters D-84
global routing
about 10-27
optimization 11-13, 11-19
preventing crosstalk during 15-12
RC layer optimization 10-28
running incremental 10-32
specifying density-driven 10-28
specifying no buffer zone 10-29
global routing congestion maps, displaying
10-30
grdgenxo -itf2TLUPlus command 7-44
group_path command 8-43
groups, adding to a scan chain B-15
GUI
creating cells 2-26
exiting an Astro session 2-39
opening existing cells 2-23
IN-17
opening existing library 2-22

starting an Astro session 2-4
using menu commands 2-10
working with layout windows
command history buttons 2-30
context view and information bar 2-33
displaying a cell 2-27
making current 2-34
navigation buttons 2-28
opening multiple 2-34
opening the same cell in multiple 2-27,
2-35
selecting and editing buttons 2-31
H
hard blockage, defined GL-1
help command 2-21
Help, online, using the Web browser 2-18
Hercules, importing antenna reports from
14-18
hierarchical antenna properties
hard macros 14-5, 14-7
routed blocks 14-7
hierarchical common graph
checking consistency information 4-28
hierarchical Verilog
about outputting 4-11
dumping information 4-19, 4-28
hierarchy preservation
about 4-12
deleting 4-28
initializing 4-16
maintaining information during ECO 12-23
marking instances 4-18
methodology for 4-14
repairing 4-23
high-fanout nets
about 8-63
buffering of 8-62
optimization, in-placement 8-68
optimization, preplacement 8-62
IN-18
reporting skew for non-clock 9-107

synthesizing 9-109
histogram reports, optimization 11-6
histogram, path timing 7-17
hmiHierAntenna command 14-7
hold time
fixing 8-46
preventing violations B-20
hot spot, defined GL-3
I
ideal slack, preplacement optimization 8-63
in-placement optimization
command to run 8-66
in-routing optimization, running with crosstalk
options enabled 15-56
integer set parameter commands, using and
getting information D-2
interactive editing 7-21
interrupt, commands 2-9
inverter-only optimization 11-7
inverters
clock tree (delay cells) 9-36
defining for clock tree synthesis 9-30
dummy cells are, clock tree 9-37
isolation cell, defined GL-3
ITF (Interconnect Technology Format) 7-44
J
jpParallelJob command 10-53
JupiterXT, working with 5-5
L
latch pairs, reporting master-slave 7-32
latency, clock
about 9-48
settings for 9-11

layers, adjusting metal costs 10-9
layout parasitic extraction
fast 11-25
in-routing 11-21, 15-62
analysis 16-13
layout window
command history buttons 2-30
context view and information bar 2-33
displaying a cell 2-27
making current 2-34
navigation buttons 2-28
opening multiple 2-34
opening the same cell in multiple 2-35
selecting and editing buttons 2-31
leaPointToPointRoute command 12-29
legalized cell, defined GL-3
legalized placement, defined GL-3
LEQ (logically equivalent cell information)
checking 7-40
creating 3-35
design LEQ, defined 3-35
extracting and loading from Boolean
information 3-36
library LEQ, defined 3-35
using design LEQ 3-37
level-shifter cell, defined GL-3
libraries, opening existing 2-22
Library Compiler, called by Astro 3-31
library data preparation
creating LM views 3-29
creating logical equivalent cell information
3-35
loading supplemental CLF 3-40
library inputs, checking 7-39
library LEQ, defined 3-35
Library page, timing setup 6-37

library startup files 2-38
library views, list of 3-8
library, design, adding TLU or TLUPlus
capacitance tables 4-8
library, macro cell, creating 3-24
library, standard cell
creating with individual commands 3-15
creating with read_lib 3-11
license
determining availability 2-16
requirements 1-6
LM view
about 3-29
command to create 3-31, 3-33
power supply information 16-7
load command 2-36, 2-38
load files 2-38
load_scheme command 2-39
LOGIC view
about 4-30
command to create 4-31
LSF, choosing 10-54
LVS, running 13-7
M
macro cells, hard, hierarchical antenna
properties 14-5, 14-7
man pages 2-22
mark_clock_tree command 9-6
menu commands, using 2-10
menuQuit command 2-40
menuReload command 4-9
metal slotting 12-14
Milkyway application directory
CLF (Cell Library Format) files 3-2
design database file 3-3
GDSII files 3-3
IN-19
netlist files 3-3

SDC file 3-3
synthesis library file 3-4
TDF (Top Design Format) files 3-3
technology files 3-2
Milkyway database, about 3-2
Milkyway library directory
about 3-6
library information file 3-7
library views 3-8
Model page, timing setup 6-42
N
net switching information, loading 16-8
netlist files, about 3-3
netlist-defined scan chain optimization flow B-2
netlists
creating a design library with 4-2, 4-8
updating for ECOs B-19
nets
analyzing crosstalk 15-36, 15-43
displaying timing information 7-18
defaults 6-63
setting constraints 10-16
shielding 10-40
NLDM libraries, timing setup 6-37
noise analysis
delay shift 15-47
during routing 15-62
reporting 15-31
sample report 15-33, 15-34
sample statistics 15-30
specifying net-based thresholds with an input
file 6-53
noise analysis, crosstalk
about 15-13
excluding nets from 15-17
IN-20
reporting noise information from reference

libraries 15-22
setting CLF constraints 15-20
using noise library information 15-20
noise libraries, using information for noise
analysis 15-20
non-unate clock network analysis 7-47
notches and gaps, filling 10-39
O
online command help facility 2-8
online documentation system, about 2-17
online Help, using the Web browser 2-18
open_design command 2-23
open_mw_lib command 2-22
operating condition, defined GL-3
operating conditions, case analysis 6-7
optimization
adding back filler cells 11-18
area recovery 8-103
detail routing 11-14, 11-21
global routing 11-13, 11-19
histogram reports 11-6
in-placement 8-66
inverter-only capablility 11-7
netlist-defined scan chains B-2
performing length-based buffer insertion
8-93
postplacement phase 1 8-78
postplacement phase 2 8-83, 8-84
postrouting clock tree 9-90
postrouting command 11-4
preplacement 8-58
scan chains B-19
setting the size_only constraint 8-20
setting the time borrowing method 6-22
topology-based
about 8-74
fixing hold violations 8-96
track assignment 11-14
updating power and ground connections

11-18
user-defined scan chains B-2, B-5
Optimization page, timing setup 6-31
optimization parameters D-116
optimize_clock_tree command 9-6
P
pad orientation, CLF requirements 3-40
PARA view
generating 13-13, 15-13
postrouting optimization 11-5
parameters
crosstalk D-76
global route D-84
optimization D-116
rectilinear D-134
timing D-146
using and getting information D-2
parasitic aggressor filters, crosstalk
list of 6-49
setting 6-46
parasitic extraction, layout
fast 11-25
in-routing 11-21, 15-62
analysis 16-13
Parasitics page, timing setup 6-38
paths
clear from graphics window 7-10
display in graphics window 7-10
display in schematic view 7-19
display information 7-14
show in timing report 7-10
timing probe histogram 7-17
view details of between the master and the
pdsCROptimization command 8-86, 8-87

pdsHFNCollapse command 7-36
pdsHFNOptimization command 8-65, 8-91
pdsHFNOptNet command 8-63, 9-29
pdsMoveCell command 8-86, 8-87
pdsMoveIOPaths command 8-86
pdsSplit3StateNet command 8-87
pin, defined GL-3
pins, displaying timing between 7-17
pitch, defined GL-3
place and route summary report
about 7-25
DRC information 7-29
global routing information 7-27
placement information 7-27
timing and optimization information 7-27
placement
about 8-3
about setting common options 8-9
congestion 8-29
defining sliver areas 8-21
displaying coupling capacitance maps 8-34
generating coupling capacitance maps 8-33
improving by moving cells in an area 8-71
improving with search-and-refine 8-67, 8-69
legalized, defined GL-3
setting the size_only constraint 8-20
timing-driven 8-11
using double-height cells 8-20
using magnets
about 8-14
command to run 8-16
considering net weight constraints 8-15
placement and placement optimization
performing after clock tree synthesis 8-40
performing before clock tree synthesis 8-17
using alternative commands 8-58
placement congestion maps
displaying 8-31
saving and restoring 8-33
updating 8-32
IN-21
placement, data preparation, defining multiple

tiles 3-42
platforms, supported 1-6
point-to-point routing 12-29
poLoadNetSwitchingInfo command 9-111,
16-8, 16-9, 16-11
poLoadPowerSupply command 4-30, 9-111,
15-19, 16-7
poPowerAnalysis command 9-111
port, defined GL-4
post_route_opt command 11-2
postplacement optimization
performing after clock tree synthesis 8-40
performing before clock tree synthesis 8-17
phase 1
about 8-78
command to run 8-78
preventing crosstalk 15-10
phase 2
about 8-83, 8-84
command to run 8-85
postrouting optimization
about 11-2
clock tree 9-90
contacts 12-3
customized flow 11-12
detail 11-14, 11-21
global routing 11-13, 11-19
recommended flow 11-4
running with crosstalk options enabled 15-53
track assignment 11-14
power and ground
adding rings 5-10
adding straps 5-14
connecting 5-2
updating connections 11-18
power and reliablility analysis
IN-22
about Astro-Rail 1-11

about PrimeRail 1-12
design flow for Astro-Rail and PrimeRail 1-13
power consumption, reporting for clock trees
9-111
power optimization
postplacement 8-35
postrouting 11-15
prerouting 8-36
power supply, loading information 4-29, 16-7
preplacement
optimization 8-58
predicting timing 8-63
reporting ideal slack 8-63
prerouting
adjusting RC 7-40
connecting standard cells 5-18
PrimeRail, about 1-12
PrimeTime
fixing crosstalk noise based on input from
15-60
loading same SDC as 6-6
probe
instance timing 7-17
net timing 7-18
path timing 7-14
path timing histogram 7-17
schematic 7-19
timing analyzer 7-12
process, voltage, and temperature (PVT),
setting runtime values 6-37
process_particle_probability_file command
12-17
properties, hierarchical antenna 14-5, 14-7
pseudo pins, defining for balanced-clock
routing 10-22
R
RC and delay output formats, list of 13-18
RC correlation
defined GL-4
prerouting 7-40
RC layer optimization, global routing 10-28
read_lib command 3-11, 3-25
real set parameter commands, using and
getting information D-2
rectilinear parameters D-134
reference library, data requirements for 3-4
region constraint, defined GL-4
remove_clock_sense command 7-48
remove_clock_tree command 9-6
remove_clock_tree_exceptions command 9-7
remove_dynamic_latch command 6-57
replay files 2-36
report_clock command 9-27
report_critical_area command 12-17
report_path_group command 8-45
report_timing command 7-10
report_units command 6-18
reports
clock skew 9-5, 9-96
detailed crosstalk analysis 15-36
ideal slack 8-63
master-slave latch pairs 7-32
noise analysis 15-31
noise information from reference libraries
15-22
place and route summary 7-25
synthesized net skew 9-107
timing 7-3
timing with crosstalk consideration 15-48
resistance, TLUPlus model
about 7-43
considerations 7-45
generating 7-44
.rhosts file 10-55
rings, adding power and ground 5-10
rising edge, clock tree 9-9

route_spreadwire command 12-16
routing
about 10-3
adjusting metal costs for layers 10-9
calculating noise during 15-62
checking the design prior to 10-6
controlling layers for 10-10
removing stubs 10-39
using the automatic command 10-25
using the control panel 12-31
routing, congestion 8-29
routing, design rules
dog bone C-24
enclosed via spacing C-20
fat contact C-13
fat poly contact C-12
fat wire via keepout region C-33
jog wire C-31
merging pins with abutting obstruction C-16
metal density C-21
minimum edge C-3
minimum enclosed area C-11
minimum length C-3
neighboring layer fat extension range
spacing C-28
parallel length C-30
protrusion length C-25
same net minimum spacing C-23
special end-of-line spacing C-16
U-shape spacing C-10
via array (via farm) C-23
via array maximum stack level C-27
via corner spacing C-9
routing, distributed
about 10-52
choosing JP 10-54
choosing LSF 10-54
connection errors 10-55
initializing 10-53
routing, DRC
IN-23
about 13-2
cleaning up errors interactively 12-20
running advanced 13-3
running basic 13-5
running with verification 13-6
routing, ECO
after postrouting clock tree optimization 9-92
on detail 10-44
routing, flow 10-4
routing, groups of nets
about 10-21
clock nets 9-114, 10-22
defining pseudo pins for balanced clock
10-22
routing, guide, defined GL-4
routing, optimization
after detail routing 11-14, 11-21
after global routing 11-13, 11-19
after track assignment 11-14
reducing wire length and via count 10-38
routing, point-to-point 12-29
routing, running LVS checking 13-7
routing, setting common options
about 10-18
crosstalk prevention during global and track
assignment 10-20
timing driven 10-20
routing, variable rules
about 10-11
assigning 10-15
defining 10-13
rsh command 10-55
S
scan chain constraints file
IN-24
creating B-13
editing B-14
scan chains
adding cell instance groups B-15
adding fixed edges B-16
adding free edges B-16
applying constraints B-19
applying order constraints B-10
control nets B-19
creating B-9
creating by extraction B-7
creating manually B-9
defining and optimizing B-2
deleting B-14
detaching B-9
disconnecting 8-46
disconnecting and optimizing 8-46
dumping to a file B-11, B-21
generating an ECO B-19
minimum edge length B-20
netlist-defined B-2
optimizing B-19
setting group priority B-15
user-defined B-5
Scheme
about 2-3
changing mode to Tcl 2-7
command to run script 2-39
setting mode 2-4
script files 2-39
SDC commands
about file 3-3
about loading 6-6
backward compatibility 6-13
checking timing constraints 7-36
command to load 6-9, 6-12
modifying 6-12
specifying units 6-17
timing constraint flow 6-7
writing ast-type to a file 6-14
SDF (Standard Delay Format) files, generating

crosstalk-induced 15-50
search-and-refine
changing placement of cells 8-67
command to run 8-69
search-and-repair
about 10-37
filling notches and gaps 10-39
set_case_analysis command 6-7
set_clock_sense command 7-47
set_clock_transition command 6-58
set_clock_tree_exceptions command 9-7,
9-22
set_clock_tree_options command 9-6
set_clock_tree_references command 9-7
set_data_check command 6-26
set_drivng_cell command 15-19
set_dynamic_latch command 6-56
set_max_capacitance command 6-62
set_noise_lib_pin command 15-24
set_propagated_clock command 6-6, 7-5
set_si_analysis command 15-17
set_si_delay_analysis command 15-18
set_units SDC command 6-17
setSideButton command 2-32
shielding nets
about 10-40
ignoring during detail routing 10-42
preventing crosstalk with 15-13
running with default spacing rules 10-42
running with variable routing rules 10-41
signal electromigration
about 16-3
analysis repair file 16-23
analysis report 16-17
performing analysis 16-13
preparing data for analysis 16-4
sample scripts 16-37
verifying analysis results 16-24

signal integrity
crosstalk 15-1
signal and cell electromigration 16-1
skew
minimizing 9-64
minimizing local 9-68
optimizing useful 9-85
soft blockage, defined GL-1
soft-fixed, defined GL-4
source command 2-36, 2-39
spare cell, defined GL-4
SPEF (Standard Parasitic Exchange Format)
output files 4-27, 13-19
split_clock_net command 9-7
standard cell library
creating with individual commands 3-15
creating with read_lib 3-11
standard cells
distributing spare 8-47
prerouting 5-18
Star-RCXT 4-9, 6-38, 6-41, 7-43
startup files
about 2-37
application 2-37
library 2-38
straps, adding power and ground 5-14
stroke commands, defining and using 2-41
stubs, removing 10-39
Swish-e program 1-xlix
synchronous pins
identifying 9-24
setting as fixed 9-54
synthesis library file, about 3-4
T
Tcl
about 2-3
changing mode to Scheme 2-8
command to run script 2-39
IN-25
setting mode 2-5

Tcl commands, man pages 2-22
TDF (Top Design Format) files
about 3-3
antenna requirements 14-6
tdfSetPowerSupply command 16-7
technology files
about 3-2
antenna data 14-8
tie-high, tie-low, and tie-highlow cells
examples 8-57
inserting 8-52
modes 8-55
tiles, defining multiple for placement 3-42
timing
improving with postplacement optimization
8-83, 8-84
physical optimization 8-64
predicting with preplacement optimization
8-63, 8-64
remapping 8-64
topology-based
about 8-74
timing analysis
checking constraints (SDC) 7-36
checking data 7-30
checking timing and optimization 7-33
using tiiming reports 7-3
timing constraints (SDC)
about loading 6-6
backward compatibility 6-13
command to load 6-9
flow 6-7
modifying 6-12
timing models, creating 13-15
timing parameters D-146
timing probe
displaying net information 7-18
displaying path timing histogram 7-17
IN-26
displaying paths in schematic view 7-19

displaying timing between pins 7-17
displaying timing path information 7-14
using the timing analyzer 7-12
timing reports
about 7-3
command to generate 7-3
generating with crosstalk consideration
15-48
sample 7-7
timing setup
Environment page 6-20
initializing 6-19
Library page 6-37
Model page 6-42
Optimization page 6-31
Parasitics page 6-38
Xtalk page 6-45
timing, clock tree
debugging information 9-14
defining information for synthesis 9-7
timing closure features, list of 9-3
timing-driven mode
placement 8-11
routing 10-20
TLU capacitance model
checking parameters 7-41
setting 4-9, 6-38, 6-41
TLUPlus capacitance model
about 7-43
generating 7-44
TLUPlus resistance model
about 7-43
considerations 7-45
generating 7-44
topology-based optimization
about 8-74
track assignment
about 10-33
limiting net layer length to prevent floating
antennas 10-34
optimization 11-14
specifying density-driven 10-34
transition, clock
about 9-48
settings for 9-12
trPanel command 12-31
reporting for antennas 14-18

running advanced DRC 13-3
running basic DRC 13-5
running DRC and verification 13-6
running LVS checking 13-7
voltage area, defined GL-5
voltage domain, defined GL-5
W
Web browser, using to view online Help 2-18
write_mdb command 3-43
write_sdc command 6-6, 6-18
U
undefineStroke command 2-43
unfixed, defined GL-5
unit tile cell, defined GL-5
unitMaxThickness command 14-8
unitMinThickness command 14-8
unitNomThickness command 14-8
useful skew, optimizing 9-85
useful_skew_opt command 9-7, 9-85
V
variable routing rules
about 10-11
assigning 10-15
defining 10-13
propagating for clock nets 9-56
Verilog netlist, creating a design library with 4-2
VHDL netlist, creating a design library with 4-8
vias, preventing isolated 12-10
views, library, list of 3-8
violations
about DRC 13-2
cleaning up DRC errors and shielding 12-20
displaying in browser 10-6, 13-9
X
Xtalk page, timing setup 6-45
xtCellEM command 16-3, 16-28, 16-29
xtDefineXtalkConxGroup command 6-54
xtDumpDeltaTransDelay command 15-45,
15-46
xtDumpStageDelay command 15-44
xtGetXtalkFilter command 6-50
xtIgnoreTieHighLowNet command 15-17
xtReportNoiseLibInfo command 15-22
xtSignalEM command 16-3, 16-4, 16-7, 16-13,
16-23
xtXTalkAnalysis command 7-3, 15-27, 15-53
xtXTalkDisplayNet command 15-43
xtXTalkReport command 15-36
Y
yield, optimizing
displaying critical area heat maps 12-19
encrypting and decrypting the particle
probability function 12-17
reporting critical area heat maps 12-17
spreading wires 12-16
IN-27
IN-28

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Destination Control Statement

Service Marks (SM)

Astro User Guide, version Z-2007.03

About This Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Astro Licensing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .

Astro Place and Route Flow and Documentation Set . . . . . . . . . .

Astro Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Astro Script-Based Methodology . . . . . . . . .

Power and Reliability Analysis . . . . . . . . . . . . . . . . . . . . . . . .

2. Using the Astro GUI and Command Files

Scheme and Tool Command Language (Tcl) . . . . . . . . . . . . . . . .

Starting an Astro Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Startup Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Menu Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the Command Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Finding Commands in Scheme Mode . . . . . . . . . . . . . . . . . .

Finding Commands in Tcl Mode . . . . . . . . . . . . . . . . . . . . . .

Determining License Availability . . . . . . . . . . . . . . . . . . . . . .

Working With and Without the GUI . . . . . . . . . . . . . . . . . . . .

Online Documentation System . . . . . . . . . . . . . . . . . . . . . . .

Displaying Help in Tcl Mode . . . . . . . . . . . . . . . . . . . . . . . . .

Tcl Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Opening and Creating Libraries and Cells . . . . . . . . . . . . . . . . . .

Opening an Existing Library. . . . . . . . . . . . . . . . . . . . . . . . . .

Opening an Existing Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Working With Layout Windows . . . . . . . . . . . . . . . . . . . . . . . . . . .

Navigating Inside a Layout Window . . . . . . . . . . . . . . . . . . . .

Using the Context View and Information Bar . . . . . . . . . . . . .

Opening Multiple Layout Windows. . . . . . . . . . . . . . . . . . . . .

Making a Layout Window Current . . . . . . . . . . . . . . . . . . . . .

Opening the Same Cell in Multiple Layout Windows . . . . . . .

Creating and Running Command Files . . . . . . . . . . . . . . . . . . . . .

Exiting an Astro Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Defining and Using Stroke Command Sequences . . . . . . . . . . . .

Using Integer and Real Parameters for Astro Operations . . . . . . .

3. Creating Milkyway Reference Libraries

Milkyway File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Output From Astro . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Milkyway Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . .

Milkyway Library Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Creating a Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . .

Creating the Library With the read_lib Command . . . . . . . . .

Creating the Library With the Individual Commands . . . . . . .

Creating a Macro Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Creating LM Views for Timing and Power Analysis . . . . . . . . . . . .

Creating Logical Equivalent Cell Information. . . . . . . . . . . . . . . . .

Extracting and Loading Logical Equivalent Cell

Using Design LEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifying Design LEQ From Multiple Reference

Clearing Design LEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Verifying Design LEQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Loading Pad Orientation, Diode Protections, and

Defining Multiple Tiles for Placement . . . . . . . . . . . . . . . . . . . . . .

4. Creating a Design Library and Adding Data

Creating a Design Library With a VHDL or EDIF Netlist . . . . . . . .

Adding TLU or TLUPlus Capacitance Tables to a

Preserving Hierarchy and Generating Hierarchical

Initializing Hierarchy Preservation . . . . . . . . . . . . . . . . . . . . .

Marking Module Instances As Preserved . . . . . . . . . . . . . . .

Generating Hierarchical Verilog . . . . . . . . . . . . . . . . . . . . . . .