International Journal of Emerging Technologies and Engineering (IJETE)

Volume 1 Issue 10, November 2014, ISSN 2348 8050

IMPLEMENTATION OF PACKET CLASSIFICATION

ALGORITHM USING VHDL
Evangeline Asha B1, Kavitha S2
1

PG Scholar, Hindusthan Institute of Technology, Tamil Nadu, India

Professor, Hindusthan Institute of Technology Tamil Nadu, India

ABSTRACT
Packet classification is one of the most important
tasks by the networking equipment. This device is used to
sort the packets. A packet has five fields where these have
to be matched with a rule. The incoming packets are
placed in a flow which is determined by the matched rule.
Packets priority is decided by the matched rule.
Classifying the packet is the difficult task. All the packets
are processed at same speed and the rulesets can contain
ten thousand of rules. The packet classification uses
classification engine that consumes more power. Power is
the major constraint in the networking device. This paper
uses modified hypercut algorithm [1] that consumes only
little amount of power. The software used here helps to
find the amount of memory used as well as the resources
used. This helps to determine the amount of area of the
hardware device that has to be manufactured. This method
avoids the floating point division.
Keywords: classification engine, networking device,
packet priority, rulesets

I.

INTRODUCTION

Packet classification is employed by Internet routers to

implement a number of advanced Internet services, such
as routing, rate limiting, and access-control in firewalls,
virtual bandwidth allocation, policy-based routing, service
differentiation, load balancing, traffic shaping, and traffic
billing. Each of these services require the router to classify
incoming packets into different flows and then perform
appropriate actions depending upon which flow the
incoming packet has been identified to fall into. These
flows or classes, are specified by a classifier. A classifier
is a set of filters or rules. There are more than ten thousand
rules. These rules determine its own action.

II.

PERFORMANCE METRICS OF
PACKET CLASSIFICATION

Search speed Faster links requires faster

classification. For example, links running at 10Gbps can
bring 31.25 million packets per second (assuming
minimum sized 40 byte TCP/IP packets).

Low storage requirements Small storage requirements

enable the use of fast memory technologies like SRAM
(Static Random Access Memory). SRAM can be used as
an on-chip cache by a software algorithm and as on-chip
SRAM for a hardware algorithm.
Ability to handle large real-life classifiers.
Fast updates As the classifier changes, the data
structure needs to be updated. Data structures are
categorized into those which can add or delete entries
incrementally, and those which need to be reconstructed
from scratch each time the classifier changes. When the
data structure is reconstructed from scratch, it is called
pre-processing. The update rate differs among different
applications: a very low update rate may be sufficient in
firewalls where entries are added manually or
infrequently, whereas a router with per-flow queues may
require very frequent updates.
Scalability in the number of header fields used for
classification.
Flexibility in specification A classification algorithm
should support general rules, including prefixes, operators
(range, less than, greater than, equal to, etc.) and
wildcards. In some applications, non-contiguous masks
may be required. [4]

III.

PROBLEMS IN CLASSIFIYING THE

PACKETS

The criteria for classifying packet is called rule R,

and the set of finite rules R1, R2, , Rn contained in
forwarding machine is called rule database or classifier.
The fields of rule and packet header are related, For
example, the rules that implement IPv4 consist of 5 fields
(source IP address, destination IP address, protocol type,
source port, and destination port). The incoming packet to
router matches specific rule if the distinct fields in the
packet match the corresponding fields in that rule.
Since a packet may match more than one rule in
the database, assigning a cost to each rule can avoid this
ambiguity. The packet classification problem is how to
determine the lowest-cost matching for the incoming
packet. The packet must match at least one rule. There are
three matching [7] types.

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International Journal of Emerging Technologies and Engineering (IJETE)

Volume 1 Issue 10, November 2014, ISSN 2348 8050

1. Exact match: The values of rule fields and Packet

header fields must be identical.
2. Prefix match: The rule fields values must be prefix for
the header fields values.
3. Range match: The header fields values must lie in the
range specified by the rule.
IV.

LITERATURE SURVEY

There are many algorithms to classify packets.

Each method consumes different amount of power.
Decision tree based packet classification is one of the
oldest techniques in classifying packets which consumes
about 15 Watts of power. Deep packet inspection
technique consumes about 13.28 Watts of power.
Multidimensional packet classification consumes about 15
Watts to less than 3Watts. Smart pre-classifier technique
uses about 11 Watts of power. Hyper split which is also a
method to classify the packets consume about 12 Watts.
This survey tells that the minimum power consumption is
about 9 Watts and a maximum of 15 Watts.
So this is a major criterion in classifying technique
and has to be reduced.

V.

MODIFIED HYPERCUT ALGORITHM

Read the value from the database

The value of the packet is taken from the database
where the value is stored. For this project, the value is
taken from notepad using readfile command in VHDL
program. With the help of this command, the SIP, DIP,
SP, DP, PRO can be read. Port which provides the detail
of the input and output is given in the program. The input
port includes clock, reset and select. The output port is
declared as y. The clock is given for a particular time
period. At first the reset value is set as 0 and then a change
is given to the value as 1. Even though the total frame bit
is 104, smaller bits are used here for the ease of the project
and hence the width of the SIP and DIP is 8 bit, the SP and
DP is 4 bit and the PRO is 2 bit. Thus the total number of
bit is 26. When reading this file, the total number of bits
will be reduced as 21. In the architecture of the fileread the
variables such as line, string, and character are
declared.EOG has two values such as 0 and 1. When the
value is 0, the value of reset is changed as 1 and 0. The
value to be read is given. If the value is a string, then read
the data else exit the command. If the EOG value is 1, then
end the read file.
Cut selection algorithm
Generic of VHDL which is the parameter that
passes the information to the entity is declared with the
rule width as 7. The input port which is the reset and the
clock is given in the standard logic. The output in general
is given as 8 bit. When the internal architecture of the cut

selection algorithm is considered, the SIP, DIP is 8 bit, SP,

DP is 4 bit. These four frames are taken as
std_logic_vector. This library also suits for the respective
action performed. The library of PRO is declared as
std_logic. After declaring the reset and the clock value, the
OR operation is performed for SIP and DIP, SP and DP
and the PRO is kept the same. Three outputs are obtained
from the above operation such as temp1, temp 2 and
temp3. To get a single output, the OR operation is
performed for three output which is given as y. If the
integer is greater than or equal to rulewidth-1, then the
enable value is 1, else it is 0.
Rule table creation
As usual the reset and the clock value are given.
These are the input to the port. Additionally the index
number is given. Since there are seven rules, the output of
the ports is out1, out 2, out3, out4, out5, out6 and out 7.
Enable value is given. The index values of rule 1, 2,
3,4,5,6 and 7 are 000, 001, 010, 011, 100, 101, and 110
respectively. If the index is 000, then the output is out1. If
its 001, then out2. Similarly for 010, 011, 100, 101, and
110, the corresponding output is out3, out4, out5, out6 and
out 7 respectively. The rule width taken here is 7.
Query feature
Query data is the input data given in the overall
architecture. The integer width of SIP and DIP is 8 bit,
whereas 4 bit for SP and DP, and 2 bit for PRO. The query
data is checked for this bit. If it is not in the specified bit,
then the corresponding codeword is generated and given
as input. Reset and clock is given for all fields. Since the
width of both SIP and DIP are 8, the select value is given
as 00. The width of SP and DP are 4 and its select value is
01. The select value of PRO is 10. The output for each
fields SIP, DIP, SP, DP, PRO are y1, y2, y3, y4, y5
respectively.
Classification engine
The incoming packet is the input to the
classification engine CE. The output of the CE is based on
the state obtained. The states considered here are sawnull,
saw1, saw11, saw110, saw111, saw2, saw3, saw4. The bit
stream is of 8 bit. If reset is 1, then match is 0. If the
corresponding reference data is equal to its corresponding
bit stream, then go to next state, else the next state is
sawnull. When the last state saw 4 is achieved, then the
next state shifts to sawnull. A match 1 is obtained if
bin(0)=bitstream(0). The number of CE assumed here is 7.
The input is reset and the clock. The query data may or
may not be equal with the reference data. If a match is in
CE1, then match is referred as match1 and its
corresponding output is out1. Similarly for CE2, CE3,
CE4, CE5, CE6, CE7 the match is match2, match3,

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International Journal of Emerging Technologies and Engineering (IJETE)

Volume 1 Issue 10, November 2014, ISSN 2348 8050

match4, match5, match6, match7 and its output is out2,

out3, out4, out5, out6 and out7 respectively.
The classifier reads the data from a separate data port and
has its own packet buffer for storing the headers of
incoming packet. All CE works paralley sharing the same
memory. The four outputs of CE are No Match, Match,
Rule ID, Packet ID. The sorter logic block registers the
Match, NoMatch, and RuleI D signals for a classified
packet to a chain of registers and multiplexers in series.
The register selected will depend on the packet ID
number. The Match, NoMatch, and RuleI D signals will
be registered to the output register if they are next in the
sequence of results to be outputted, and stored if not. All
stored results are shifted toward the output register each
time a result appears that is due to be outputted.
Verify matched pattern
Each CE produces an output. Thus, there are
seven CE that produces seven output individually. The
corresponding output represents the corresponding match.
For instance, if CEI produces out1, then its match id is
match1.
Perform action according to the matched data
For seven matches, there are seven final actions
given by Act(0), Act(1), Act(2), Act(3), Act(4), Act(5),
Act(6) reported from Action1, Action2, Action3, Action4,
Action5, Action6, Action7 when the case matchid is
1000000, 0100000, 0010000, 0001000, 0000100,
00000010. 0000001. If some other matched is found, then
report ***** with final action as ZZZ.

VI.

RESULTS AND DISCUSSION

The reference data is already given and the query

data is given as the input. The code of the program is
coded as such in the flow of the project. The
corresponding values of the SIP, DIP, SP, DP and PRO
are 10111100, 10110000, 1011, 1011 and 11 respectively.
The query data given here is 0010111. Since the query
data and the DIP are same, a rule match is found in 001
which represents the match2 after simulation. This value is
already given when forming the rule table. When the
query data is given as 11001111, no match is found and
hence the output zzz is obtained.

Fig2: Matching of data

Resource estimation
To estimate the resource, Xilinx PlanAhead is
used. This software helps in estimating the components
used for the program written in Xilinx. For this program,
328 registers, 311 LUT, 7 blocks of memory and 5 I/O are
used.

Fig3: Resource estimation

Fig1: Opertion of packet classification engine

Power estimation and power comparison

The parameters such as total-on-chip power,
junction temperature, and thermal margin are estimated.
The clock power used is 7mW. The power of
I/O and
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International Journal of Emerging Technologies and Engineering (IJETE)

Volume 1 Issue 10, November 2014, ISSN 2348 8050

block memory is 3mW and 4mW respectively. Thus the

total power consumed 57mW is obtained by adding all the
amount of power consumed

without which this would have not been possible. We wish

to take this opportunity to express our gratitude to all, who
helped me directly or indirectly to complete this paper.

REFERENCES

Fig4: Estimation of power

VII.

CONCLUSION

Packet classification is usually limited to use by

routers at the edge of a network where line speeds do not
typically exceed a few gigabit per second. This paper
introduced a new algorithm and packet classification
hardware accelerator with enough processing power to
allow packet classification to be implemented at the core
of a network, thus improving security. The classifier
consumed only 57mW when classifying the packets. This
is low when compared to other classifiers. The classifier
ran a modified version of the Hyper Cuts algorithm that
has been modified so that it is better suited to hardware
implementation. These modifications included changing
the cutting scheme so that the need for slow and logic
intensive floating point division is removed when
classifying a packet. This was done by replacing the
region compaction scheme used by HyperCuts algorithm.

VIII.

FUTURE WORK

When the packet is classified using different types

of algorithm, maximum amount of power from 9-15 Watts
is consumed. This will be a great impact in the real time
applications. So a method called Finite state machine can
be introduced to reduce these effects. It uses a same
classification data memory because the method does not
involve overwriting existing data. So the amount of
memory can also be reduced.

IX. ACKNOWLEDGEMENT
Apart from the efforts taken, the success of any
work depends largely on the encouragement and
guidelines of many others. We take this opportunity to
express our gratitude to the people who have been
instrumental in the successful completion of this work. We
would like to extend our sincere thanks to all of them We
owe a sincere prayer to the LORD ALMIGHTY for His
kind blessings and giving me full support to do this work,

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